JP2009217908A - 不揮発性半導体記憶装置 - Google Patents
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Abstract
【解決手段】互いに交差する第1及び第2の配線、並びにこれら第1及び第2の配線の各交差部に配置された電気的書き換え可能で抵抗値をデータとして不揮発に記憶する可変抵抗素子からなるメモリセルを備えたメモリセルアレイと、第1及び第2の配線を介してメモリセルにデータの書き込みに必要な電圧を印加するデータ書き込み回路と、データの書き込み時にメモリセルに流れる電流値を所定のリミット値に制限する電流リミット回路とを備えた。
【選択図】図11
Description
以下、図面を参照して、この発明の第1の実施形態を説明する。
図1は、本発明の第1の実施形態に係る不揮発性メモリのブロック図である。
図2は、メモリセルアレイ1の一部の斜視図、図3は、図2におけるI−I′線で切断して矢印方向に見たメモリセル1つ分の断面図である。
次に、このように構成された不揮発性半導体メモリの動作について説明する。
次に、具体的なReRAMの読み出し/書き込み回路とその動作を説明する。
図13は、本発明の第2の実施形態に係る電荷分配回路を示す回路図である。この電荷分配回路は、選択セルをセットするのに必要且つ十分な電荷量を選択セルに供給する制御を行うようにしたもので、電荷供給量を制限することによってセット動作の際の再リセットを防止するものである。
図14は、書き込みバッファ102によるリセット時の消去電圧VERA、メモリセルMCの抵抗値変化、及びメモリセルMCの電流値変化を示す動作波形図である。図14(1)には、正常動作時の動作波形が示されている。2V程度の消去電圧VERAを選択セルに1μs程度印加すると、選択セルの抵抗値は、低抵抗状態から高抵抗状態へと変化する。電流は、最初は低抵抗であるため大きいが、選択セルの抵抗値が上昇するに従って電流値が減少する。
図17は、本発明の第4の実施形態で使用可能なで電圧クランプ回路を示す回路図である。第4の実施形態では、パルスジェネレータからのセルに対する消去電圧VERAを制限することで再セットを防止する。
本発明は、上述した実施形態に限定されるものではない。
Claims (5)
- 互いに交差する第1及び第2の配線、並びにこれら第1及び第2の配線の各交差部に配置された電気的書き換え可能で抵抗値をデータとして不揮発に記憶する可変抵抗素子からなるメモリセルを備えたメモリセルアレイと、
前記第1及び第2の配線を介して前記メモリセルにデータの書き込みに必要な電圧を印加するデータ書き込み回路と、
前記データの書き込み時に前記メモリセルに流れる電流値を所定のリミット値に制限する電流リミット回路と
を備えたことを特徴とする不揮発性半導体記憶装置。 - 互いに交差する第1及び第2の配線、並びにこれら第1及び第2の配線の各交差部に配置された電気的書き換え可能で抵抗値をデータとして不揮発に記憶する可変抵抗素子からなるメモリセルを備えたメモリセルアレイと、
前記第1及び第2の配線を介して前記メモリセルにデータの書き込みに必要な電圧を印加するデータ書き込み回路と、
前記データの書き込み時に前記メモリセルに供給する電荷量を所定のリミット値に制限する電荷リミット回路と
を備えたことを特徴とする不揮発性半導体記憶装置。 - 互いに交差する第1及び第2の配線、並びにこれら第1及び第2の配線の各交差部に配置された電気的書き換え可能で抵抗値をデータとして不揮発に記憶する可変抵抗素子からなるメモリセルを備えたメモリセルアレイと、
前記第1及び第2の配線を介して前記メモリセルにデータの消去に必要な電流を供給するデータ消去回路と、
前記データの消去時に前記メモリセルに印加される電圧値を所定のリミット値に制限する電圧リミット回路と
を備えたことを特徴とする不揮発性半導体記憶装置。 - 前記所定のリミット値はチップ毎にトリミング可能であることを特徴とする請求項1〜3のいずれか1項記載の不揮発性半導体記憶装置。
- 前記リミット値は、前記メモリセルの消去に必要な値よりも小さいことを特徴とする請求項1又は2記載の不揮発性半導体記憶装置。
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JP2008061753A JP4719233B2 (ja) | 2008-03-11 | 2008-03-11 | 不揮発性半導体記憶装置 |
US12/401,200 US7978497B2 (en) | 2008-03-11 | 2009-03-10 | Nonvolatile semiconductor memory device |
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Cited By (13)
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JP2011108327A (ja) * | 2009-11-18 | 2011-06-02 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2011175716A (ja) * | 2010-02-25 | 2011-09-08 | Toshiba Corp | 半導体記憶装置 |
JP2011198430A (ja) * | 2010-03-23 | 2011-10-06 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2011204289A (ja) * | 2010-03-24 | 2011-10-13 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2011243265A (ja) * | 2010-05-20 | 2011-12-01 | Toshiba Corp | 不揮発性記憶装置及びその駆動方法 |
JP2012059321A (ja) * | 2010-09-09 | 2012-03-22 | Toshiba Corp | 抵抗変化メモリ装置 |
JP2012169023A (ja) * | 2011-02-16 | 2012-09-06 | Nec Corp | 半導体装置 |
US8498141B2 (en) | 2010-03-24 | 2013-07-30 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device |
US8699262B2 (en) | 2010-10-12 | 2014-04-15 | Hitachi, Ltd. | Semiconductor memory device |
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US9105332B2 (en) | 2012-03-15 | 2015-08-11 | Panasonic Intellectual Property Management Co., Ltd. | Variable resistance nonvolatile memory device |
US9601196B2 (en) | 2014-09-17 | 2017-03-21 | Kabushiki Kaisha Toshiba | Resistive change memory including current limitation circuit |
US10706925B2 (en) | 2014-11-06 | 2020-07-07 | Sony Semiconductor Solutions Corporation | Non-volatile memory device and method of controlling non-volatile memory device |
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JP4846813B2 (ja) * | 2009-03-12 | 2011-12-28 | 株式会社東芝 | 不揮発性半導体記憶装置 |
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US8437174B2 (en) * | 2010-02-15 | 2013-05-07 | Micron Technology, Inc. | Memcapacitor devices, field effect transistor devices, non-volatile memory arrays, and methods of programming |
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US8891277B2 (en) | 2011-12-07 | 2014-11-18 | Kabushiki Kaisha Toshiba | Memory device |
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US10163503B2 (en) | 2015-11-16 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM array with current limiting element to enable efficient forming operation |
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