JP2009206429A - Storage - Google Patents

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JP2009206429A
JP2009206429A JP2008049823A JP2008049823A JP2009206429A JP 2009206429 A JP2009206429 A JP 2009206429A JP 2008049823 A JP2008049823 A JP 2008049823A JP 2008049823 A JP2008049823 A JP 2008049823A JP 2009206429 A JP2009206429 A JP 2009206429A
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Japan
Prior art keywords
electrodes
formed
semiconductor package
signal
semiconductor
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Pending
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JP2008049823A
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Japanese (ja)
Inventor
Tetsuya Yamamoto
哲也 山本
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Toshiba Corp
株式会社東芝
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Application filed by Toshiba Corp, 株式会社東芝 filed Critical Toshiba Corp
Priority to JP2008049823A priority Critical patent/JP2009206429A/en
Publication of JP2009206429A publication Critical patent/JP2009206429A/en
Application status is Pending legal-status Critical

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage which can be excellent in shock resistance and temperature cycle resistance, and whose reliability can be improved. <P>SOLUTION: The storage (SSD100) includes a semiconductor package 40 and a mounting substrate 30. The semiconductor package 40 includes a semiconductor chip 5 on which a nonvolatile semiconductor is formed, a resin sealing body 10 which seals the semiconductor chip 5, and lattice electrodes (a group electrode, solder balls 20) which are arranged in lattice shape on the rear surface of the resin sealing body 10. The mounting substrate 30 includes a bonding conductor 31 bonded to the solder ball 20, and has the semiconductor package 40 mounted thereon. The solder ball 20 includes a signal electrode 20A which is formed in the central region of the arrangement, and a dummy electrode 20B which is formed outside the signal electrode 20A. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a storage medium including a semiconductor package for resin-sealing a semiconductor chip and a mounting substrate for mounting the semiconductor package.

  In a storage medium including such a semiconductor package and a mounting substrate on which the semiconductor package is mounted, further reduction in size and capacity is desired. As one of the methods for realizing small size and large capacity, it has been proposed to use a semiconductor package of BGA (Ball Grid Array) type or LGA (Land Grid Array) type.

  The BGA type and LGA type semiconductor packages are provided with electrodes on the back surface of the resin sealing body, and like the TSOP (Thin Small Outline Package) type, electrodes (leads) are formed from the peripheral portion (end surface) of the resin sealing body. ) Does not extend, the resin sealing bodies of adjacent packages can be placed close to each other when mounted on the mounting substrate, and the density of the semiconductor chip and the size of the storage medium can be reduced. . Conventionally, in order to further increase the density of semiconductor chips, an MCP (Multi Chip Package) type semiconductor package in which a plurality of semiconductor chips are stacked and sealed in one package has been proposed.

  In such a semiconductor package, the density of the semiconductor chip and the size of the storage medium can be reduced, while a large number of electrodes are disposed on the back surface of the resin sealing body. A large number of electrodes formed on the back surface of the resin sealing body are generally formed in a rectangular grid shape, but the electrodes formed at the corners of the array are not used for signal transmission and reception for the purpose of improving reliability. This is because cracks are likely to occur at the corners of the package (see, for example, Patent Document 1).

JP 2007-207397 A

  However, further high reliability is desired for a storage medium on which such a semiconductor package is mounted. Particularly in recent years, a storage medium equipped with a nonvolatile semiconductor memory has been used in various places such as a large computer, a personal computer, a home appliance, a mobile phone, and more recently as a replacement for a hard disk drive (HDD). It is considered. Therefore, a highly reliable material excellent in impact resistance and temperature cycle resistance is required.

  An object of the present invention is to provide a highly reliable storage medium having excellent impact resistance and temperature cycle resistance.

  According to one aspect of the present invention, a semiconductor chip, a resin sealing body for sealing the semiconductor chip, a semiconductor package having a plurality of electrodes arrayed in a lattice pattern on the back surface of the resin sealing body, and a plurality of A mounting substrate having a bonding conductor to be bonded to the electrode and mounting a semiconductor package, and the plurality of electrodes include a signal electrode formed in a central region of the array, a dummy electrode formed outside the signal electrode, Can be provided.

  According to the present invention, it is possible to provide a highly reliable storage medium having excellent impact resistance and temperature cycle resistance.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

[Embodiment 1]
FIG. 1 is a perspective view of a storage medium according to Embodiment 1 of the present invention. An SSD (Solid State Drive) 100 as a storage medium is a module configured by mounting a plurality of semiconductor packages on a mounting board (motherboard) 30 which is a rectangular small board having a thickness of 3 mm. The plurality of semiconductor packages are BGA type semiconductor packages each of which encapsulates a semiconductor chip, and includes eight semiconductor packages 40 including a NAND flash memory as a nonvolatile memory and a drive control circuit as a controller. The semiconductor package 50 includes a semiconductor package 60 incorporating a DRAM as a volatile memory, and a semiconductor package 70 incorporating a power supply circuit. A connector 80 is provided on one side of the short edge of the outer peripheral edge of the mounting substrate 30.

  The external dimensions of the mounting substrate 30 are substantially the same as the external dimensions of a 1.8-inch HDD in accordance with the HDD standards. The connector 80 is also produced based on the HDD standard, and the same high-speed serial ATA as that of the HDD is adopted for the interface. The semiconductor package 40 with a built-in NAND flash memory has an outer dimension of 14 × 18 mm and a maximum height of 1.46 mm from the mounting substrate 30. This height is 2.35 mm, which is the height of two stacked TSOP type semiconductor packages containing four semiconductor chips (that is, the height when eight stacked semiconductor chips are realized in the TSOP type). (The TSOP type semiconductor package is currently limited to resin sealing of four semiconductor chips).

  FIG. 2 is a cross-sectional view of a portion where the semiconductor package 40 incorporating the NAND flash memory of the SSD 100 shown in FIG. 1 is mounted. The semiconductor package 40 includes eight semiconductor chips 5 on which NAND flash memories are formed, a substantially flat resin sealing body 10 for resin-sealing these semiconductor chips 5, and a lattice pattern on the back surface of the resin sealing body 10. It is comprised from the solder ball 20 as a grid | lattice-like electrode formed by arranging in (grid shape). The NAND flash memory employs a multi-value technology that records “00”, “01”, “10”, or “11” for each memory cell, and the capacity per element is higher than that of the binary technology. Has also been raised. One semiconductor chip 5 is formed with a NAND flash memory capable of storing 2 GB, and the entire SSD 100 can store 128 GB. The number of semiconductor chips is not limited to eight, and can be changed as appropriate according to the capacity of the storage medium.

  The resin sealing body 10 includes a wiring board (interposer) 7, a sealing resin 8, and bonding wires 9. The wiring board 7 has the semiconductor chip 5 mounted on the first surface (front surface), and the solder balls 20 are formed on the second surface (back surface) facing the first surface. The sealing resin 8 seals the eight semiconductor chips 5 on the first surface side of the wiring substrate 7. The bonding wire 9 electrically connects the semiconductor chip 5 and the wiring board 7. The solder ball 20 is soldered to a bonding conductor 31 formed as a wiring pattern on the mounting substrate 30.

  FIG. 3 is a view showing a state in which the solder balls 20 are arranged vertically and horizontally, and shows a state in which the semiconductor package 40 is viewed from the second surface side of the wiring board 7. The solder balls 20 are formed on the second surface of the wiring board 7 so as to be aligned vertically and horizontally. In addition, the solder balls 20 are arranged in a substantially rectangular shape with the center coincident with the center of the wiring board 7, and approximately 16 pieces are arranged in the long side direction of the wiring board 7 and about 12 pieces are arranged in the short side direction ( In the drawing, a portion surrounded by a one-dot chain line) is further formed, and in the four corners of the array, one or two rows of solder balls 20 are additionally formed on the outside. In addition, the solder balls 20 are not provided in the 2 × 6 region (portion surrounded by a two-dot chain line) in the center of the wiring substrate 7 in the arrangement.

  The solder balls 20 formed in this way are composed of a signal electrode 20A indicated by a black circle in the figure formed in a predetermined area (hereinafter referred to as a central area) in the center of the arrangement indicated by a dotted line in the figure, and an outside of the signal electrode 20A. And a dummy electrode 20B indicated by a white circle in the figure. The central region in which the signal electrode 20A is formed is a region having a width of about 1/3 of the entire width in the arrangement long side direction, and the signal electrode 20A is mixed with the dummy electrode 20B in the central region. On the other hand, a part of the dummy electrode 20B is formed in a mixed manner with the signal electrode 20A in the central region as described above, but the remaining dummy electrodes spread in both directions of the central region and remain on the wiring board. An array is formed only with dummy electrodes so as to occupy the region.

  The signal electrode 20A is an electrode used for transmitting and receiving signals, and functions as, for example, a data pin, a command pin, a power supply pin (ground, Vdd, etc.), and a clock pin. On the other hand, the dummy electrode 20 </ b> B is not used for transmitting / receiving signals, but is used for fixing and supporting the semiconductor package 40. Here, for example, 224 solder balls 20 are formed, of which 30 are signal electrodes 20A and 194 are dummy electrodes 20B. That is, the ratio of the number of signal electrodes 20A and dummy electrodes 20B is about 2 to 13, and the ratio of the number of signal electrodes 20A to the whole is about 13%.

  According to the impact resistance and temperature resistance tests of the inventors, the joint of the grid-like electrode joined to the mounting substrate by soldering or the like is from the center due to external stress such as impact or due to solder fatigue due to temperature cycling. It was found that cracks were generated from those having a large distance, that is, those located outside the array, and the cracks tended to gradually progress toward the inside. Therefore, in this embodiment, the signal electrode 20A is formed on the center side of the grid-like array, and the dummy electrode 20B is formed outside the array, thereby increasing the time until the crack is generated in the signal electrode 20A. Improves impact resistance and temperature cycle resistance. In addition, cracks are likely to occur first at the four corners of the array as a position having a large distance from the center. For this reason, in the present embodiment, by further forming one or two rows of dummy electrodes 20B outside the array at the four corners of the array, the adhesion at the corners is further enhanced. Improves impact resistance and temperature cycle resistance.

  In order to obtain the above effect, it is effective to sufficiently increase the number of dummy electrodes 20B arranged around the signal electrode 20A with respect to the signal electrode 20A. As in the present embodiment, when the number of signal electrodes 20A is about 30 (about 13%) among all 224 electrodes, the effect of impact resistance and temperature cycle resistance can be obtained satisfactorily.

  Regarding the ratio of the signal electrode 20A to the total electrode, when the inventors adjusted the number of signal electrodes in the same 14 × 18 mm semiconductor package as in the present embodiment, the ratio of the number of signal electrodes is about 10%. Up to about% (for example, 22 out of 224), it was possible to obtain an effect that gradually increased as the signal electrode decreased. However, after that, even if the number of signal electrodes was further reduced, the effect was not significantly increased. In addition, when the experiment was conducted not only on the semiconductor package of 14 × 18 mm but also on other sizes, it was found that the same effect can be obtained at substantially the same ratio.

  Note that the solder balls 20 do not necessarily have to be arranged in a grid pattern at equal pitches in the vertical and horizontal directions, but are formed in irregular groups rather than at equal pitches (collective electrodes). May be. Further, the outer peripheral shape of the group may be a trapezoid or an ellipse as well as a square. In other words, by forming a signal electrode in a predetermined region of the collective center portion of the solder balls forming the group and forming a dummy electrode outside the signal electrode, an effect substantially similar to the above effect can be obtained. .

  A more detailed structure will be described. FIG. 4 is a partial enlarged sectional view showing a detailed structure of the semiconductor package 40. In detail, the wiring board 7 has a copper wiring pattern 13 formed on the surface of a core material 11 made of a resin material. The wiring substrate 7 is formed by attaching a copper foil to a plate-like core material 11 and etching the surface to form a copper wiring pattern 13. Further, a solder resist is formed on the surface for the purpose of preventing oxidation and maintaining insulation. 15 is coated. A through hole (not shown) is formed in the core material 11 according to the arrangement of the solder balls 20, and the wiring pattern 13 is formed so as to penetrate the through hole and be exposed to the second surface side of the wiring substrate 7. Has been. A solder ball 20 is formed on the wiring pattern 13 exposed from the core material 11 via nickel or aluminum electrolytic plating 17.

  The eight semiconductor chips 5 are fixed to each other by a die attach film 19 and stacked. The die attach film 19 is a mixture of epoxy and polyimide and serves as an adhesive. A bonding wire 9 extending from the semiconductor chip 5 is connected to the wiring pattern 13 at the end of the wiring substrate 7. The eight semiconductor chips 5 are stacked while being shifted little by little in order to facilitate the connection of the bonding wires 9. That is, the upper semiconductor chip 5 is stacked with a predetermined amount shifted to the side facing the wire 9 so that the other semiconductor chip 5 overlapping the upper side does not overlap the upper surface of the peripheral edge to which the bonding wire 9 is connected. ing. Each time two semiconductor chips 5 are stacked, wire bonding is performed, and this is repeated four times to stack eight. Thereafter, the sealing resin 8 is molded with a mold so as to cover the semiconductor chip 5 and the bonding wires 9.

  FIG. 5 is a diagram illustrating a state in which the bonding wire 9 is connected to the semiconductor chip 5 and illustrates a state in which the sealing resin 8 is removed as viewed from the arrow A side in FIG. The bonding wire 9 is connected to one side of each semiconductor chip 5. As can be seen in conjunction with FIG. 2, the two semiconductor chips 5 adjacent to each other in the stacking direction form a set so that the bonding wires 9 extending from each set do not overlap in the stacking direction of the semiconductor chip 5. It is connected in four places. By stacking and bonding the semiconductor chips 5 in this way, the working process is simplified and the package is downsized.

  In the SSD 100 according to the present embodiment configured as described above, the semiconductor chip 5 on which a nonvolatile semiconductor memory formed of a NAND flash memory is formed, the resin sealing body 10 for sealing the semiconductor chip, the resin sealing A semiconductor package 40 having solder balls 20 arranged in a grid pattern is mounted on the back surface of the stationary body 10. In this type of semiconductor package, unlike the TSOP type, the electrode (lead) does not extend in the direction along the substrate 30 from the peripheral edge (end face) of the resin sealing body 10. Therefore, when mounting on the mounting substrate 30, the resin sealing bodies 10 of adjacent packages can be densely arranged. Thereby, the ratio of the area which the resin sealing body 10 occupies with respect to the mounting board | substrate 30 can be enlarged, and the density increase of a semiconductor chip can be achieved by extension. Further, in the present embodiment, eight semiconductor chips are mounted on one semiconductor package 40 to further increase the density. Furthermore, the semiconductor package 40 of the present embodiment is a BGA type package and is excellent in thinning because a lead frame is not used when forming the resin sealing body 10.

  Furthermore, in the SSD 100 according to the present embodiment, the solder ball 20 includes the signal electrode 20A formed on the center side of the grid-like arrangement (in the region of about 1/3 of the central portion in the long side direction) and the outside of this region. Therefore, the impact resistance and temperature cycle resistance are promoted, and the reliability of the SSD 100 can be improved. Further, the semiconductor package 40 has 224 solder balls 20 including many dummy electrodes 20B, and the number thereof is far larger than the number of TSOP type electrodes (leads) of 46 of the same size. Therefore, the heat generated in the semiconductor chip 5 is favorably conducted to the mounting substrate 30 via the solder balls 20, thereby realizing a very excellent heat dissipation effect.

  FIG. 6 is a logarithmic graph comparing the mounting reliability of the BGA type semiconductor package 40 used in the SSD 100 of the present embodiment and the TSOP type semiconductor package conventionally used in the temperature cycle test. In the temperature cycle test, the temperature of the package was raised and lowered between −25 ° C. and 125 ° C. at intervals of 30 minutes, and the cumulative defect rate at that time was measured and compared. The horizontal axis indicates the number of cycles [number of times], and the vertical axis indicates the cumulative failure rate [%]. The triangular plot in the figure represents the number of cycles in which the TSOP type has a predetermined cumulative failure rate, and the black circle plot in the figure represents the number of cycles in which the BGA type has a predetermined cumulative failure rate. Yes. For example, when the number of cycles that reach a cumulative 1% defect rate is compared, the TSOP type semiconductor package reaches 467 cycles, while the BGA type semiconductor package 40 reaches 900 cycles. From these facts, it was proved that the semiconductor package 40 of the present embodiment has an extended life of about 1.93 times.

  In the present embodiment, in a semiconductor component disposed in the peripheral portion of the mounting substrate 30, for example, a semiconductor package 70 incorporating a power supply circuit, the solder ball 20 is interposed between the resin sealing body 10 and the mounting substrate 30. Filling an underfill agent (resin sealant) so as to seal is effective in improving impact resistance and temperature cycle resistance. With this configuration, the fixing force between the resin sealing body 10 and the mounting substrate 30 is increased, and the solder ball 20 is protected from external stress, and the occurrence of cracks is further suppressed, so the reliability of the SSD is further improved. To do.

  On the other hand, of the semiconductor packages 40, 50, 60, the semiconductor package 40 with a built-in NAND flash memory that is closely arranged on the mounting substrate 30 does not use an underfill agent, and has a corner portion as described above. It is effective to reinforce by increasing the number of dummy electrodes.

[Embodiment 2]
FIG. 7 is a diagram showing an arrangement of signal electrodes and dummy electrodes of the storage medium according to the second embodiment of the present invention. Solder balls 120 of the present embodiment are divided into signal electrodes 120A indicated by black circles in the figure formed on the center side of the grid-like arrangement and dummy electrodes 120B indicated by white circles in the figure formed outside the arrangement. There are 224 solder balls 120 in this embodiment, of which 30 are signal electrodes 120A and 194 are dummy electrodes 120B. The signal electrode 120A is formed in a region of about 1/3 of the central portion in both the long side direction and the short side direction of the array.

  The arrangement of the signal electrodes 120 </ b> A of the present embodiment is line symmetric with respect to the center line L on the plane of the second surface of the wiring board 7. By arranging them symmetrically with respect to the center line in this way, cracks are not easily generated in any one of the halves, and they are averaged, so that the impact resistance and temperature cycle resistance are further improved. Further, as in the present embodiment, the effect is further improved when the dummy electrode 120B is arranged so as to surround the signal electrode 120A over the entire circumference.

[Embodiment 3]
FIG. 8 is a diagram showing an arrangement of signal electrodes and dummy electrodes of the storage medium according to the third embodiment of the present invention. Solder balls 220 of the present embodiment are divided into signal electrodes 220A indicated by black circles in the figure formed on the center side of the grid-like arrangement and dummy electrodes 220B indicated by white circles in the figure formed outside the arrangement. There are 224 solder balls 220 in this embodiment, of which 30 are signal electrodes 220A and 194 are dummy electrodes 220B. The signal electrode 220A is formed in an approximately square area rotated 45 ° at the center with respect to an array having a rectangular shape as a whole.

  The arrangement of the signal electrodes 220 </ b> A of the present embodiment is point symmetric with respect to the center point P on the plane of the second surface of the wiring board 7. By making point symmetry with respect to the center in this way, cracks are not easily generated at any one of the portions, and an effect substantially similar to that of the second embodiment can be obtained. In addition, as in the present embodiment, the area where the signal electrode 220A is formed is a substantially square area rotated by 45 ° at the center, so that the signal electrode 220A is farthest from the corner where cracks are likely to occur. It is effective for improving impact resistance and temperature cycle resistance.

[Embodiment 4]
FIG. 9 is a diagram showing an arrangement of signal electrodes and dummy electrodes of the storage medium according to the fourth embodiment of the present invention. The solder balls 320 of the present embodiment are divided into signal electrodes 320A indicated by black circles in the figure formed on the center side of the grid-like arrangement and dummy electrodes 320B indicated by white circles in the figure formed outside the arrangement. There are 224 solder balls 320 also in this embodiment, of which 48 are the signal electrodes 320A and 176 are the dummy electrodes 320B. That is, the number of signal electrodes 320A is increased from that in the above embodiment. The central region where the signal electrode 320A is formed is a region having a width that is approximately ½ of the entire arrangement width.

  In the semiconductor package, the number of signal electrodes is expected to increase in the near future in response to further multilayering of semiconductor chips. However, as described in the first embodiment, in order to obtain the effect of impact resistance and temperature cycle resistance by the dummy electrode, if the number of pins of the dummy electrode surrounding the signal electrode is reduced more than necessary with respect to the signal electrode. Not valid. As in the present embodiment, when the number of signal electrodes 320A is 48 (about 21% of the total) out of all 224 electrodes, the central region where the signal electrodes 320A are formed is arranged in the entire array width. In the case of a region having a width of about ½, a good effect was obtained.

  Then, when the inventors repeated the experiment while increasing the ratio of the signal electrodes, until the number of the signal electrodes was 66 (about 30%), the effect of improving the impact resistance and the temperature resistance cycle was improved. Although it could be obtained, when it was more than that, the impact resistance and the temperature cycling effect were not obtained remarkably. Further, when the central region where the signal electrode is formed is set to 1/2 or more of the entire arrangement width, the effect is remarkably reduced. In view of the above, in comparison with the experimental results of the first embodiment, it was found that a region having a width of about 1/3 to 1/2 of the entire width is appropriate for the region where the signal electrode is formed. For example, 5.6 / 14.4≈1 / 3 (example in FIG. 3), 7.2 / 14.4≈1 / 2 (example in FIG. 9), and the like are appropriate. Further, it was found that the ratio of the number of signal electrodes among all the electrodes is suitably less than 30%, and desirably less than 20%. Furthermore, it was found that the effect can be obtained efficiently when the ratio of the number of signal electrodes is 10% or more and less than 30%. The relationship between the ratio of the signal electrodes and the effect is not limited to the 14 × 18 mm semiconductor package, and it has been experimentally found that the relationship is substantially the same for other sizes.

  In the SSDs of the first to fourth embodiments, a BGA type semiconductor package is used for the purpose of increasing the density of the semiconductor chip. However, in order to achieve the same purpose, not only the BGA type but also an LGA (Land) (Grid Array) type semiconductor package may be used. In the LGA type semiconductor package, a fine flat electrode called a land is formed as a grid electrode instead of a solder ball on the back surface of the resin sealing body. Other configurations are the same as those of the BGA type. Then, the pins corresponding to the respective electrodes are pressed against a socket having a sword-like shape in which the pins are arranged in a lattice shape, and are mounted on the mounting board.

  According to the experiments by the inventors, even in this LGA type semiconductor package, the bonding failure of the lattice-shaped electrode joints occurs in order from the largest distance from the center due to external stress such as impact. Then, this bonding failure gradually progresses to the inner electrode as time passes. Therefore, also in this LGA type semiconductor package, the durability against external stress can be improved by arranging the signal electrodes and the dummy electrodes in the same concept as in the first to fourth embodiments.

  Furthermore, according to the inventors, not only the BGA type and LGA type semiconductor packages, but a package having a plurality of electrodes arranged on the back surface of the resin encapsulant, the joint portion may be impact or the like. Since the bonding failure occurs in order from the farthest from the center due to the external stress, etc., by forming the arrangement of the signal electrode and the dummy electrode based on the same idea as in the first to fourth embodiments, the external stress The durability with respect to can be improved.

  In addition, this invention is not limited to the above-mentioned embodiment, In the range which does not deviate from the summary, each component can be changed and embodied. Various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above-described embodiments. For example, some constituent elements may be deleted from all the constituent elements disclosed in the above-described embodiments, or constituent elements of different embodiments may be appropriately combined.

1 is a perspective view of a storage medium according to Embodiment 1 of the present invention. Sectional drawing of the part which mounts the semiconductor package of SSD. FIG. 3 shows an arrangement of signal electrodes and dummy electrodes of the storage medium in the first embodiment. The partial expanded sectional view which shows the detailed structure of a semiconductor package. The figure which shows a mode that a bonding wire is connected to a semiconductor chip. The figure which shows the logarithm graph which compared the mounting reliability by the temperature cycle test of a BGA type semiconductor package and a TSOP type semiconductor package. FIG. 6 shows an arrangement of signal electrodes and dummy electrodes of the storage medium of the second embodiment. FIG. 9 shows an arrangement of signal electrodes and dummy electrodes of the storage medium of the third embodiment. FIG. 10 shows an arrangement of signal electrodes and dummy electrodes of the storage medium of the fourth embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 5 ... Semiconductor chip, 7 ... Wiring board, 8 ... Sealing resin, 9 ... Bonding wire, 10 ... Resin sealing body, 20A, 120A, 220A, 320A ... Solder ball (signal electrode), 20B, 120B, 220B, 320B DESCRIPTION OF SYMBOLS ... Solder ball (dummy electrode), 30 ... Mounting board, 31 ... Joining conductor, 40 ... Semiconductor package with built-in NAND flash memory, 50 ... Semiconductor package with built-in drive control circuit, 60 ... Semiconductor package with built-in DRAM, 70 ... Power supply Semiconductor package with built-in circuit, 80... Connector, 100... SSD (storage medium).

Claims (5)

  1. A semiconductor package having a semiconductor chip, a resin sealing body for sealing the semiconductor chip, and a plurality of electrodes arranged in a lattice pattern on the back surface of the resin sealing body;
    A mounting substrate having a bonding conductor for bonding to the plurality of electrodes and mounting the semiconductor package;
    The plurality of electrodes include a signal electrode formed in a central region of the array and a dummy electrode formed outside the signal electrode.
  2. The storage medium according to claim 1, wherein the central region in which the signal electrode is formed has a region having a width of about 1/3 to 1/2 of the entire width of the array.
  3. The storage medium according to claim 1, wherein a ratio of the number of the signal electrodes among the plurality of electrodes is less than 30%, desirably less than 20%.
  4. The arrangement of the signal electrodes is line symmetric with respect to a center line of an array formed by the electrodes or point symmetric with respect to a center of the array. The storage medium described.
  5. The storage medium according to claim 1, wherein the dummy electrode is formed so as to surround the signal electrode over the entire circumference.
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