JP2009177575A - Reference clock signal generation device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device for preventing picture quality deterioration or sound quality deterioration caused by a jitter from being conspicuous as much as possible in the case of using a method having a jitter generation factor as a method for obtaining a reference clock signal with a prescribed frequency necessary for digital video signal processing. <P>SOLUTION: It is detected whether signal levels of an image signal and a sound signal are in a low-level period or not, and in the period when the signal levels are not low, the frequency division rate of a feedback frequency divider 5 as a configuring element of a PLL circuit which generates a clock signal is set to a fixed value, and in the period when the signal levels are low, the frequency division rate of the feedback frequency divider 5 is varied, and when these periods are integrated in a long period of time which is sufficiently longer than each period, a reference clock with a prescribed frequency is generated as a whole. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an apparatus for generating a reference clock signal used when digital signal processing is performed on a video signal or an audio signal.

  When digital signal processing including A / D conversion processing and D / A conversion processing is performed on video signals and audio signals, a reference clock signal is required. The reference clock signal is generally generated using a PLL (Phase locked loop) circuit.

  The PLL circuit includes a feedback frequency divider, a phase comparator, a filter, a voltage controlled oscillator (VCO), and the like. As is well known, the PLL circuit is a circuit that generates an output clock signal having a frequency obtained by multiplying the frequency of the input clock signal by P when the frequency dividing ratio of the feedback frequency divider is P (P is a natural number).

There are various conventional techniques using a PLL circuit.
For example, Patent Document 1 relates to a conventional technique using a PLL circuit for generating a reference clock signal used when A / D converting a video signal.

Patent Document 2 relates to a conventional technique for suppressing jitter generated in a PLL circuit.
Japanese Patent No. 2705588 Japanese Patent No. 3514255

If a PLL circuit is used, it is possible to generate a reference clock signal having a frequency N times that of the input clock signal. Therefore, the PLL circuit can be said to be a multiplier for frequency.
A reference clock generator can be configured by using a crystal oscillator that oscillates itself and generates an oscillation clock signal of a predetermined frequency, this multiplier (PLL circuit), and a frequency divider that is a divider for the frequency. .

  This reference clock generating device can generate a reference clock signal having an arbitrary frequency to some extent by multiplying and dividing the oscillation frequency of the crystal oscillator by using a PLL circuit and a frequency divider.

  When the frequency of the reference clock signal required for digital signal processing is obtained as an integer value from the oscillation frequency of the crystal oscillator described above, the multiplication coefficient of the PLL circuit, and the division coefficient of the frequency divider, the jitter is excellent. A reference clock signal can be obtained. This is because the value of P, which is a multiplication coefficient of the PLL circuit, can be fixed, so that the design of the PLL circuit can be optimized so that unnecessary jitter does not occur in the reference clock signal.

  Therefore, in the digital signal processing using the reference clock signal generated by the reference clock generation apparatus including the optimized PLL circuit as described above, image quality deterioration and sound quality deterioration due to jitter of the reference clock signal hardly occur.

  However, in practice, the frequency of the reference clock signal required for digital signal processing is determined from the oscillation frequency of the crystal oscillator, the multiplication factor of the PLL circuit, and the division factor of the frequency divider due to hardware scale and cost constraints. , May not be obtained with integer values well. Two typical examples of the factors will be described below.

  First, since the output frequency of the VCO cannot physically exceed several hundred MHz, the upper limit can be set in the setting range of the division ratio of the feedback divider that divides the output frequency of the VCO. This is because the frequency resolution of the signal is limited. Another reason is that a very high accuracy of ± 30 ppm or less is required for a reference clock signal used in, for example, MPEG (Moving Picture Experts Group) processing in digital signal processing.

  In such a case, for example, a method of adaptively changing the frequency division ratio P (that is, the multiplication coefficient) of the feedback frequency divider of the PLL circuit is generally used. That is, the frequency of the output signal at a certain point is slightly deviated around the desired frequency, but the frequency division ratio P is controlled so that the desired frequency is obtained as a whole when integrating on the time axis. It is a technique.

  However, this method cannot avoid the occurrence of jitter at the time when the frequency division ratio is changed. Therefore, there is a problem that image quality deterioration and sound quality deterioration due to the jitter occur.

  Therefore, in view of the above problems, the present invention uses a technique having a jitter generation factor that adaptively changes the setting of a frequency division ratio and the like in order to obtain a reference clock signal having a desired frequency. Even in such a case, an object of the present invention is to provide a reference clock signal generation device capable of making image quality degradation and sound quality degradation caused by this jitter as inconspicuous as possible.

In order to solve the above problems, the present invention provides the following apparatuses.
(1) Multiplication / division using at least a multiplier that multiplies the first predetermined frequency of the input clock signal by a multiplication coefficient N (N is a natural number) and a divider that divides the frequency by a division coefficient M (M is a natural number). In a reference clock signal generation device that generates a reference clock signal having a second predetermined frequency necessary for executing predetermined digital video signal processing,
In a feedback frequency divider used in a PLL circuit constituting the multiplier, frequency division ratio control means for controlling a frequency division ratio that is a value for determining the multiplication coefficient N;
The digital video signal processing target video signal is received as an input, and a luminance level of the video signal or a level of a signal obtained by filtering at least one of a vertical line component and a horizontal line component from the video signal is determined. Video pattern detection means for detecting whether or not a predetermined first threshold value or less;
Have
The frequency division ratio control means includes:
When the reference clock signal having the second predetermined frequency cannot be generated even by multiplication and division with the multiplication coefficient N and the division coefficient M as fixed values,
In the first period in which the video pattern detection means detects that the video signal has exceeded the first threshold, the frequency of the output clock signal of the reference clock signal generator is a value close to the second predetermined frequency. A first division ratio that is a fixed value such that the division ratio is controlled by the feedback frequency divider so that the division ratio becomes the determined first division ratio;
In the second period in which the video pattern detection means detects that the video signal is equal to or lower than the first threshold, the first period depends on the control status of the feedback frequency divider up to that time. When the frequency of the output clock signal is integrated within a predetermined period that is sufficiently longer than the period and the second period, the frequency of the output clock signal is equivalent to the second predetermined frequency. A second frequency division ratio obtained by correcting a frequency shift amount between the frequency obtained by the frequency division ratio of 1 and the second predetermined frequency is calculated, and the feedback is performed so that the calculated second frequency division ratio is obtained. Means for controlling the frequency divider,
A reference clock signal generator characterized by the above.
(2) Multiplication / division using at least a multiplier that multiplies the first predetermined frequency of the input clock signal by a multiplication coefficient N (N is a natural number) and a divider that divides the frequency by a division coefficient M (M is a natural number). In a reference clock signal generation device that generates a reference clock signal having a second predetermined frequency necessary for executing predetermined digital audio signal processing,
In a feedback frequency divider used in a PLL circuit constituting the multiplier, frequency division ratio control means for controlling a frequency division ratio that is a value for determining the multiplication coefficient N;
The level of a signal obtained by receiving the digital audio signal processing target audio signal as an input and extracting at least one of a volume level of the audio signal or a single tone component, a chord component, or a high frequency component from the audio signal by filtering. Audio pattern detection means for detecting whether or not is equal to or less than a first threshold value set in advance;
Have
The frequency division ratio control means includes:
When the reference clock signal having the second predetermined frequency cannot be generated even by multiplication and division with the multiplication coefficient N and the division coefficient M as fixed values,
In a first period in which the audio pattern detection means detects that the audio signal has exceeded the first threshold, the frequency of the output clock signal of the reference clock signal generator is a value close to the second predetermined frequency. A first division ratio that is a fixed value such that the division ratio is controlled by the feedback frequency divider so that the division ratio becomes the determined first division ratio;
The second period in which the audio pattern detection unit detects that the video signal is equal to or less than the first threshold is determined according to the control status of the feedback frequency divider up to that time. When the frequency of the output clock signal is integrated within a predetermined period that is sufficiently longer than the period and the second period, the frequency of the output clock signal is equivalent to the second predetermined frequency. A second frequency division ratio obtained by correcting a frequency shift amount between the frequency obtained by the frequency division ratio of 1 and the second predetermined frequency is calculated, and the feedback is performed so that the calculated second frequency division ratio is obtained. Means for controlling the frequency divider,
A reference clock signal generator characterized by the above.

  According to the present invention, even when a technique having a jitter generation factor is used to adaptively change the setting of the frequency division ratio or the like in order to obtain a reference clock signal having a desired frequency, It is possible to make the image quality degradation and sound quality degradation caused by the image as inconspicuous as possible.

  In addition, according to the present invention, since a large-scale circuit necessary for suppressing jitter of the reference clock signal is not required, it is possible to suppress an increase in cost.

  Next, the best mode (Example) for carrying out the present invention will be described.

First, Example 1 will be described.
FIG. 1 is a block diagram illustrating the configuration of the first embodiment.
In this embodiment, an input stage divider 1, a phase comparator 2, a filter 3, a VCO 4, a feedback divider 5, a first output stage divider 6, a second output stage divider 7, and a division ratio control. And the image pattern detection unit 9 and the like.

The phase comparator 2, the filter 3, the VCO 4, and the feedback frequency divider 5 constitute a PLL circuit.
The input stage frequency divider 1 receives an oscillation clock signal having a predetermined frequency Fref generated by a crystal oscillator (not shown) as an input, divides the oscillation clock signal by a predetermined frequency division ratio, and generates a divided clock signal. Generate.

The phase comparator 2 generates a phase difference signal corresponding to a phase difference between a divided clock signal generated by the input stage divider 1 and a feedback divided clock signal 6 that is an output signal of a feedback divider 5 described later. Generate.
The filter 3 is a so-called loop filter for compensating the stability of the PLL circuit and suppressing jitter. The input phase difference signal is mainly attenuated by a high frequency component by the filter 3 and becomes a frequency control signal.

The VCO 4 generates a control clock signal whose frequency changes according to the voltage value of the frequency control signal supplied from the filter 3.
The feedback frequency divider 5 is variably controlled in frequency division ratio by a frequency division ratio control signal supplied from a frequency division ratio control unit 8 described later. Then, the control clock signal input from the VCO 4 is divided by the division ratio determined by this control to generate a feedback divided clock signal, which is output to the phase comparator 2 described above.

  The first output stage frequency divider 6 divides the input control clock signal by a predetermined frequency dividing ratio to generate a video processing reference clock signal having a predetermined frequency for use in video signal processing. Output to the signal processor.

  The second output stage frequency divider 7 divides the input control clock signal by a predetermined frequency dividing ratio, generates a reference clock signal for MPEG processing having a predetermined frequency for use in MPEG processing, and performs MPEG processing (not shown). Output to the section.

  The video pattern detector 9 receives the same video signal that is input to a video processor (not shown). Then, the video pattern detection unit 9 detects a specific video pattern included in the input video signal and outputs a video pattern detection signal indicating the period of the detected video pattern to the frequency division ratio control unit 8.

  The frequency division ratio control unit 8 generates a frequency division ratio control signal corresponding to the video pattern detection signal input from the video pattern detection unit 9 and outputs the frequency division ratio control signal to the feedback frequency divider 5. Controls the frequency division ratio.

Next, the operation of the first embodiment will be described with reference to FIG. 1, FIG. 4A, and FIG.
FIG. 4A shows how a specific video pattern is detected from a video signal and a control signal A / B is generated.

FIG. 7 is a block diagram showing a detailed internal configuration of the frequency division ratio control unit 8.
In the first embodiment, jitter is generated in the reference clock signal during variable control by variably controlling the frequency division ratio of the feedback frequency divider 5 in accordance with a specific video pattern detected from the input video signal. However, it is possible to make the image quality deterioration due to the jitter as inconspicuous as possible.

  For example, the frequency of the oscillation clock signal that is an input signal is Fref (Hz), the frequency division ratio of the input stage divider 1 is M1, the frequency division ratio of the first output stage frequency divider 6 is M2, and the feedback frequency divider 5 Is M3, and the output frequency of the first output stage divider 6 is Fout (Hz).

Fout = Fref ÷ M1 × M3 × M2 Equation 1
However, Fout, Fref, M1, M2, and M3 are natural numbers. Here, when the required Fout cannot completely satisfy the relationship of the above equation 2 based on natural numbers, the frequency dividing ratio of the feedback frequency divider is set to M3. And M3 + α are changed at a predetermined timing, so that when integrated on the time axis, the target frequency Fout is obtained as a whole. Α is the minimum step × natural number for setting the frequency division ratio of the feedback frequency divider 5.

  In the first embodiment, a period in which the frequency dividing ratio of the feedback frequency divider 5 is fixed at M3 and a period in which variable control is performed by M3 + α are provided, and the timing for switching each other period is not a fixed pattern. The circumferential ratio control unit 8 is characterized in that it is dynamically changed.

Hereinafter, the operation of dynamically changing the frequency division ratio of the feedback frequency divider 5 by the frequency division ratio control unit 8 will be described in detail with reference to FIG. 4A.
As shown in FIG. 4A, the video pattern detection unit 9 detects whether or not the luminance level of the input video signal exceeds a preset threshold value. Then, the detection result is output to the frequency division ratio control unit 8 as a video pattern detection signal.

  Next, the variable timing setting unit 36 of the frequency division ratio control unit 8 shown in FIG. 7 is a bright video in which the luminance level of the video signal is higher than the threshold according to the video pattern signal supplied from the video pattern detection unit 9. In the video period (A) determined to be present, a control signal A for fixing the frequency division ratio to M3 is generated and output to the subsequent frequency division ratio control signal generation unit 37. On the other hand, in the video period (B) in which the luminance level of the video signal is equal to or lower than the threshold value and is determined to be a dark video, a control signal B for variably controlling the division ratio by M3 + α is generated and the subsequent division ratio Output to the control signal generator 37. In FIG. 7, an audio pattern detection signal is also described as an input signal to the variable timing setting unit 36, but this is used in Example 2 and Example 3 to be described later, and is used in Example 1. do not do.

  The frequency division ratio control signal generation unit 37 generates a frequency division ratio control signal so that the frequency division ratio becomes a fixed value M3 that is determined in advance during the period in which the control signal A is supplied, and the feedback frequency divider 5 Output to. On the other hand, during the period in which the control signal B is supplied, for example, by analyzing the setting condition of the frequency division ratio for each predetermined period, the frequency of the reference clock signal can be controlled on the time axis. When integration is performed in a period sufficiently longer than each period in which the frequency is supplied, the coefficient of the α portion of the frequency division ratio M3 + α is calculated so that the desired frequency is obtained as a whole. Then, using this calculated α, a frequency division ratio control signal is generated so that the frequency division ratio becomes M3 + α, and is output to the feedback frequency divider 5.

  According to the first embodiment, the period of changing the frequency dividing ratio by the above processing is set to the reference clock by setting the low-dark (dark) luminance level of the input video signal where the jitter level is not noticeable. It is possible to reduce the visual influence on the image due to the jitter of the signal.

  In the above description, the video pattern is detected based on the luminance level. However, the video pattern detection method is not limited to this. Any video pattern may be detected as long as it is a video pattern that can distinguish between a video that is less noticeable and a video that is less noticeable due to jitter of the reference clock signal.

  For example, as shown in FIG. 4B, an image that is susceptible to jitter such as a vertical line component and a horizontal line component appearing in the video may be extracted by filtering and used.

Next, Example 2 will be described.
FIG. 2 is a block diagram illustrating the configuration of the second embodiment. In the figure, the same components as those in FIG.

  In the second embodiment, a third output stage frequency divider 11 is provided in place of the first output frequency divider 6 in the first embodiment, and an audio pattern detection unit 10 is provided in place of the video pattern detection unit 9 in the first embodiment. There is a feature in the point.

  The third output stage frequency divider 11 divides the input control clock signal by a predetermined frequency division ratio, generates a sound processing reference clock signal having a predetermined frequency for use in sound signal processing, and generates a sound (not shown). Output to the signal processor.

  The audio pattern detection unit 10 receives the same audio signal as that input to an audio processing unit (not shown). The voice pattern detection unit 10 detects a specific voice pattern included in the input voice signal, and outputs a voice pattern detection signal indicating the period of the detected voice pattern to the frequency division ratio control unit 8.

Next, the operation of the second embodiment will be described with reference to FIG. 2 and FIG.
FIG. 5A shows a state where a specific sound pattern is detected from the sound signal and the control signal A / B is generated.

  In the second embodiment, jitter is generated in the reference clock signal during variable control by variably controlling the frequency dividing ratio of the feedback frequency divider 5 according to a specific sound pattern detected from the input sound signal. However, it is possible to make the deterioration of sound quality caused by the jitter as inconspicuous as possible.

  As shown in FIG. 5A, the sound pattern detection unit 10 determines whether or not the volume level of the input sound signal exceeds a preset threshold value. Then, the determination result is output to the frequency division ratio control unit 8 as an audio pattern detection signal.

Since the operation of the frequency division ratio control unit 8 is the same as that of the first embodiment except that the input signal is changed from the video pattern detection signal to the audio pattern detection signal, description thereof is omitted.
According to the second embodiment, the period during which the frequency division ratio is changed by the above processing is set to a reference level by setting a low (low tone) audio part with low jitter level in the input audio signal. It is possible to reduce the auditory influence on the sound due to the jitter of the clock signal.

  In the above description, the sound pattern is detected based on the sound volume level, but the sound pattern detection method is not limited to this. Any sound pattern may be detected as long as it is a sound pattern that can distinguish between sound that is hardly noticeable and sound that is not easily noticeable due to jitter of the reference clock signal.

  For example, as shown in FIG. 5B, a specific frequency component that is easily affected by jitter may be extracted as a voice pattern by filtering and used. Specific frequency components that are easily affected by jitter include, for example, clear single tone components, chord components, and high frequency components.

Next, Example 3 will be described.
FIG. 3 is a block diagram illustrating the configuration of the third embodiment. In the figure, the same components as those in FIGS. 1 and 2 are denoted by the same reference numerals, and description thereof is omitted.

  The third embodiment is characterized in that the first output frequency divider 6 and the video pattern detector 9 in the first embodiment and the third output stage frequency divider 11 and the audio pattern detector 10 in the second embodiment are provided simultaneously. There is.

The operation of the third embodiment will be described below with reference to FIGS.
FIG. 6 is a diagram showing how a specific video pattern is detected from a video signal, a specific audio pattern is detected from an audio signal, and a control signal A / B is generated therefrom.

In the third embodiment, the frequency division ratio control unit 8 receives the video pattern detection signal and the audio pattern detection signal at the same time.
Then, as shown in FIG. 6, the variable timing setting unit 36 generates a control signal A / B from the logical product of the video pattern detection signal and the audio pattern detection signal. Depending on the situation of the video signal and the audio signal, the control signal A / B may be generated from the logical sum instead of the logical product.

Since the operation after the control signal A / B is generated is the same as that of the first and third embodiments, the description thereof is omitted.
According to the third embodiment, the period in which the frequency division ratio is changed by the above processing is set to a period in which jitter is not conspicuous in both the input audio signal and the video signal. The audiovisual effect on the audio can be reduced, and the PLL circuit can be shared for generating the reference clock signal for video signal processing and the reference clock signal for processing the audio signal, thereby suppressing cost increase. It becomes.

  In the above description, an example in which an oscillation clock signal generated by a crystal oscillator or the like is used as an input signal is shown. However, even if the input signal is not an oscillation clock signal, the signal has a constant frequency and low jitter. Any signal can be used. For example, a video synchronization signal such as H sync may be used.

  Further, the VCO 4 may be configured by analog or may be configured by digital.

1 is a block diagram illustrating a configuration of Example 1. FIG. 6 is a block diagram illustrating a configuration of Example 2. FIG. 10 is a block diagram illustrating a configuration of Example 3. FIG. It is a figure which shows a mode that a specific video pattern is detected from a video signal in Example 1, and control signal A / B is produced | generated. It is a figure which shows a mode that a specific video pattern is detected from a video signal in Example 1, and control signal A / B is produced | generated. It is a figure which shows a mode that a specific audio | voice pattern is detected from an audio | voice signal in Example 2, and control signal A / B is produced | generated. It is a figure which shows a mode that a specific audio | voice pattern is detected from an audio | voice signal in Example 2, and control signal A / B is produced | generated. In Example 3, it is a figure which shows a mode that a specific audio | voice pattern is detected from an audio | voice signal while a specific video pattern is detected from an image | video signal, and control signal A / B is produced | generated from these. 3 is a detailed block diagram of a frequency division ratio control unit 8. FIG.

Explanation of symbols

1 Input stage frequency divider 2 Phase comparator 3 Filter 4 VCO
DESCRIPTION OF SYMBOLS 5 Feedback frequency divider 6 1st output stage frequency divider 7 2nd output stage frequency divider 8 Frequency division ratio control part 9 Video pattern detection part 10 Audio | voice pattern detection part 11 3rd output stage frequency divider 36 Variable timing setting part 37 Dividing ratio control signal generator

Claims (2)

The first predetermined frequency of the input clock signal is multiplied / multiplied using at least a multiplier that multiplies by a multiplication coefficient N (N is a natural number) and a divider that divides by a division coefficient M (M is a natural number). In a reference clock signal generation device for generating a reference clock signal having a second predetermined frequency necessary for executing the digital video signal processing of
In a feedback frequency divider used in a PLL circuit constituting the multiplier, frequency division ratio control means for controlling a frequency division ratio that is a value for determining the multiplication coefficient N;
The digital video signal processing target video signal is received as an input, and a luminance level of the video signal or a level of a signal obtained by filtering at least one of a vertical line component and a horizontal line component from the video signal is determined. Video pattern detection means for detecting whether or not a predetermined first threshold value or less;
Have
The frequency division ratio control means includes:
When the reference clock signal having the second predetermined frequency cannot be generated even by multiplication and division with the multiplication coefficient N and the division coefficient M as fixed values,
In the first period in which the video pattern detection means detects that the video signal has exceeded the first threshold, the frequency of the output clock signal of the reference clock signal generator is a value close to the second predetermined frequency. A first division ratio that is a fixed value such that the division ratio is controlled by the feedback frequency divider so that the division ratio becomes the determined first division ratio;
In the second period in which the video pattern detection means detects that the video signal is equal to or lower than the first threshold, the first period depends on the control status of the feedback frequency divider up to that time. When the frequency of the output clock signal is integrated within a predetermined period that is sufficiently longer than the period and the second period, the frequency of the output clock signal is equivalent to the second predetermined frequency. A second frequency division ratio obtained by correcting a frequency shift amount between the frequency obtained by the frequency division ratio of 1 and the second predetermined frequency is calculated, and the feedback is performed so that the calculated second frequency division ratio is obtained. Means for controlling the frequency divider,
A reference clock signal generator characterized by the above. The first predetermined frequency of the input clock signal is multiplied / multiplied using at least a multiplier that multiplies by a multiplication coefficient N (N is a natural number) and a divider that divides by a division coefficient M (M is a natural number). In a reference clock signal generation device for generating a reference clock signal having a second predetermined frequency necessary for executing the digital audio signal processing of
In a feedback frequency divider used in a PLL circuit constituting the multiplier, frequency division ratio control means for controlling a frequency division ratio that is a value for determining the multiplication coefficient N;
The level of a signal obtained by receiving the digital audio signal processing target audio signal as an input and extracting at least one of a volume level of the audio signal or a single tone component, a chord component, or a high frequency component from the audio signal by filtering. Audio pattern detection means for detecting whether or not is equal to or less than a first threshold value set in advance;
Have
The frequency division ratio control means includes:
When the reference clock signal having the second predetermined frequency cannot be generated even by multiplication and division with the multiplication coefficient N and the division coefficient M as fixed values,
In a first period in which the audio pattern detection means detects that the audio signal has exceeded the first threshold, the frequency of the output clock signal of the reference clock signal generator is a value close to the second predetermined frequency. A first division ratio that is a fixed value such that the division ratio is controlled by the feedback frequency divider so that the division ratio becomes the determined first division ratio;
The second period in which the audio pattern detection unit detects that the video signal is equal to or less than the first threshold is determined according to the control status of the feedback frequency divider up to that time. When the frequency of the output clock signal is integrated within a predetermined period that is sufficiently longer than the period and the second period, the frequency of the output clock signal is equivalent to the second predetermined frequency. A second frequency division ratio obtained by correcting a frequency shift amount between the frequency obtained by the frequency division ratio of 1 and the second predetermined frequency is calculated, and the feedback is performed so that the calculated second frequency division ratio is obtained. Means for controlling the frequency divider,
A reference clock signal generator characterized by the above.

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