JP2009147054A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing parasitic capacitance between wiring portions and preventing a short circuit caused by an air gap, a deterioration in breakdown voltage caused by the reduction of space between wirings, and the generation of a short circuit between the wiring portions, and its manufacturing method. <P>SOLUTION: A third insulating film 110 covering the upper surface and the side surface of wiring portions 108 and 109 is formed on a first insulating film 102. The third insulating film 110 comprises a first region 155 having a first aspect ratio and a second region 156 having a second aspect ratio smaller than the first aspect ratio. The wiring portion 109 comprises a second region 156 having the second aspect ratio. An air gap 111 is formed on the first region 155. The air gap 111 is not formed on the second region 156. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a semiconductor integrated circuit and a manufacturing method thereof.

  With the recent high density integration of semiconductor integrated circuits, the distance between wiring and other wiring has been reduced, and the wiring layer including wiring has been made multi-layered, resulting in an increase in parasitic capacitance between wirings. Yes. The increase in the parasitic capacitance between the wirings hinders the delay of the circuit operation, that is, the high speed of the integrated circuit. Further, crosstalk between the wirings becomes a problem.

Normally, SiO ₂ having a relative dielectric constant of about 4 is used as an interlayer insulating film of a semiconductor integrated circuit. However, a method of forming an interlayer insulating film having a low dielectric constant is used to reduce the parasitic capacitance between wirings. It has been adopted. For example, a porous film having fine pores or a low dielectric constant film such as organic SOG has been put into practical use, but the equipment needs to be changed, the difficulty of processing becomes high, and the mechanical strength is low. There are also many problems with the characteristics of the film.

  As another method for reducing the parasitic capacitance between the wirings, there is a method in which an air gap called an air gap is arranged between the wirings instead of using a low dielectric constant film. This air gap is an air gap formed of a closed region and has a low relative dielectric constant of about 1 and is effective in reducing parasitic capacitance between wirings.

  As a method of forming the air gap, a method of forming an air gap according to the distance between wirings is described in Japanese Patent No. 2853661 (Patent Document 1). Hereinafter, a method for forming the air gap will be described.

  In the above formation method, first, as shown in FIG. 16, a wiring metal film 203 is deposited on the substrate 201 on which the first insulating film 202 is deposited.

  Next, the wiring metal film 203 is etched to form a wiring 205 as shown in FIG. The distance between the wiring 205 and another wiring 205 adjacent to the wiring 205 is arbitrarily set to a value not less than a value specified in the design. Note that reference numeral 204 in FIG. 17 denotes a photoresist serving as an etching mask.

  Next, as shown in FIG. 18, a second insulating film 206 is deposited on the wiring 205. At this time, if the distance between the wiring 205 and another wiring 205 adjacent thereto is equal to or smaller than a certain value, an air gap 207 is formed between them.

  Next, the second insulating film 206 is planarized by a known CMP (Chemical Mechanical Polishing) technique or the like to obtain the second insulating film 250 shown in FIG.

  Next, the second insulating film 250 is etched to form a second insulating film 251 having a plurality of via holes 252 as shown in FIG. Thereafter, a connection plug 208 is formed in the via hole 252, and the connection plug 208 is connected to the via hole 252.

  As described above, the air gap 207 is formed, but the via hole 252 may be formed out of a desired position due to misalignment. Specifically, in the photo process of transferring the via pattern, the via pattern is transferred out of position from the wiring 205 due to misalignment, and the via hole 252 is formed out of the desired position by the etching process. For this reason, as shown in FIG. 20, the via hole 252 formed at the left end may communicate with the air gap 207. At this time, an etching gas, a chemical solution, or the like enters from the via hole 252 through the air gap 207 to expose the side wall of the wiring 205.

  Therefore, when the connection plug 208 is formed in the via hole 252 communicating with the air gap 207, the material of the connection plug 208 also flows into the air gap 207, and the wiring near the air gap 207 and the connection plug 208 are short-circuited. Problem arises.

  As a method for solving the above problem, Japanese Patent No. 2948588 (Patent Document 2) describes a method in which a via hole does not communicate with an air gap even when misalignment occurs. This is a method of forming a wiring connected to the connection plug after the connection plug is formed first. Hereinafter, the method will be described.

  In the above method, first, as shown in FIG. 21, a first wiring metal film 303 is deposited on a substrate 301 on which a first insulating film 302 is deposited, and then a first wiring metal film 303 is formed on the first wiring metal film 303. Two insulating films 304 are deposited.

  Next, the second insulating film 304 is etched to obtain a second insulating film 350 in which a plurality of via holes 306 are formed as shown in FIG. The via hole 306 reaches the first wiring metal film 303 from the upper surface of the second insulating film 350 and penetrates through the second insulating film 350. Note that reference numeral 305 in FIG. 22 denotes a photoresist serving as an etching mask.

  Next, as shown in FIG. 23, a second wiring metal film 307 is deposited on the first wiring metal film 303 and the second insulating film 350 by a known CVD technique. As a result, part of the second wiring metal film 307 enters the via hole 306.

  Next, a part of the second wiring metal film 307 is removed by a known CMP technique or the like to form a connection plug 308 in the via hole 306 as shown in FIG.

  Next, the second insulating film 350 is etched to leave the connection plug 308 and the second insulating film 310 on the first wiring metal film 303 as shown in FIG. The second insulating film 310 is processed into a wiring pattern. Note that reference numeral 309 in FIG. 25 denotes a photoresist serving as an etching mask.

  Next, using the photoresist 309, the connection plug 308, and the second insulating film 310 as an etching mask, the first first metal wiring film 303 is selectively removed by etching, as shown in FIG. The wiring 311 is obtained.

  Next, after removing the photoresist 309 and etching residues, a third insulating film 312 shown in FIG. 27 is formed so as to cover the second insulating film 310, the wiring 311 and the connection plug 308 processed into a wiring pattern. Form. At this time, if the distance between the wiring 311 and another wiring 311 adjacent to the wiring 311 is equal to or smaller than a certain value, an air gap 313 is formed therebetween.

  Next, the third insulating film 312 is planarized by a known CMP technique or the like until the connection plug 308 is exposed, whereby a third insulating film 351 shown in FIG. 28 is obtained.

  Thus, since the air gap 313 is formed after the connection plug 308 is formed first, a short circuit due to the metal material entering the air gap 313 can be prevented.

  However, since the wiring 311 connected to the connection plug 308 is formed using the connection plug 308 as an etching mask, the width of the wiring connected along the shape of the connection plug increases when misalignment occurs.

For this reason, in the portion where the width of the wiring is widened, the wiring interval becomes smaller than the minimum wiring interval specified in the design, and as a result, the breakdown voltage between the wiring 311 and the other wiring 311 adjacent thereto is deteriorated. Or a short circuit occurs.
Japanese Patent No. 2853661 Japanese Patent No. 2948588

  Therefore, the problem of the present invention is that the parasitic capacitance between the wiring portions can be reduced, and furthermore, the short circuit between the wirings due to the connection plug material entering the air gap and the breakdown voltage deterioration due to the reduction of the wiring interval. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same.

In order to solve the above problems, a semiconductor device of the present invention is
A semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
A plurality of first wiring portions including a conductor film formed on the first insulating film and a second insulating film formed on the conductor film and extending in parallel with each other;
A plurality of second wiring portions made of only a conductor film formed on the first insulating film and extending in parallel with each other;
A third insulating film covering the top and side surfaces of the first wiring portion and the second wiring portion;
A via hole reaching at least one of the conductor film of the first wiring portion or the second wiring portion from the upper surface of the third insulating film;
A connection plug formed in the via hole and connected to the conductor film of the first wiring portion or the second wiring portion;
The third insulating film is
A first region defined by at least one side surface of the plurality of first wiring portions and having a first aspect ratio in a cross section orthogonal to a direction in which the first wiring portion extends;
Based on the first aspect ratio in a cross section defined by at least one side surface of the plurality of first wiring portions and the second wiring portions and orthogonal to the extending direction of the first wiring portions and the second wiring portions. And a second region having a small second aspect ratio,
There is an air gap that is a closed space in the first region, and there is no air gap that is a closed space in the second region,
The via hole and the connection plug are connected to a conductor film of the first wiring portion or the second wiring portion having a side surface defining the second region.

  According to the semiconductor device having the above configuration, since there is an air gap that is a closed space in the first region, the parasitic capacitance between the first wiring portions can be reduced.

  The connection plug is connected to the first wiring portion having the side surface defining the second region, but there is no air gap that is a closed space in the second region. A short circuit due to the plug material entering the air gap can be prevented.

In the semiconductor device of one embodiment,
A via hole and a connection plug are connected to the conductor film of the wiring part having a side surface defining the first region, the first wiring part width being wider than the minimum wiring part width of the plurality of first wiring parts. Has been.

  According to the semiconductor device of the above embodiment, since the wiring portion width of the first wiring portion is wider than the minimum wiring portion width of the plurality of first wiring portions, a margin for allowing misalignment can be secured, and the connection The plug is connected to the upper surface of the first wiring part.

  Therefore, although there is an air gap in the vicinity of the first wiring portion having the side surface defining the first region, even if the connection plug is connected to the conductor film of the first wiring portion, the material of the connection plug is not changed. A short circuit due to entering the air gap can be prevented.

In the semiconductor device of one embodiment,
The first aspect ratio is in the range of 1-5.

  According to the semiconductor device of the embodiment, since the first aspect ratio is in the range of 1 to 5, an air gap can be reliably obtained in the first region.

  Further, if the first aspect ratio is less than 1, it is difficult to form an air gap in the third insulating film, which is not preferable.

  Further, if the first aspect ratio exceeds 5, it is not preferable because it is difficult to process the first wiring portion.

In the semiconductor device of one embodiment,
The second aspect ratio is greater than 0 and 4 or less.

  According to the semiconductor device of the above embodiment, since the second aspect ratio is greater than 0 and 4 or less, it is possible to reliably prevent an air gap from being formed in the second region.

  The second aspect ratio is a positive value larger than 0 because it is the ratio of the height of the first wiring portion to the distance between the first wiring portions.

  Further, if the second aspect ratio exceeds 4, it is not preferable because it is difficult to deposit the third insulating film without forming an air gap.

A method for manufacturing a semiconductor device of the present invention includes:
A plurality of first wiring portions including a conductor film formed on the first insulating film deposited on the semiconductor substrate and a second insulating film formed on the conductor film, and extending in parallel with each other. Forming on the first insulating film a plurality of second wiring portions formed only on the first insulating film and made only of the conductor film and extending in parallel with each other; When,
Depositing a third insulating film on the first wiring portion and the second wiring portion, and covering the side surfaces and the upper surface of the first wiring portion and the second wiring portion with the third insulating film; ,
Forming a via hole that reaches at least one of the conductor film of the first wiring portion or the second wiring portion from the upper surface of the third insulating film;
Forming a connection plug connected to the conductor film of the first wiring portion or the second wiring portion in the via hole,
The third insulating film is
A first region defined by at least one side surface of the plurality of first wiring portions and having a first aspect ratio in a cross section orthogonal to a direction in which the first wiring portion extends;
Based on the first aspect ratio in a cross section defined by at least one side surface of the plurality of first wiring portions and the second wiring portions and orthogonal to the extending direction of the first wiring portions and the second wiring portions. And a second region having a small second aspect ratio,
Further, the third insulating film is formed so that there is no air gap in the second region so as to have an air gap which is a closed space in the first region,
The via hole and the connection plug are formed so as to be connected to the first wiring portion or the second wiring portion having a side surface defining the second region.

  According to the method of manufacturing a semiconductor device having the above configuration, the third insulating film includes a first region having a first aspect ratio and a second region having a second aspect ratio smaller than the first aspect ratio. Therefore, an air gap that is a closed space can be formed in the first region of the third insulating film. Therefore, the parasitic capacitance between the first wiring portions can be reduced.

  In addition, since the second aspect ratio of the second region is smaller than the first aspect ratio of the first region, it is possible to prevent an air gap that is a closed space from being formed in the second region. it can. That is, it is possible to prevent an air gap from being present in the vicinity of the first wiring portion having the side surface defining the second region. Therefore, even if the connection plug is connected to the first wiring portion and the second wiring portion having the side surfaces defining the second region, a short circuit due to the material of the connection plug entering the air gap can be prevented. it can.

  Further, since the connection plug is formed after the first wiring portion and the second wiring portion are formed, the connection plug is not used as an etching mask for forming the first wiring portion and the second wiring portion. . Accordingly, the first wiring portion width and the second wiring portion width are increased along the shape of the connection plug, and the first wiring portion interval and the second wiring portion interval are reduced. It is possible to prevent a short circuit between the first wiring portions and the second wiring portions.

In one embodiment of a method for manufacturing a semiconductor device,
A via hole and a connection are formed in a wiring part formed so that a wiring part width of the first wiring part having a side surface defining the first region is wider than a minimum wiring part width of the plurality of first wiring parts. Connect the plug.

  According to the method of manufacturing a semiconductor device of the above embodiment, the wiring portion width of the first wiring portion is wider than the minimum wiring portion width of the plurality of first wiring portions. The connection plug is connected to the upper surface of the first wiring portion.

  Therefore, there is an air gap in the vicinity of the first wiring portion having the side surface defining the first region, but the air gap and the via hole do not communicate with each other, so that the first wiring portion is connected to the conductor film. Even if the plug is connected, the connection plug material does not enter the air gap, and a short circuit due to the connection plug material entering the air gap can be prevented.

In one embodiment of a method for manufacturing a semiconductor device,
The first aspect ratio is in the range of 1-5.

  According to the method for manufacturing a semiconductor device of the above embodiment, since the first aspect ratio is in the range of 1 to 5, it is possible to reliably obtain an air gap that is a closed space in the first region. it can.

  Further, if the first aspect ratio is less than 1, it is not preferable because it is difficult to form an air gap when the third insulating film is deposited.

  Further, if the first aspect ratio exceeds 5, it is not preferable because it is difficult to process the first wiring portion.

In one embodiment of a method for manufacturing a semiconductor device,
The second aspect ratio is greater than 0 and 4 or less.

  According to the method of manufacturing a semiconductor device of the above embodiment, since the second aspect ratio is in the range of greater than 0 and less than or equal to 4, the air gap is reliably prevented from being formed in the second region. Can do.

  The second aspect ratio is a positive value larger than 0 because it is the ratio of the height of the first wiring portion to the distance between the first wiring portions.

  Further, if the second aspect ratio exceeds 4, it is not preferable because it is difficult to deposit the third insulating film without forming an air gap.

  In the semiconductor device of the present invention, since there is an air gap in the first region of the third insulating film, the parasitic capacitance between the first wiring portions can be reduced.

  In addition, since there is no air gap in the second region of the third insulating film, a connection plug is connected to the first wiring portion and the second wiring portion having side surfaces defining the second region. However, it is possible to prevent a short circuit due to the material of the connection plug entering the air gap.

  According to the method of manufacturing a semiconductor device of the present invention, a first region having a first aspect ratio and a second region having a second aspect ratio smaller than the first aspect ratio are formed in the third insulating film. Therefore, the air gap can be formed in the first region of the third insulating film. Therefore, the parasitic capacitance between the first wiring portions can be reduced.

  Further, since the second aspect ratio of the second region is smaller than the first aspect ratio of the first region, the first wiring portion having the side surface defining the second region and the vicinity of the second wiring portion are disposed. An air gap can be prevented from being formed. Therefore, even if the connection plug is connected to the first wiring portion and the second wiring portion having the side surfaces defining the second region, a short circuit due to the material of the connection plug entering the air gap can be prevented. it can.

  In addition, since the connection plug is formed after the first wiring portion is formed, the connection plug is not used as an etching mask for forming the first wiring portion. Accordingly, the first wiring portion width and the second wiring portion width are increased along the shape of the connection plug, and the first wiring portion interval and the second wiring portion interval are reduced. It is possible to prevent a short circuit between the first wiring portions and the second wiring portions.

  Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to embodiments shown in the drawings.

(First embodiment)
FIG. 1 is a schematic view of a semiconductor device according to a first embodiment of the present invention as viewed from above. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. In FIG. 1, only the wiring layer of the semiconductor device is shown, and the substrate and elements below the wiring layer are omitted.

  As shown in FIGS. 1 and 2, the semiconductor device includes a semiconductor substrate 101, a first insulating film 102 formed on the semiconductor substrate 101, and a first insulating film 102 formed on the first insulating film 102. A plurality of wiring portions 108 and 109 extending in parallel, a third insulating film 110 covering the top and side surfaces of the wiring portions 108 and 109, and a plurality of reaching the wiring portions 108 and 109 from the top surface of the third insulating film 110. Via holes 154 and a plurality of connection plugs 112 formed in the plurality of via holes 154. The wiring unit 108 is an example of a first wiring unit. The wiring unit 109 is an example of a second wiring unit.

The plurality of wiring portions 108 are formed on the Ti film 108a, the TiN film 108b formed on the Ti film 108a, the AlCu film 108c formed on the TiN film 108b, and the AlCu film 108c, respectively. The TiN film 108d and the SiO ₂ film 108e formed on the TiN film 108d are included. The SiO ₂ film 108e is the upper part of the wiring part 108. The Ti film 108a, TiN film 108b, AlCu film 108c, and TiN film 108d are examples of conductor films. The SiO ₂ film 108e is an example of a second insulating film.

The plurality of wiring portions 109 are respectively formed on the Ti film 109a, the TiN film 109b formed on the Ti film 109a, the AlCu film 109c formed on the TiN film 109b, and the AlCu film 109c. TiN film 109d thus formed. Further, each of the plurality of wiring portions 109 is composed of a TiN film 109d at the top and does not include an insulating film such as a SiO ₂ film.

Of the plurality of connection plugs 112, the connection plug 112 connected to the wiring portion 108 penetrates the SiO ₂ film 108e in the thickness direction and is in contact with at least the TiN film 108d.

  The third insulating film 110 has a first region 155 and a second region 156. The first region 155 is defined by the side surfaces of the plurality of wiring portions 108 and has a first aspect ratio in a cross section orthogonal to the extending direction of the wiring portions 108. The second region 156 is defined by the side surfaces of the plurality of wiring portions 108 and has a second aspect ratio smaller than the first aspect ratio in a cross section orthogonal to the extending direction of the wiring portions 108. .

  The first region 155 has an air gap 111 that is a closed space, but the second region 156 has no air gap.

  The via hole 154 and the connection plug 112 are not connected to the wiring portion 108 having the side surface defining the first region 155.

  The via hole 154 and the connection plug 112 are connected to the wiring portion 108 having a side surface defining the second region 156. Note that a region similar to the second region is also formed between the wiring portions 109, and the via hole 154 and the connection plug 112 are connected to the wiring portion 109.

  Further, a MOS (metal oxide semiconductor) field effect transistor 150 and an STI (shallow trench isolation) region 152 are formed on the semiconductor substrate 101.

  Further, on the third insulating film 110, a wiring portion 115, a fifth insulating film 116 covering the upper surface and the side surface of the wiring portion 115, and a bonding pad connected to an electrode of a package housing the semiconductor device. 153 is formed.

The wiring portion 115 includes a Ti film 115a, a TiN film 115b formed on the Ti film 115a, an AlCu film 115c formed on the TiN film 115b, and a TiN film formed on the AlCu film 115c. 115d and a SiO ₂ film 115e formed on the TiN film 115d. The Ti film 115a, TiN film 115b, AlCu film 115c, and TiN film 115d are examples of conductor films. The SiO ₂ film 115e may or may not be an insulating film other than SiO ₂ .

  Hereinafter, the manufacturing method of the semiconductor device will be described with reference to FIGS.

  In the above manufacturing method, first, as shown in FIG. 3, a first wiring metal film 103 is deposited on the semiconductor substrate 101 on which the first insulating film 102 is deposited, and further on the first wiring metal film 103. Then, a second insulating film 104 is deposited.

More specifically, Ti, TiN, AlCu, and TiN are arranged in this order as an example of the first wiring metal film on the semiconductor substrate 101 on which the SiO ₂ film having a thickness of 600 nm is deposited as an example of the first insulating film 102. Are deposited with a thickness of 20 nm, a thickness of 30 nm, a thickness of 400 nm, and a thickness of 50 nm, respectively, and an SiO ₂ film with a thickness of 100 nm is deposited as an example of the second insulating film 104. This SiO ₂ film is later processed to become the SiO ₂ film 108e of FIG.

  Further, the first wiring metal film 102 may be formed of a material normally used for a semiconductor device including Ag, Au, Al, Cu, Ta, W, Ru, or the like.

In addition to the SiO ₂ film, the second insulating film 104 may be an insulating film normally used in a semiconductor device such as a SiOF film, a SiON film, a SiOC film, a SiN film, or a SiC film.

  Further, an antireflection film such as a SiON film may be deposited on the first wiring metal film 102 or the second insulating film 104. The thickness of the antireflection film is about 100 nm, but in order to control the first and second aspect ratios, it may be in the range of about 50 nm to 400 nm, about 50 nm to 200 nm, or about 30 to 100 nm.

  Next, a part of the second insulating film 104 is selectively removed by a known etching technique to form a second insulating film 106 on the first wiring metal film 103 as shown in FIG. To do. Thereafter, a treatment for removing the etching residue and the photoresist 105 may be performed.

  A plurality of wiring portions 109 (see FIG. 2) are formed in a post process in a region exposed by removing a part of the second insulating film 104. On the other hand, in a region where a part of the second insulating film 104 is left, that is, a region covered with the second insulating film 106, a plurality of wiring portions 108 (see FIG. 2) are formed in a later process. The

  Next, a part of the first wiring metal film 103 and the second insulating film 106 is selectively removed by a known etching technique, and a plurality of films are formed on the first insulating film 102 as shown in FIG. Wiring portions 108 and 109 are formed. Reference numeral 107 denotes a photoresist on which a wiring pattern is formed.

More specifically, after forming a photoresist 107 on the first wiring metal film 103 and the second insulating film 106, the second insulating film 106 made of SiO ₂ is etched in a chamber for etching SiO _2. Further, the first wiring metal film 103 is etched in a chamber for etching the metal film. Here, the second insulating film 106 and the first wiring metal film 103 are etched in different chambers, but etching may be performed by changing the etching gas in the same chamber.

The wiring portion 109 has a height of 500 nm, and the wiring portion 108 has a height of 600 nm. That is, the wiring part 108 is higher than the wiring part 109 by the amount of SiO ₂ at the top.

  Next, as shown in FIG. 6, a third insulating film 157 covering the upper surfaces and side surfaces of the wirings 108 and 109 is deposited by a CVD (chemical vapor deposition) method. As a result, the air gap 111 can be formed in the gap 155 having the first aspect ratio between the wiring portions 108 as the first regions, and between the wiring portions 108 as the second regions. The gap 156 having the second aspect ratio smaller than the first aspect ratio can be completely filled with the third insulating film 157. Note that the vicinity of the wiring portion 109 is only the second region and is completely filled with the third insulating film 157.

More specifically, as an example of the third insulating film 157, a 1000 nm SiO ₂ film is deposited by a high-density plasma CVD apparatus. The SiO ₂ film is formed by introducing SiH ₄ at 100 sccm, O ₂ at 180 sccm, and Ar at 300 sccm in a high-density plasma CVD apparatus. The power of the plasma generation source having a frequency of 450 kHz is 2500 W and the frequency is 13.56 MHz. The bias power is 1800 W. As a result, a gap having an aspect ratio of 2.4 or less in the gap between the wiring portions 108 can be completely filled with SiO ₂ . At this time, if the minimum wiring part interval defined in the design is, for example, 230 nm, the aspect ratio of the gap of the minimum wiring part interval of the wiring part 109 is about 2.2, so that the gap is completely filled with SiO _2. . Since the aspect ratio of the gap of the minimum wiring interval of the wiring part 108 is about 2.6, the gap is not completely filled with SiO ₂ , and the air gap 111 is formed in the gap. Further, if the gap larger than the minimum wiring interval of the wiring part 108 is 280 nm, for example, the aspect ratio of this gap is about 2.1, so that it is completely filled with SiO ₂ .

Here, the film formation conditions are described with the aspect ratio for embedding the SiO ₂ film as 2.4, but the value of the aspect ratio for embedding the SiO ₂ film by changing the film formation conditions such as power and gas flow rate is from 1. It can be arbitrarily changed within the range of 4.

The third insulating film 157 may be a silicon oxide film containing fluorine, carbon, nitrogen, etc. in addition to the SiO ₂ film.

  Further, the deposition of the third insulating film 157 may be performed while changing the film forming conditions in the middle. For example, deposition may be performed under conditions where the aspect ratio is 2.4 or less until the space between the wirings is buried, and then deposition may be performed under a condition where the deposition rate is high, thereby reducing the deposition time.

  Next, a planarization process is performed on the third insulating film 157 by a known CMP technique or the like to form a third insulating film 158 shown in FIG. Note that the planarization treatment may be performed after an insulating film such as a plasma TEOS film is deposited over the third insulating film 157.

  Next, an etching process is performed on the third insulating film 158 to form a third insulating film 110 having a plurality of via holes 154, as shown in FIG. A metal that is a material of the connection plug 112 is deposited inside the via hole 154. Then, when the metal outside the via hole 154 is removed by a known CMP technique or the like, the connection plug 112 is obtained in the via hole 154. The connection plug 112 is connected to the metal film of the wirings 108 and 109.

  More specifically, TiN and W are deposited in a thickness of 10 nm and 300 nm in this order in the via hole 154 by CVD, respectively, and the TiN and W films outside the via hole 154 are removed by CMP. At this time, since the air gap 111 is not formed near the via hole 154, the via hole 154 does not communicate with the air gap 111. Thus, the TiN and W do not enter the air gap 111, and a short circuit due to the TiN and W entering the air gap 111 can be prevented.

  In addition to TiN and W, the material of the connection plug 112 may be a material normally used for a semiconductor device including Ag, Au, Al, Cu, Ta, Ru, and the like.

  Next, as shown in FIG. 9, a wiring metal film 113 and a fourth insulating film 114 are deposited in this order on the third insulating film 110. Thereafter, when a predetermined process is performed, the semiconductor device shown in FIGS. 1 and 2 is obtained.

  The wiring metal film 113 includes a Ti film 113a, a TiN film 113b formed on the Ti film 113a, an AlCu film 113c formed on the TiN film 113b, and a TiN film formed on the AlCu film 113c. And a film 113d.

  Thus, since the air gap 111 is formed in the first region 155 of the third insulating film 110, the parasitic capacitance between the wiring portions 108 can be reduced.

  Further, since the second aspect ratio of the second region 156 is smaller than the first aspect ratio of the first region, the air gap 111 can be prevented from being formed in the second region 156. Therefore, even if the connection plug 112 is connected to the wiring portions 108 and 109 having the side surfaces defining the second region 156, the material of the connection plug 112 does not enter the air gap 111. Therefore, a short circuit due to the material of the connection plug 112 entering the air gap 111 can be prevented.

  The connection plug 112 is not used as an etching mask for forming the wiring portions 108 and 109. Therefore, the wiring width increases along the shape of the connection plug 112 and the interval between the wiring portions 108 and 109 is reduced, so that it is possible to prevent the breakdown voltage from being deteriorated or a short circuit from occurring.

  In addition, the width of the wiring portion 108 having a side surface defining the first region 155 (for example, the wiring portion 108 adjacent to the portion where the upper right wiring portion 108 is bent 90 degrees in FIG. 1) is specified by design. The width may be wider than the minimum wiring portion width. In this case, even when the connection plug 112 is connected to the wiring part 108 having the side surface defining the first region 155, a width that allows the misalignment of the via hole 154 that accommodates the connection plug 112 is secured. The via hole 154 can be prevented from communicating with the air gap 111. Therefore, a short circuit due to the material of the connection plug 112 entering the air gap 111 can be prevented.

  The first aspect ratio may be in the range of 1-5. In this case, the air gap 111 can be reliably formed in the first region 155.

  The second aspect ratio is in the range of greater than 0 and 4 or less. In this case, it is possible to reliably prevent the air gap 111 from being formed in the second region 156.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described below with reference to FIGS. In the following description, the same components as those of the first embodiment are denoted by reference numerals of the components of the first embodiment.

  10 to 15, the same components as those of the first embodiment shown in FIGS. 3 to 5 are denoted by the same reference numerals as the components in FIGS. 3 to 5.

  In the manufacturing method, as in the first embodiment, first, as shown in FIG. 10, the first wiring metal film 103 is deposited on the semiconductor substrate 101 on which the first insulating film 102 is deposited. Then, a second insulating film 104 is deposited on the first wiring metal film 103.

More specifically, Ti, TiN, AlCu, and TiN are formed in this order as the first wiring metal film on the semiconductor substrate 101 on which a 600 nm SiO ₂ film is deposited as an example of the first insulating film 102. Deposition is performed with a thickness of 20 nm, a thickness of 30 nm, a thickness of 400 nm, and a thickness of 50 nm. As an example of the second insulating film 104, a SiO ₂ film with a thickness of 100 nm is deposited. Note that an antireflection film or the like may be deposited over the second insulating film 104.

  Next, part of the second insulating film 104 is selectively removed by a known etching technique to obtain the second insulating film 106 shown in FIG. Thereafter, a treatment for removing the etching residue and the photoresist 105 may be performed.

Next, when the second insulating film 106 is used as an etching mask and a part of the first metal film 103 is selectively removed by a known etching technique, as shown in FIG. 12, the Ti film 108a, TiN A wiring 108 including the film 108b, the AlCu film 108c, the TiN film 108d, and the SiO ₂ film 108e is formed on the first insulating film 102. Thereafter, a treatment for removing the etching residue may be performed.

  Next, as shown in FIG. 13, an antireflection film 117 is deposited so as to cover the first insulating film 102 and the wiring portion 108.

  More specifically, as an example of the antireflection film 117, an organic antireflection film is deposited on the wiring portion 108 to have a thickness of 50 nm by spin coating, so that the first insulating film 102 and the wiring portion 108 are organically reflected. Cover with a protective film. At this time, an organic antireflection film is deposited thicker on the wiring portion 108 between the wirings 108.

  Next, as shown in FIG. 14, after a part of the antireflection film 117 is covered with the photoresist 118, the antireflection film 117 not covered with the photoresist 118 and the insulating film 108 e above the wiring portion 108 are formed. It is selectively removed by etching. As a result, a wiring portion 109 including the Ti film 109a, TiN film 109b, AlCu film 109c, and TiN film 109d is formed on the first insulating film 102.

  Next, when the photoresist 118 and the antireflection film 117 are removed, the state shown in FIG. 15 is obtained.

More specifically, the photoresist 118, the antireflection film 117, and the etching residue are removed by O ₂ plasma ashing treatment and chemical treatment.

  Thereafter, by depositing the third insulating film 157 of FIG. 6 as in the first embodiment, an air gap can be selectively formed between the wirings.

  As described above, even when the semiconductor device manufacturing method of the second embodiment is performed, the same effects as those of the first embodiment can be obtained.

  The manufacturing method of the semiconductor device according to the first and second embodiments can be widely applied to the field related to a fine semiconductor device capable of high-speed operation.

  In the first and second embodiments, the connection plug 112 is connected to the conductor film of the wiring portion 108 and the connection plug 112 is connected to the wiring portion 109. The connection plug 112 may be prevented from being connected, and the connection plug 112 may be connected to the wiring portion 109. Alternatively, the connection plug 112 may be connected to the conductor film of the wiring portion 108, and the connection plug 112 may not be connected to any of the wiring portions 109.

FIG. 1 is a schematic view of a semiconductor device according to a first embodiment of the present invention as viewed from above. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. FIG. 3 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment. FIG. 4 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment. FIG. 5 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment. FIG. 6 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment. FIG. 7 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment. FIG. 8 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment. FIG. 9 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the first embodiment. FIG. 10 is a schematic cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 11 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment. FIG. 12 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment. FIG. 13 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment. FIG. 14 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment. FIG. 15 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of the second embodiment. FIG. 16 is a schematic cross-sectional view for explaining a conventional method for manufacturing a semiconductor device disclosed in Patent Document 1. FIG. 17 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 1. FIG. 18 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 1. FIG. 19 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 1. FIG. 20 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 1. FIG. 21 is a schematic cross-sectional view for explaining another conventional method for manufacturing a semiconductor device of Patent Document 2. In FIG. FIG. 22 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 2. FIG. 23 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 2. FIG. 24 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 2. FIG. 25 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 2. FIG. 26 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 2. FIG. 27 is a schematic cross-sectional view for explaining the method for manufacturing the semiconductor device of Patent Document 2. FIG. 28 is a schematic cross-sectional view for explaining the method of manufacturing the semiconductor device of Patent Document 2.

Explanation of symbols

101 Semiconductor substrate 102 First insulating film 103 First wiring metal film 103a Ti film 103b TiN film 103c AlCu film 103d TiN film 104 Second insulating film 105 Photoresist 106 Second insulating film 107 Photoresist 108 Wiring part 108a Ti film 108b TiN film 108c AlCu film 108d TiN film 108e SiO ₂ film 109 Wiring part 109a Ti film 109b TiN film 109c AlCu film 109d TiN film 110 Third insulating film 111 Air gap 112 Connection plug 113 Second wiring metal film 113a Ti film 113b TiN film 113c AlCu film 113d TiN film 114 fourth insulating film 115 the wiring 115a Ti film 115b TiN film 115c AlCu film 115 d TiN film 115e SiO ₂ film 116 fifth insulating film 117 Barrier layer 118 photoresist 0.99 MOS field-effect transistor 151 contact plug 152 STI morphism
153 Bonding pad 154 Via hole 155 First region 156 Second region 157 Third insulating film 158 Third insulating film

Claims (8)

A semiconductor substrate;
A first insulating film formed on the semiconductor substrate;
A plurality of first wiring portions including a conductor film formed on the first insulating film and a second insulating film formed on the conductor film and extending in parallel with each other;
A plurality of second wiring portions made of only a conductor film formed on the first insulating film and extending in parallel with each other;
A third insulating film covering the top and side surfaces of the first wiring portion and the second wiring portion;
A via hole reaching at least one of the conductor film of the first wiring portion or the second wiring portion from the upper surface of the third insulating film;
A connection plug formed in the via hole and connected to the conductor film of the first wiring portion or the second wiring portion;
The third insulating film is
A first region defined by at least one side surface of the plurality of first wiring portions and having a first aspect ratio in a cross section orthogonal to a direction in which the first wiring portion extends;
Based on the first aspect ratio in a cross section defined by at least one side surface of the plurality of first wiring portions and the second wiring portions and orthogonal to the extending direction of the first wiring portions and the second wiring portions. And a second region having a small second aspect ratio,
There is an air gap that is a closed space in the first region, and there is no air gap that is a closed space in the second region,
The semiconductor device, wherein the via hole and the connection plug are connected to a conductor film of the first wiring portion or the second wiring portion having a side surface defining the second region. The semiconductor device according to claim 1,
A via hole and a connection plug are connected to the conductor film of the wiring part having a side surface defining the first region, the first wiring part width being wider than the minimum wiring part width of the plurality of first wiring parts. A semiconductor device which is characterized by being made. The semiconductor device according to claim 1 or 2,
The semiconductor device according to claim 1, wherein the first aspect ratio is in a range of 1 to 5. In the semiconductor device according to any one of claims 1 to 3,
The semiconductor device according to claim 1, wherein the second aspect ratio is greater than 0 and 4 or less. A plurality of first wiring portions including a conductor film formed on the first insulating film deposited on the semiconductor substrate and a second insulating film formed on the conductor film, and extending in parallel with each other. Forming on the first insulating film a plurality of second wiring portions formed only on the first insulating film and made only of the conductor film and extending in parallel with each other; When,
Depositing a third insulating film on the first wiring portion and the second wiring portion, and covering the side surfaces and the upper surface of the first wiring portion and the second wiring portion with the third insulating film; ,
Forming a via hole that reaches at least one of the conductor film of the first wiring portion or the second wiring portion from the upper surface of the third insulating film;
Forming a connection plug connected to the conductor film of the first wiring portion or the second wiring portion in the via hole,
The third insulating film is
A first region defined by at least one side surface of the plurality of first wiring portions and having a first aspect ratio in a cross section orthogonal to a direction in which the first wiring portion extends;
Based on the first aspect ratio in a cross section defined by at least one side surface of the plurality of first wiring portions and the second wiring portions and orthogonal to the extending direction of the first wiring portions and the second wiring portions. And a second region having a small second aspect ratio,
Further, the third insulating film is formed so that there is no air gap in the second region, so that the first region has an air gap which is a closed space,
The method of manufacturing a semiconductor device, wherein the via hole and the connection plug are formed so as to be connected to the first wiring portion or the second wiring portion having a side surface defining the second region. In the manufacturing method of the semiconductor device according to claim 5,
A via hole and a connection plug are formed in a wiring part formed so that a wiring part width of the first wiring part having a side surface defining the first region is wider than a minimum wiring part width of the plurality of first wiring parts. A method for manufacturing a semiconductor device, characterized by comprising: In the manufacturing method of the semiconductor device according to claim 5 or 6,
The method of manufacturing a semiconductor device, wherein the first aspect ratio is in a range of 1 to 5. In the manufacturing method of the semiconductor device according to any one of claims 5 to 7,
The method of manufacturing a semiconductor device, wherein the second aspect ratio is greater than 0 and 4 or less.

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