JP2009122636A - Electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electro-optical device in which a drive circuit can be arranged for a signal line along a deformed portion when the outer peripheral portion provided in the extending direction of the signal line in a pixel region is curved or bent. <P>SOLUTION: On an element substrate 10 of the electro-optical device 100, the pixel region 10b has a curved outer peripheral portion opposite scanning line drive circuits 104a, 104b. In the scanning line drive circuits 104, circuit blocks 4a, 4b, 4c, 4d having unit circuit blocks 4 equipped with one or more unit circuits are arranged along the outer periphery of the pixel region 10b while shifting in the extending direction of a scanning line 3a and/or the extending direction of a data line 6a. One type of unit circuit block with the same plane configuration is used for the unit circuit block 4. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an electro-optical device such as a liquid crystal device, an organic electroluminescence (hereinafter referred to as organic EL) device, an inorganic electroluminescence device, a plasma display device, an electrophoretic display device, and a device using an electron-emitting device.

  Typical examples of the electro-optical device include a liquid crystal device and an organic EL device. The electro-optical device includes a plurality of scanning lines and a plurality of data lines extending on the element substrate in directions intersecting each other. Is provided with a pixel region in which a plurality of pixels corresponding to the intersections are arranged. A scanning line driving circuit that outputs signals to the scanning lines is arranged in a direction in which the plurality of scanning lines outside the pixel region extends. Further, a data line driving circuit for outputting signals to the plurality of data lines is arranged in the extending direction of the plurality of data lines. In addition, a connection terminal to which a flexible substrate to which a signal is supplied from the outside of the element substrate is connected in the direction in which the scanning line or the data line extends outside the pixel region. In addition, a region in which a connection wiring for connecting both of them is provided between the region where the driving circuit and the connection terminal are arranged and the scanning line or the data line.

  In the electro-optical device having such a configuration, each of the element substrate and the pixel region has a rectangular planar shape. Therefore, in the scanning line driving circuit, a unit corresponding to a plurality of scanning lines on a one-to-one basis. The circuit should be arranged along the side of the pixel region.

  On the other hand, an electro-optical device has been proposed that includes a circular pixel region on a hexagonal element substrate (see Patent Document 1).

JP 2006-276361 A (FIG. 12)

  In the electro-optical device described in Patent Document 1, the scanning line driving circuit is disposed in the extending direction of the data line and is not disposed in the extending direction of the scanning line. If the scanning line driving circuit is linearly arranged in the direction in which the data lines extend, it is necessary to form the outer region of the pixel region wider on the element substrate, and the electro-optical device becomes larger for the size of the pixel region. There is a problem that.

  In view of the above problems, the problem of the present invention is that along the deformed portion when the outer peripheral portion located in the extending direction of the signal line in the pixel region is a deformed portion composed of a curved portion or a bent portion. An object of the present invention is to provide an electro-optical device in which a driving circuit for the signal line can be arranged.

  As shown in FIG. 15A, when a circular pixel region 10b is formed on an irregularly shaped element substrate 10 other than a quadrangle, the length dimension of the data line driving circuit 101 is the width dimension of the pixel area 10. It is impossible to extend the data line 6a straight as it is. Therefore, as shown in FIG. 15B, in the routing area (wiring area) of the data line 6a, the data line 6a extends as parallel as possible while being bent at a necessary portion and led to the data line driving circuit 101. There is a need.

  However, when the data line 6a is routed as shown in FIG. 15B, the pitch of the routing portion of the data line 6a is wide in the data line 6a extending in the center of the pixel region 10b, whereas in the pixel region 10b. The portion of the data line 6a extending on both sides of the line has a very narrow pitch, resulting in a region where the pitch is extremely different. For this reason, as shown in FIG. 16A, in the data line 6a located in the center of the pixel region 10a, the capacitance component parasitic between the routing portions of the adjacent data lines 6a is small, so that the voltage rises quickly. On the other hand, in the data line 6a located at both ends of the pixel region 10b, the capacitance component that is parasitic between the routing portions of the adjacent data lines 6a is large, so that the rise of the voltage is delayed. As a result, when an image is displayed in the pixel area 10b, a clear difference in gradation and brightness occurs between the center of the pixel area 10b and both sides of the pixel area 10b, and the image quality is low. is there.

  Note that the configurations shown in FIGS. 15A and 15B are reference examples devised by the inventors of the present application to explain the present invention, and are not conventional examples.

  In order to solve the above-described problems, the present invention provides a first signal line (scanning line 3a or data line 6a) and a second signal line (data line) extending in a direction intersecting each other on an element substrate (element substrate 10). Line 6a or scanning line 3a), a pixel region (pixel region 10a, 10b) in which a pixel electrode (pixel electrode 9a) is arranged corresponding to the intersection of the first signal line and the second signal line, and the pixel region And a signal output circuit (a connection terminal to the scanning line driving circuit 104, the data line driving circuit 101, or a flexible substrate) that outputs a driving signal to the second signal line, and the signal output circuit and the second signal output circuit. In an electro-optical device (electro-optical device 100) having a connection wiring (output line 46 or output line 44) for connecting a signal line, the outer peripheral edge of the pixel region has a curved portion or a portion facing the signal output circuit. The length dimension of the region in which the signal output circuit is arranged in the direction orthogonal to the second signal line, including a curved portion, is the width dimension of the pixel region in the direction orthogonal to the extending direction of the second signal line. A plurality of virtual reference lines (virtual reference lines L (virtual reference lines L1, L2, L3, L4)) set so as to cross the area in a shorter area where the connection wiring is routed, and the virtual reference If a virtual connection wiring that connects a plurality of virtual reference points set at predetermined intervals on the line and the virtual reference points of adjacent virtual reference lines (virtual reference points P) is provided, the connection wiring It is characterized by being routed over the connection wiring (virtual connection wiring Q (virtual connection wiring Q1, Q2, Q3)) or along the virtual connection wiring.

  In the present invention, a curved portion or a bent portion is directed to the outer peripheral edge of the pixel region facing the region where the signal output circuit is disposed, and the length dimension of the region where the signal output circuit is disposed (for example, a data line) The dimension of the region in which the data line driving circuit 101 (signal output circuit) is arranged in the direction orthogonal to the extending direction of 6a (second signal line) is the width dimension of the pixel region (for example, the data line 6a (second signal line)). Signal line) is shorter than the dimension of the pixel region 10b in the direction orthogonal to the extending direction of the signal line). Therefore, the region where the connection wiring (for example, the output line 46) is wired is narrow and curved or bent. There will be a part.

  However, in the present invention, each connection wiring is set at a predetermined interval on the plurality of virtual reference lines in each region sandwiched between the plurality of virtual reference lines set so as to cross the region where the connection wiring is wired. In the region sandwiched between the virtual reference lines, the adjacent connection wirings are routed and wired along the virtual connection lines that connect the plurality of virtual reference points. There is no great difference in the distance between them. Therefore, between the connection wiring connected to the second signal line located in the center of the pixel region and the connection wiring connected to the second signal line located at both ends of the pixel region, the adjacent connection wirings There is no big difference in the interval. Therefore, a large difference does not occur in the capacitance component parasitic between the routing portions of the adjacent connection wirings, so that a large difference does not occur in the voltage rising speed. Therefore, when an image is displayed in the pixel area, there is no difference in gradation and brightness between the center of the pixel area and both sides of the pixel area, so that the image quality is high.

  Further, in the present invention, the predetermined interval is an equal interval, and the plurality of virtual reference lines are set at four or more locations separated in the extending direction of the region where the connection wiring is routed. Features. In this way, by setting the virtual reference points at equal intervals, a large difference does not occur in the interval between adjacent connection wirings. Further, if virtual reference lines are set at four or more locations, the connection wiring can be properly routed in many cases.

  In the present invention, the plurality of virtual reference lines are set in parallel to each other. If comprised in this way, the routing part of connection wiring can be designed easily.

  In the present invention, it is further preferable that each of the plurality of virtual reference lines extends in a direction orthogonal to an extending direction of the second signal line in the pixel region. If comprised in this way, the routing part of connection wiring can be designed easily.

  In the present invention, the element substrate may further include a region where a second signal output circuit for outputting a signal to the first signal line is disposed outside the pixel region, and the connection wiring is wired The region to be formed is at least partially located between the pixel region and the region where the second signal output circuit is disposed. That is, when at least a part of the region where the connection wiring is wired is located between the pixel region and the region where the second signal output circuit is disposed, the region where the connection wiring is wired accordingly. However, according to the present invention, the connection wiring can be properly routed even if there is such a limitation.

  In the present invention, the second signal line is a data line, and the signal output circuit is a data line driving circuit. Alternatively, the second signal line is a scanning line, and the signal output circuit is a scanning line driving circuit. Thus, an electro-optical device corresponding to the data line driving circuit or the scanning line driving circuit can be realized.

  Further, the invention is characterized in that the planar shape of the pixel region is a circle or a shape formed by combining a curve and a straight line. The term “circular” in the present invention means a shape of an athletics track (oval, rounded rectangle) in which a semicircle is combined with both ends of a perfect circle, an ellipse, or a rectangle, and a shape including a circle on the outer periphery. It is meant to include any shape. In addition, “circular” in the present invention is meant to include those having some unevenness and step portions on the circumference.

  Furthermore, the present invention is characterized in that the planar shape of the element substrate is a circle, a triangle, a polygon of pentagon or more, or a shape formed by combining a curve and a straight line. With this configuration, the outer peripheral shape of the element substrate can be formed so as to follow the outer peripheral shape of the pixel region, so that the width dimension of the outer region of the deformed portion including the curved portion or the bent portion can be further compressed.

  When the electro-optical device to which the present invention is applied is a liquid crystal device, the element substrate has a configuration in which a liquid crystal layer is held between the element substrate and a counter substrate disposed to face the element substrate.

  When the electro-optical device to which the present invention is applied is an organic EL device, the element substrate includes an organic EL element in each of the plurality of pixels.

  An electro-optical device to which the present invention is applied is used as a direct-view display unit or the like in an electronic device such as a watch or a mobile phone.

  Embodiments of the present invention will be described below. In the drawings to be referred to in the following description, the scales of the layers and the members are different from each other in order to make the layers and the members large enough to be recognized on the drawings. Note that in a thin film transistor, a source and a drain are switched depending on an applied voltage. However, in the following description, for convenience of explanation, a side to which a pixel electrode is connected will be described as a drain. Further, illustration of a color filter, an alignment film, and the like is omitted.

[Embodiment 1]
(overall structure)
FIG. 1 is a block diagram showing an electrical configuration of an electro-optical device (liquid crystal device) according to Embodiment 1 of the present invention. As shown in FIG. 1, the electro-optical device 100 of the present embodiment is a liquid crystal device, and a plurality of scanning lines 3a (first signal lines) extending on the element substrate 10 in the X direction and the Y direction intersecting each other. A plurality of pixels 100a are formed at positions corresponding to intersections with the plurality of data lines 6a (second signal lines). On the element substrate 10, a pixel area 10 b is configured by an area in which a plurality of pixels 100 a are arranged. The pixel area 10 b is an image display area 10 a for displaying an image in the electro-optical device 100. Used. However, dummy pixels that do not directly contribute to the display may be formed along the outer periphery of the pixel area 10b. In this case, the image display area 10a is configured by an area excluding the dummy pixels in the pixel area 10b. Is done.

  In the element substrate 10, in the outer region of the pixel region 10 b, scanning line driving circuits 104 a (signal output circuits) and 104 b (signal output circuits) are formed on both sides where the scanning lines 3 a extend, and the data lines 6 a are formed. A data line driving circuit 101 (signal output circuit) is formed on the extending side. The scanning line driving circuits 104a and 104b and the data line driving circuit 101 are formed on the element substrate 10 in addition to a configuration formed by using a thin film transistor formed on the element substrate 10 by SOG (system on glass) technology. It may be mounted as a driving IC. In any case, the scanning line driving circuits 104a and 104b function as regions where signal output circuits for the ends of the scanning lines 3a are arranged. For this reason, all the scanning lines 3 a are routed to the scanning line driving circuits 104 a and 104 b through the connection wiring 44.

  The electro-optical device 100 illustrated in FIG. 1 has a so-called double-sided input configuration in which the scanning line driving circuits 104a and 104b are connected to the left and right sides of the scanning line 3a. Therefore, the scanning line driving circuits 104a and 104b on both sides are configured by the same circuit and are driven in synchronization, so that each line of the scanning line 3a is simultaneously driven from the scanning line driving circuits 104a and 104b on both sides. To do. By simultaneously inputting the driving signals from the scanning line driving circuits 104a and 104b to both lines of the scanning line 3a from both sides, it is possible to prevent malfunction due to the rounding or delay of the driving signal due to the resistance component of the scanning line 3a. The reliability of the electro-optical device 100 can be improved. The scanning line driving circuits 104a and 104b do not necessarily need to be connected on both the left and right sides of the scanning line 3a. The scanning line 3a is alternated between the scanning line driving circuit 104a or 104b on one side and the scanning line driving circuit 104a or 104b. Alternatively, the scanning lines 3a may be divided at the top and bottom in the scanning direction, and the scanning line driving circuit 104a or 104b on one side may be connected to each. Alternatively, the scanning line driving circuit 104a or 104b may be disposed only on one side of the pixel region 10b and connected to all the scanning lines 3a.

  The data line driving circuit 101 functions as a region where a signal output circuit for the end of the data line 6a is disposed. For this reason, all the data lines 6 a are routed to the data line driving circuit 101 via the connection wiring 46. In this embodiment, among the scanning line driving circuits 104a and 104b and the data line driving circuit 101, the scanning line driving circuit 104 is formed using a thin film transistor formed on the element substrate 10, and the data line driving circuit 101 is formed on the element substrate. 10 is constituted by a driving IC mounted on the board 10.

  In each of the plurality of pixels 100a, a pixel electrode 9a and a pixel switching thin film transistor 30a (pixel transistor) for controlling the pixel electrode 9a are formed. The data line 6a extending from the data line driving circuit 101 is electrically connected to the source of the thin film transistor 30a, and the data line driving circuit 101 supplies image signals to the data line 6a in a line sequential manner. The scanning line 3a connected to the scanning line driving circuits 104a and 104b is electrically connected to the gate of the thin film transistor 30a, and the scanning line driving circuits 104a and 104b supply scanning signals to the scanning line 3a in a line sequential manner. . The pixel electrode 9a is electrically connected to the drain of the thin film transistor 30a. In the electro-optical device 100, by turning on the thin film transistor 30a for a certain period, an image signal supplied from the data line 6a is supplied to each pixel. Data is written into the liquid crystal capacitor 50a of 100a at a predetermined timing. An image signal of a predetermined level written in the liquid crystal capacitor 50a is held for a certain period between a pixel electrode 9a formed on the element substrate 10 and a common electrode on a counter substrate described later. A storage capacitor 60 is formed between the pixel electrode 9a and the common electrode, and the voltage of the pixel electrode 9a is held, for example, for a time that is three orders of magnitude longer than the time when the source voltage is applied. As a result, the charge retention characteristic is improved, and the electro-optical device 100 capable of performing display with a high contrast ratio is realized. In this embodiment, when the storage capacitor 60 is configured, the capacitor line 3b is formed in parallel with the scanning line 3a. However, the storage capacitor 60 may be formed between the previous scanning line 3a. In the case of a fringe field switching (FFS) mode liquid crystal device, the common electrode is formed on the element substrate 10 in the same manner as the pixel electrode 9a.

(Specific configuration of electro-optical device 100)
2A, 2B, 3A, and 3B are a plan view of the electro-optical device 100 according to the first embodiment of the present invention and a plan view of the element substrate 10, respectively. 4A and 4B are a plan view of two adjacent pixels and a cross-sectional view of one pixel in the element substrate 10 of the electro-optical device 100 according to Embodiment 1 of the present invention. is there. 4B is a cross-sectional view taken along the line AA ′ in FIG. 4A. In FIG. 4A, the pixel electrode 9a is indicated by a long dotted line, and is formed simultaneously with the data line 6a. The thin film is indicated by a one-dot chain line, the scanning line 3a is indicated by a solid line, and the semiconductor layer is indicated by a short dotted line.

  In this embodiment, the electro-optical device 100 is specifically configured as shown in FIGS. 2 (a) and 2 (b), FIGS. 3 (a) and 3 (b), and FIGS. 4 (a) and 4 (b). ing. First, the counter substrate 20 and the element substrate 10 are bonded to each other on the element substrate 10 by the sealing material 107, and the liquid crystal 50 is held in a region surrounded by the sealing material 107. The liquid crystal 50 is made of, for example, one or a mixture of several types of nematic liquid crystals. In addition, a conductive material (not shown) for electrical connection between the element substrate 10 and the counter substrate 20 is disposed.

  As shown in FIGS. 4A and 4B, a plurality of transparent pixel electrodes 9a are formed in a matrix on the element substrate 10 for each pixel 100a, and along the vertical and horizontal boundary regions of the pixel electrode 9a. Data lines 6a and scanning lines 3a extend. In the element substrate 10, the capacitor line 3 b is formed in parallel with the scanning line 3 a.

  The base of the element substrate 10 shown in FIG. 4B includes a support substrate 10d such as a quartz substrate or a heat resistant glass substrate, and the base of the counter substrate 20 is a support substrate 20d such as a quartz substrate or a heat resistant glass substrate. Consists of. In the element substrate 10, a base insulating layer 12 made of a silicon oxide film or the like is formed on the surface of the support substrate 10d, and on the surface side, a thin film transistor 30a is formed in a region corresponding to the pixel electrode 9a. The thin film transistor 30a is an LDD (Lightly Doped) in which a channel region 1g, a low concentration source region 1b, a high concentration source region 1d, a low concentration drain region 1c, and a high concentration drain region 1e are formed on an island-shaped semiconductor layer 1a. Drain) structure. A gate insulating layer 2 made of a silicon oxide film or a silicon nitride film is formed on the surface side of the semiconductor layer 1a, and a gate electrode (scanning line 3a) is formed on the surface of the gate insulating layer 2. The semiconductor layer 1a is a polysilicon film that is polycrystallized by laser annealing or lamp annealing after an amorphous silicon film is formed on the element substrate 10. The semiconductor layer 1a may be formed of a single crystal silicon layer, and the gate insulating layer 2 may be formed by thermal oxidation on the surface of the semiconductor layer 1a.

  On the upper layer side of the thin film transistor 30a, an interlayer insulating layer 71 made of a silicon oxide film or a silicon nitride film, an interlayer insulating layer 72 made of a silicon oxide film or a silicon nitride film, and a thick photosensitive film having a thickness of 1.5 μm to 2.0 μm. An interlayer insulating film 73 (flattening film) made of a conductive resin is formed. A data line 6 a and a drain electrode 6 b are formed on the surface of the interlayer insulating layer 71 (between the interlayer insulating films 71 and 72). The data line 6 a has a high concentration via a contact hole 71 a formed in the interlayer insulating layer 71. It is electrically connected to the source region 1d. The drain electrode 6b is electrically connected to the high concentration drain region 1e through a contact hole 71b formed in the interlayer insulating layer 71. A pixel electrode 9 a made of an ITO film is formed on the surface of the interlayer insulating layer 73. The pixel electrode 9 a is electrically connected to the drain electrode 6 b through a contact hole 73 a formed in the interlayer insulating layers 72 and 73. An alignment film 16 made of a polyimide film is formed on the surface side of the pixel electrode 9a. Further, for the extended portion 1f (lower electrode) from the high concentration drain region 1e, the capacitance of the same layer as the scanning line 3a is provided via an insulating layer (dielectric film) formed simultaneously with the gate insulating layer 2. The storage capacitor 60 is configured by the line 3b facing as an upper electrode.

  In this embodiment, the scanning line 3a and the capacitor line 3b are conductive films formed at the same time, and are made of a single metal film such as a molybdenum film, an aluminum film, a titanium film, a tungsten film, a tantalum film, or a chromium film, or a laminated film thereof. Become. The data line 6a and the drain electrode 6b are conductive films formed simultaneously, and are made of a single metal film such as a molybdenum film, an aluminum film, a titanium film, a tungsten film, a tantalum film, or a chromium film, or a laminated film thereof.

  In the counter substrate 20, a light shielding film 23 is formed in a region overlapping between the pixel electrodes 9 a formed on the element substrate 10, and a common electrode 21 made of an ITO film is formed on the upper side of the light shielding film 23. An alignment film 22 is formed on the surface. Here, when the electro-optical device 100 is configured for color display, a color filter (not shown) is formed on each of the plurality of pixels 100 a on the counter substrate 20.

  The element substrate 10 and the counter substrate 20 configured as described above are disposed so that the pixel electrode 9a and the common electrode 21 face each other, and the sealing material 107 (see FIG. The liquid crystal 50 as an electro-optical material is sealed in the space surrounded by (). The liquid crystal 50 takes a predetermined alignment state by the alignment films 16 and 22 in a state where the electric field from the pixel electrode 9a is not applied.

  In this embodiment, the electro-optical device 100 is configured as a transmissive liquid crystal device, but may be configured as a reflective liquid crystal device or a transflective liquid crystal device.

(Configuration of the scanning line driving circuits 104a and 104b)
5A and 5B are plan views schematically showing a state in which circuit blocks are arranged outside the pixel region 10b in the element substrate 10 of the electro-optical device 100 according to Embodiment 1 of the present invention. And an explanatory diagram of one circuit block. FIG. 6 is a plan view schematically showing an enlarged connection portion between a circuit block and a scanning line arranged in the outer region of the pixel region 10b in the element substrate 10 of the electro-optical device 100 according to the first embodiment of the present invention. FIG. In FIG. 5A, illustration of the scanning line 3a, the capacitor line 3b, and the data line 6a in the pixel region 10b is omitted. FIG. 6 shows only a part of the scanning lines connected to the scanning line driving circuit shown in the figure, among the wirings formed in the pixel region 10b. The capacitor line 3b, the data line 6a, and the circuit block are shown in FIG. The illustration of the wiring that connects them is omitted, and the illustration of the scanning line 3a connected to the scanning line driving circuit disposed on the opposite side to the pixel region 10b is also omitted. Furthermore, the outer peripheral edge of the pixel region 10b has a stepped portion along the pixel 100a, but the actual pixel 100 has a larger number and is smaller than the form shown in FIGS. 2 (a) and 6. Therefore, in FIG. 2A, FIG. 5 and FIG. 6, the pixel region 10b is represented as a complete circle.

  As shown in FIGS. 2A and 2B and FIGS. 3A and 3B, the electro-optical device 100 according to the present embodiment has a planar shape of the element substrate 10 in which a semicircle and a straight line are combined. Corresponding to this shape, the planar shape of the counter substrate 20 also has a deformed shape combining a semicircle and a straight line. Further, the planar shape of the pixel region 10b may be a slightly vertically long oval or elliptical shape (FIGS. 2A and 2B), or a perfect circular shape (FIGS. 3A and 3B). )It has become. For this reason, the pixel region 10b includes a deformed outer peripheral edge portion including a curved portion in a portion facing the scanning line driving circuits 104a and 104b.

  The element substrate 10 includes an extended region 19 that protrudes from one linear end of the counter substrate 20 in the extending direction of the data line 6 in the pixel region 10b. In the overhang area 19, the data line driving circuit 101 is arranged along the side portion, and a flexible substrate 108 is connected to the pad 102 formed at the end of the overhang area 19. In the element substrate 10, scanning line driving circuits 104 a and 104 b are disposed on the outer region 10 x of the pixel region 10 b on the side positioned in the extending direction of the scanning line 3 a, and the scanning line driving circuits 104 a and 104 b The element substrate 10 is formed so as to extend along the outer peripheral edge.

  In the electro-optical device 100 configured as described above, the scanning line 3 a is connected to the scanning line driving circuits 104 a and 104 b via the connection wiring 44. In order to realize such a structure, in the present embodiment, the following configuration is adopted because the portion of the pixel region 10b facing the scanning line driving circuits 104a and 104b has a curved shape.

  First, as shown in FIGS. 5A and 6, the scanning line driving circuits 104 a and 104 b include a plurality of circuit blocks 4 a, 4 b, 4 c, and 4 d, and the plurality of circuit blocks 4 a, 4 b, In 4c and 4d, adjacent circuit blocks are arranged along the outer peripheral edge of the pixel region 10b while being shifted from each other in the extending direction (X direction) of the scanning line 3a and / or the extending direction (Y direction) of the data line 6a. Has been.

  Here, the circuit blocks 4a, 4b, 4c, and 4d are configured by combining one or a plurality of unit circuit blocks 4 as shown in FIG. 5B. The unit circuit block 4 includes a plurality of unit circuits 40 that output scanning signals on a one-to-one basis with respect to the end portions of the scanning lines 3a. Each of the plurality of unit circuits 40 includes, for example, a shift register 41 including two clocked inverters and one inverter, and a buffer 42 including two inverters, and extends from each of the plurality of unit circuits 40. The output line 44 to be connected is connected to the end of the scanning line 3a. Within the circuit block 4, the plurality of unit circuits 40 have substantially the same circuit configuration, wiring structure, and the like, and the pitches of the plurality of output lines 44 are also the same. The buffer 42 may be a NOR gate or an AND gate.

  In this embodiment, in the plurality of circuit blocks 4a, 4b, 4c, and 4d shown in FIGS. 5A and 6, the configuration and the number of unit circuits 40 of the unit circuit block 4 included in each, the number of output lines 44, The pitch and the like are the same, and the unit circuit blocks 4 have the same planar configuration (planar size and planar shape). Therefore, the scanning line driving circuit 101 is composed of one type of unit circuit block 4.

  The circuit blocks 4a, 4b, 4c, 4c, 4c, 4c, 4d, 4d,... Are configured by combining unit circuit blocks 4 in one or more units. The number of the unit circuit blocks 4 is appropriately selected so as to be easily arranged along the outer peripheral edge of the pixel region 10b. 5A and 6, the circuit block 4a is configured by combining four unit circuit blocks 4, and the circuit block 4b includes two unit circuit blocks 4, circuit blocks 4c and 4d. Is composed of one unit circuit block 4 each.

  In the circuit blocks 4a, 4b, 4c, and 4d, adjacent circuit blocks are shifted in both / or one of the extending direction of the data line 6a (Y direction) and the extending direction of the scanning line 3a (X direction). It is arranged while curving.

  Here, the circuit blocks 4c, 4c, 4c, and 4c have a shift amount in the extending direction (Y direction) of the data line 6a between adjacent circuit blocks and a shift in the extending direction (X direction) of the scanning line 3a. The quantities are arranged equally between adjacent circuit blocks.

  On the other hand, in the circuit blocks 4d, 4d,..., The shift amount in the extending direction (Y direction) of the data lines 6a between the adjacent circuit blocks differs between the adjacent circuit blocks, and scanning is performed. The amount of deviation in the extending direction (X direction) of the line 3a is also different between adjacent circuit blocks. Further, the circuit block 4d may be arranged in the X direction when the shift amount in the extending direction (X direction) of the scanning line 3a is larger than the length of the circuit block 4d in the X direction.

  In this way, the plurality of circuit blocks 4a, 4b, 4c, and 4d are arranged in a curved shape so as to faithfully follow the curved shape of the portion facing the scanning line driving circuits 104a and 104b at the outer periphery of the pixel region 10b. As a result, the scanning line driving circuits 104a and 104b are configured in a curve along the pixel region 10b.

  Thus, in arranging the circuit blocks 4a, 4b, 4c, and 4d, the circuit blocks are displaced in the extending direction (X direction) of the scanning line 3a, that is, the circuit blocks are displaced in the oblique direction. For this reason, in the circuit blocks 4a, 4b, 4c, and 4d, it is necessary to connect the circuit blocks to each other by wiring, and it is necessary to secure a wiring routing area 4z.

  Therefore, in this embodiment, as shown in FIG. 6, in all the circuit blocks 4, the pitch P4 of the output lines 44 drawn from the circuit blocks 4a, 4b, 4c and 4d is a scanning line to which the output lines 44 are to be connected. The output is different in pitch by providing a relay portion 45 extending in the extending direction of the data line 6a between the output line 44 and the scanning line 3a, which is narrower than the pitch P3 of 3a. The line 44 and the scanning line 3a are connected. Therefore, even if the circuit block is displaced in the extending direction (X direction) of the scanning line 3a, the wiring routing region 4z can be secured sufficiently and easily.

(Main effects of this form)
As described above, in the element substrate 10 used in the electro-optical device 100 of the present embodiment, the scanning line driving circuit 104a is located in the region located in the extending direction of the plurality of scanning lines 3a in the outer region 10x of the pixel region 10b. 104b, and the outer peripheral edge of the pixel region 10b is provided with a deformed outer peripheral portion including a curved portion at a portion facing the scanning line driving circuits 104a and 104b. For this reason, in the scanning line driving circuits 104a and 104b, the unit circuit 40 that outputs a signal on the scanning line 3a on a one-to-one basis cannot be linearly arranged. However, in this embodiment, a plurality of unit circuits 40 are provided. A plurality of circuit blocks 4a, 4b, 4c, and 4d are arranged along the outer peripheral edge of the pixel region 10b while shifting in the extending direction of the scanning line 3a (X direction) and / or the extending direction of the data line 6a (Y direction). It is. For this reason, even when the outer peripheral portion located in the extending direction of the scanning line 3a is a curved portion, the scanning line driving circuits 104a and 104b can be arranged along the curved portion. Therefore, in the element substrate 10, it is not necessary to configure the outer region 10x of the pixel region 10b to be wide.

  In particular, in the present embodiment, the plurality of circuit blocks 4a, 4b, 4c, and 4d are arranged such that adjacent circuit blocks are mutually in the extending direction of the scanning line 3a (X direction) and the extending direction of the data line 6a (Y direction). It is shifted. In addition, the plurality of circuit blocks 4a, 4b, 4c, and 4d have a shift amount between adjacent circuit blocks in the extending direction (X direction) of the scanning lines 3a and a shift amount in the extending direction (Y direction) of the data lines 6a. The amount is different. Therefore, since the circuit blocks 4a, 4b, 4c, and 4d can be arranged more faithfully along the curved portion of the pixel region 10b, the width dimension of the outer region 10x of the pixel region 10b can be further compressed.

  In addition, the position of each unit circuit 40 is not shifted along the outer peripheral shape of the pixel region 10b, but the circuit blocks 4a, 4b, 4c each having one or a plurality of unit circuit blocks 4 each including a plurality of unit circuits 40. Since the position of 4d is shifted along the outer peripheral shape of the pixel region 10b, the layout of the scanning line driving circuits 104a and 104b can be simplified and the design is easy. In addition, in this embodiment, since the circuit blocks 4a, 4b, 4c, and 4d are used by combining one or a plurality of one type of unit circuit blocks 4 having the same planar layout of the unit circuit 40, the scanning line Since the configuration of the drive circuits 104a and 104b can be simplified, the design is easy.

  Further, since the pitch P4 of the output lines 44 of the unit circuit block 4 is narrower than the pitch P3 of the scanning lines 3a connected to the output lines 44, the circuit blocks 4a, 4b, 4c, 4d comprising the unit circuit block 4 are used. Even when the scanning line 3a is shifted in the extending direction of the scanning line 3a, the wiring routing region 4z can be sufficiently secured between the circuit blocks 4a, 4b, 4c, and 4d.

[Modification of Embodiment 1]
In the first embodiment, the plurality of unit circuit blocks 4 have the same configuration and number of unit circuits 40, the number of output lines 44, and the pitch, and the unit circuit block 4 has a planar configuration ( However, depending on the shape of the pixel region 10b, the configuration and number of unit circuits 40, the configuration and number of output lines 44, and the configuration of the plane (planar size and shape) are different. A plurality of types of unit circuit blocks 4 may be employed.

[Embodiment 2]
FIG. 7 is a plan view schematically showing a state where the circuit blocks 4x and 4y are arranged in the outer region of the pixel region 10b in the element substrate 10 of the electro-optical device 100 according to the second embodiment of the present invention. In FIG. 7, the scanning lines 3a, the capacitor lines 3b, and the data lines 6a in the pixel region 10b are not shown. In addition, since the basic configuration of the present embodiment is the same as that of the first embodiment, common portions are denoted by the same reference numerals and description thereof is omitted.

  In the first embodiment, one unit circuit block having the same planar configuration (planar size and planar shape) is used as the unit circuit block 4 constituting the circuit blocks 4a, 4b, 4c, and 4d. As shown, two or more types of unit circuit blocks 4 ′, 4 ″, etc. having different plane configurations (plane size and shape) may be used. That is, in this embodiment, the unit circuit block 4 ′ and the unit In the circuit block 4 ″, the number of output lines 44 described with reference to FIGS. 5B and 6 is equal, but the pitch of the output lines 44 is different. Note that the pitch of the output lines 44 of the unit circuit block 4 ′ and the pitch of the output lines 44 of the unit circuit block 4 ″ are equal to the pitch of the scanning lines 3a connected to these output lines 44, or both. The circuit block 4x may be formed by combining one or more unit circuit blocks 4 ′, and the circuit block 4y may include one unit circuit block 4 ″. Composed of one or more.

  Here, the element substrate 10 includes linear portions 10s and 10t on the outer peripheral portion facing the scanning line driving circuits 104a and 104b so as to substantially conform to the shape of the outer peripheral portion of the pixel region 10b. Are connected diagonally through the corner 10u. Corresponding to this configuration, in the plurality of circuit blocks 4 configuring the scanning line driving circuit, the circuit blocks 4x and 4y are linearly arranged at two locations along each of the two linear portions 10s and 10t of the element substrate 10. Has been. That is, all the circuit blocks 4x are arranged at positions shifted in the extending direction (Y direction) of the data lines 6a, but in the extending direction (X direction) of the scanning lines 3a, They are not displaced and are linearly arranged in the extending direction (Y direction) of the data lines 6a along the straight line portion 10t. Further, in the circuit block 4x, the shift amount in the extending direction (Y direction) of the data lines 6a between the adjacent circuit blocks is the same between the adjacent circuit blocks.

  On the other hand, in the circuit block 4y, adjacent circuit blocks are shifted in both the extending direction of the data line 6a (Y direction) and the extending direction of the scanning line 3a (X direction). However, unlike the circuit blocks 4c and 4d of the first embodiment, in the circuit block 4x, the shift amount in the extending direction (X direction) of the scanning lines 3a between the adjacent circuit blocks is the same between the adjacent circuit blocks. The shift amount in the extending direction (Y direction) of the data lines 6a between adjacent circuit blocks is also the same between the adjacent circuit blocks. Therefore, the circuit block 4y is diagonally arranged in a straight line along the straight part 10s.

  Thus, also in this embodiment, the plurality of circuit blocks 4x and 4y are arranged along the outer peripheral edge of the element substrate 10 substantially along the curved shape of the portion facing the scanning line driving circuits 104a and 104b in the pixel region 10b. As a result, the scanning line driving circuits 104a and 104b are configured along the pixel region 10b. Therefore, in the element substrate 10, the outer region 10x of the pixel region 10b can be narrowed.

[Other Embodiments of Embodiment 1 and Embodiment 2]
In the above embodiment, the data line driving circuit 101 which is a signal output circuit for the data line 6a is configured by the driving IC mounted on the element substrate 10, but the data line driving circuit 101 is mounted on the element substrate 10. In addition, the present invention may be applied to an electro-optical device configured using a thin film transistor formed by SOG (system on glass) technology. Further, the present invention is applied to an electro-optical device in which the data line driving circuit 101 is not configured on the element substrate 10 and signal output to the data line 6 a is performed from the outside via a flexible substrate connected to the element substrate 10. May be. In this case, a region (connection region) where a connection terminal for a flexible substrate or the like is arranged functions as a region where a signal output circuit for the data line 6a is arranged. The present invention may be applied to an electro-optical device having such a configuration.

  In the above embodiment, the scanning line driving circuits 104a and 104b are configured on both sides of the pixel region 10b. However, the scanning line driving circuit 104a or 104b is configured only on one side of the pixel region 10b. The present invention may be applied to an electro-optical device.

  Further, in the above embodiment, the present invention is applied to configure the scanning line driving circuits 104 a and 104 b, but the present invention may be applied to configure the data line driving circuit 101. That is, in the above embodiment, the scanning line 3a is the first signal line and the data line 6a is the second signal line. However, the scanning line 3a is the second signal line, and the data line 6a is the first signal line. The present invention may be applied to the electro-optical device.

  In the first embodiment, a polysilicon film is used as the semiconductor layer 1a of the thin film transistor 30a. However, in the electro-optical device 100 in which a single crystal silicon layer or an amorphous silicon film is used as the semiconductor layer 1a of the thin film transistor 30a. The present invention may be applied.

[Embodiment 3]
(Data line 6a routing structure)
FIG. 8 shows the data line 6a (second signal line) and the data line driving circuit 101 (signal output circuit and signal output circuit) arranged on the element substrate 10 in the electro-optical device 100 according to Embodiment 3 of the present invention. It is a top view which expands and shows typically a mode that it was drawn to the area | region. FIG. 9 is an explanatory diagram of virtual reference lines and virtual reference points set for routing the data lines 6a to the data line driving circuit 101 in the electro-optical device 100 according to Embodiment 3 of the present invention. In FIGS. 8 and 9, the drawing lines of the scanning lines 3a (first signal lines) in the pixel region 10b are not shown. Further, the outer peripheral line of the pixel region 10b has a stepped portion along the pixel 100a, but the actual pixel 100a has a larger number and smaller than the forms shown in FIGS. 8 and 9, the pixel region 10b is represented as a complete circle.

  As shown in FIGS. 2A and 2B and FIGS. 3A and 3B, the electro-optical device 100 according to the present embodiment has a planar shape of the element substrate 10 in which a semicircle and a straight line are combined. Corresponding to this shape, the planar shape of the counter substrate 20 also has a deformed shape combining a semicircle and a straight line. Further, the planar shape of the pixel region 10b is a slightly vertically long oval or elliptical shape (FIGS. 2A and 2B) or a perfect circular shape (FIGS. 3A and 3B). Yes. For this reason, the pixel region 10 b includes a deformed outer peripheral edge portion formed of a curved portion at a portion facing the data line driving circuit 101.

  The element substrate 10 includes an extended region 19 that protrudes from one linear end of the counter substrate 20 in the extending direction of the data line 6 in the pixel region 10b. In the overhang region 19, the data line driving circuit 101 is disposed along the side portion, and a flexible substrate 108 is connected to the pad 102 formed at the end. In the element substrate 10, the scanning line driving circuits 104 a and 104 b are arranged on the outer region of the pixel region 10 b on the side positioned in the extending direction of the scanning line 3 a, and the scanning line driving circuits 104 a and 104 b It is formed so as to extend along the outer peripheral edge of the element substrate 10.

  In the electro-optical device 100 configured as described above, the scanning line 3a needs to be connected to the scanning line driving circuits 104a and 104b via the output line 44, and the data line 6a is connected to the data line driving circuit 101 and the data line. It is necessary to connect via the output line 46 (connection wiring) of 6a. Here, among the data lines 6a, the output lines 46 of the data lines 6a extending at both ends in the X direction of the pixel area 10b are routed areas 15 of the output lines 46 (areas where the connection wiring is wired). Among them, it is necessary to draw in a narrow and deep region sandwiched between the outer peripheral edge of the element substrate 10 and the outer peripheral edge of the pixel region 10b. Moreover, since the scanning line driving circuits 104a and 104b are formed along the outer peripheral edge of the element substrate 10, the output lines 46 of the data lines 6a extending at both end portions in the X direction of the pixel region 10b. Of the routing area 15, among the areas sandwiched between the pixel area 10 b and the outer peripheral edge of the element substrate 10, it is necessary to route in a narrow area sandwiched between the pixel area 10 b and the scanning line driving circuits 104 a and 104 b. is there.

  Here, the planar shape of the pixel region 10b is circular, and the lead-out region 15 becomes wider as it approaches the data line driving circuit 101 from both ends of the pixel region 10b. However, the pixel region 10b is extracted from the pixel region 10b accordingly. The number of output lines 46 connected to the incoming data line 6a is increasing. Furthermore, in the routing area 15, if there is a large difference in the spacing between the adjacent output lines 46, as described with reference to FIG. When a signal is applied, a large difference occurs in the rising speed of the potential.

  Therefore, in this embodiment, as shown in FIGS. 2B, 3B, and 8, in the routing region 15 of the output line 46 of the data line 6a, the extending direction of the output line 46 of the data line 6a. A plurality of virtual reference lines L are set so as to cross the routing area 15 at positions spaced apart by a plurality of virtual reference points P set at equal intervals on each of the plurality of virtual reference lines L. Is provided. The output line 46 of the data line 6a passes on a straight line (virtual connection wiring Q (Q1, Q2, Q3)) connecting the plurality of virtual reference points P in each region sandwiched between the virtual reference lines L. In addition, the data line is driven to the data line driving circuit 101 while being bent at the virtual reference point P on the virtual reference line L. Thereby, in any region sandwiched between the virtual reference lines L, the output lines 46 of the data lines 6a can be routed at substantially equal intervals.

  The output line 46 of each data line 6a may be routed along a virtual connection wiring Q that connects the plurality of virtual reference points P. Even in this case, the output line 46 of the data line 6a can be routed at substantially equal intervals in any region sandwiched between the virtual reference lines L. Further, the virtual connection wiring Q may be a line connected in a curve along the outer peripheral edge of the pixel region. In this case as well, it may be routed along or along the virtual connection wiring Q. Even in this case, the output line 46 of the data line 6a can be routed at substantially equal intervals in any region sandwiched between the virtual reference lines L.

  Further, the virtual reference points P are not limited to equal intervals, and may be set at intervals that gradually increase or decrease toward the outside of the element substrate 10. By making the intervals slightly different, it is possible to arrange the output lines 46 in a well-balanced area in a narrow, bent or bent area, and to suppress the occurrence of a large difference in the parasitic capacitance component between the output lines 46. can do.

  Such a configuration will be described in detail with reference to FIG. First, with respect to the routing area 15 of the output line 46 of the data line 6a, a plurality of virtual reference lines L, for example, four lines are provided so as to cross the routing area 15 at positions spaced in the extending direction of the routing area 15. Virtual reference lines L1, L2, L3, and L4 are set. In this embodiment, the four virtual reference lines L (virtual reference lines L1, L2, L3, and L4) are parallel to each other, and all are orthogonal to the extending direction of the data line 6a in the pixel region 10b. Yes.

  Next, a plurality of virtual reference points P corresponding to the number of output lines 46 of the passing data lines 6a are set in any of the four virtual reference lines L. At that time, the virtual reference points P are set at equal intervals in each of the four virtual reference lines L. More specifically, a portion of the virtual reference line L located within the routing area 15 is divided at equal intervals by the output line 46 of the passing data line 6a, and the virtual reference point P is set.

  For example, in the example shown in FIG. 9, among the four virtual reference lines L, the virtual reference line L1 farthest from the data line driving circuit 101 has three output lines 46 of the data lines 6 passing therethrough. Three virtual reference points P are set at equal intervals. In the next virtual reference line L2, since there are eight output lines 46 of the data line 6 passing therethrough, eight virtual reference points P are set at equal intervals. Further, in the next virtual reference line L3, since there are 15 output lines 46 of the data line 6 passing therethrough, 15 virtual reference points P are set at equal intervals. In the virtual reference line L4 closest to the data line driving circuit 101, since there are 31 output lines 46 of the data line 6 passing therethrough, 31 virtual reference points P are set at equal intervals.

  Then, as shown in FIG. 8, the output line 46 of each data line 6a is drawn from the pixel region 10b and then routed to the data line driving circuit 101 along the corresponding virtual reference point P. As a result, in each region sandwiched by the virtual reference line L, the output line 46 of the data line 6a is drawn linearly in the region sandwiched by the virtual reference line L and bent at the virtual reference line L. However, the data line driving circuit 101 is routed. With this configuration, in any region sandwiched between the virtual reference lines L, the output lines 46 of all the data lines 6a are routed at substantially equal intervals.

(Main effects of this form)
As described above, in the electro-optical device 100 according to the present embodiment, even if the shape and width of the routing region 15 of the output line 46 of the data line 6a are greatly limited due to the pixel region 10b not being a square or the like. A large difference does not occur in the interval between the output lines 46 of the adjacent data lines 6a. Therefore, between the data line 6a extending in the center of the pixel region 10b and the output line 46 of the data line 6a connecting the data line driving circuit 101 from the outer periphery of the pixel region 10b, adjacent output lines 46 are connected to each other. There is no big difference in the interval. Therefore, a large difference does not occur in the capacitance component that is parasitic in the routing portion of the output line 46 of the adjacent data line 6a. Therefore, as shown in FIG. 16B, a large difference in the voltage rising speed does not occur. Therefore, when an image is displayed in the pixel area 10b, gradation and luminance are reduced between the center of the pixel area 10b and both sides in the direction (X direction) orthogonal to the extending direction of the data line 6a in the pixel area 10b. Since no difference occurs, the image quality is high.

  In particular, in this embodiment, the planar shape of the pixel region 10b is circular, and the output line 46 of the data line 6a is a narrow recessed region sandwiched between the pixel region 10b and the scanning line driving circuit 104a or 104b. However, even in such a case, if the virtual reference line L and the virtual reference point P are used, the output lines 46 of all the data lines 6a can be routed at substantially equal intervals.

  In this embodiment, the output line 46 of the data line 6a extends linearly in each region sandwiched between the virtual reference lines L. However, since the number of virtual reference lines L is 4, The output lines 46 of the data lines 6a are also appropriately distributed, and an appropriate interval can be ensured between the output lines 46 of the adjacent data lines 6a. Here, the number of virtual reference lines L may be set to an optimum number according to the number of output lines 46 of the data line 6a and the curvature of the pixel region 10b, and if it is four or more, it is appropriate for various conditions. If there are eight, almost all conditions can be handled.

[Embodiment 4]
FIG. 10 is an explanatory diagram of virtual reference lines and virtual reference points set for routing the output line 46 of the data line 6a to the data line driving circuit 101 in the electro-optical device 100 according to Embodiment 4 of the present invention. Since the basic configuration of this embodiment is the same as that of Embodiment 3, common portions are denoted by the same reference numerals and description thereof is omitted.

  In the third embodiment, a plurality of virtual reference lines L are set parallel to each other, and the virtual reference lines L are set in a direction orthogonal to the extending direction of the data lines 6a in the pixel region 10b. As shown in FIG. 7, a configuration in which the virtual reference lines L are not parallel to each other may be employed. In this case, all the virtual reference lines L are not parallel to each other, or among the plurality of virtual reference lines L, some virtual reference lines L are parallel and other virtual reference lines L are not parallel. You may employ | adopt the structure which is. Furthermore, although all the virtual reference lines L are parallel to each other, a configuration in which the virtual reference lines L are set in a direction intersecting with the extending direction of the data lines 6a in the pixel region 10b may be employed.

[Other Embodiments of Embodiment 3 and Embodiment 4]
In the third and fourth embodiments, the driving IC mounted on the element substrate 10 is arranged as the data line driving circuit 101 in the region where the signal output circuit for the data line 6a is arranged. However, the data line driving circuit 101 may be configured by using a thin film transistor formed on the element substrate 10 by SOG technology. In this case, the number of parts is reduced, the cost can be reduced, and the electro-optical device can be further improved in industrial utility value. In addition, when the data line driving circuits 104a and 104b are not formed on the element substrate 10 and signal output to the data line 6a is performed from the outside through the flexible substrate connected to the element substrate 10, the connection area of the flexible substrate (For example, the pad 102) functions as a region where a signal output circuit for the data line 6a is disposed. The present invention may be applied to an electro-optical device having such a configuration.

  In the third and fourth embodiments, the polysilicon film is used as the semiconductor layer 1a of the thin film transistor 30a. However, the electro-optical device using a single crystal silicon layer or an amorphous silicon film as the semiconductor layer 1a of the thin film transistor 30a. The present invention may be applied to 100. Further, in the above embodiment, the data line 6a is the second signal line and the scanning line 3a is the first signal line. However, the scanning line 3a is the second signal line, and the data line 6a is the first signal line. The present invention may be applied to the electro-optical device.

  In the third and fourth embodiments, the output line 46 of each data line 6a is drawn from the pixel region 10b and then routed to the data line driving circuit 101 along the corresponding virtual reference point P. At this time, in each region sandwiched by the virtual reference line L, the output line 46 of the data line 6a is drawn linearly in the region sandwiched by the virtual reference line L and bent at the virtual reference line L. However, although it is routed to the data line driving circuit 101, the present invention is not limited to this, and in the region sandwiched between the virtual reference lines L, it is routed along the outer peripheral edge of the pixel region, and the virtual reference line A configuration in which the output lines 46 of all the data lines 6a are routed at substantially equal intervals in any region sandwiched between the virtual reference lines L by gently bending the lines L.

[Embodiment 5]
Hereinafter, an example in which the present invention is applied to an organic EL device will be described. In the following description, corresponding parts are denoted by the same reference numerals as much as possible so that the correspondence with the first, second, third, and fourth embodiments can be easily understood.

(overall structure)
FIG. 11 is a block diagram showing an electrical configuration of an electro-optical device (organic EL device) according to Embodiment 5 of the present invention. 12A and 12B are a plan view of two adjacent pixels and a cross-sectional view of one pixel of the electro-optical device 100 according to Embodiment 5 of the present invention. 12B is a cross-sectional view taken along line BB ′ of FIG. 12A. In FIG. 12A, the pixel electrode 9a is indicated by a long dotted line, and is formed simultaneously with the data line 6a. The thin film is indicated by a one-dot chain line, the scanning line 3a is indicated by a solid line, and the semiconductor layer is indicated by a short dotted line.

  An electro-optical device 100 shown in FIG. 11 is an organic EL device, and on the element substrate 10, a plurality of scanning lines 3a (first signal lines) and a plurality of data extending in a direction intersecting the scanning lines 3a. A line 6a (second signal line) and a plurality of power supply lines 3e extending in parallel with the scanning line 3a are provided. In the element substrate 10, a plurality of pixels 100a are arranged in a matrix in the pixel region 10b. A data line driving circuit 101 (signal output circuit) is connected to the data line 6a, and scanning line driving circuits 104a and 104b (signal output circuit) are connected to the scanning line 3a. Each pixel region 10b holds a switching thin film transistor 30b to which a scanning signal is supplied to the gate electrode via the scanning line 3a, and a pixel signal supplied from the data line 6a via the switching thin film transistor 30b. The storage capacitor 70 to be driven, the driving thin film transistor 30c to which the pixel signal held by the storage capacitor 70 is supplied to the gate electrode, and the power supply line 3e when electrically connected to the power supply line 3e through the thin film transistor 30c. A pixel electrode 9a (anode layer) into which a drive current flows and an organic EL element 80 in which an organic functional layer is sandwiched between the pixel electrode 9a and the cathode layer are configured.

  According to this configuration, when the scanning line 3a is driven and the switching thin film transistor 30b is turned on, the potential of the data line 6a at that time is held in the holding capacitor 70, and according to the charge held in the holding capacitor 70, The on / off state of the driving thin film transistor 30c is determined. Then, a current flows from the power supply line 3e to the pixel electrode 9a through the channel of the driving thin film transistor 30c, and a current flows to the counter electrode layer through the organic functional layer. As a result, the organic EL element 80 emits light according to the amount of current flowing therethrough.

  In the configuration shown in FIG. 11, the power supply line 3e is in parallel with the scanning line 3a, but a configuration in which the power supply line 3e is in parallel with the data line 6a may be adopted. In the configuration shown in FIG. 11, the storage capacitor 70 is configured using the power supply line 3e. However, a storage capacitor may be formed separately from the power supply line 3e. Good.

  As shown in FIGS. 12A and 12B, a plurality of transparent pixel electrodes 9a (regions surrounded by long dotted lines) are formed in a matrix on the element substrate 10 for each pixel 100a. Data lines 6a (regions indicated by alternate long and short dash lines) and scanning lines 3a (regions indicated by solid lines) are formed along the vertical and horizontal boundary regions 9a. In the element substrate 10, a power supply line 3e is formed in parallel with the scanning line 3a.

  The base of the element substrate 10 shown in FIG. 12B is a support substrate 10d such as a quartz substrate or a heat-resistant glass substrate. In the element substrate 10, a base insulating layer 12 made of a silicon oxide film or the like is formed on the surface of the support substrate 10d, and a thin film transistor 30c is formed in a region corresponding to the pixel electrode 9a on the surface side. In the thin film transistor 30c, a channel region 1g, a source region 1h, and a drain region 1i are formed with respect to the island-shaped semiconductor layer 1a. A gate insulating layer 2 is formed on the surface side of the semiconductor layer 1a, and a gate electrode 3f is formed on the surface of the gate insulating layer 2. The gate electrode 3f is electrically connected to the drain of the thin film transistor 30b. Note that the basic configuration of the thin film transistor 30b is the same as that of the thin film transistor 30c, and thus description thereof is omitted.

  On the upper layer side of the thin film transistor 30c, an interlayer insulating layer 71 made of a silicon oxide film or a silicon nitride film, an interlayer insulating layer 72 made of a silicon oxide film or a silicon nitride film, and a thick photosensitive film having a thickness of 1.5 μm to 2.0 μm. An interlayer insulating film 73 (flattening film) made of a conductive resin is formed. A source electrode 6g and a drain electrode 6h are formed on the surface of the interlayer insulating layer 71 (between the interlayer insulating films 71 and 72). The source electrode 6g is connected to the source region via a contact hole 71g formed in the interlayer insulating layer 71. It is electrically connected to 1h. The drain electrode 6h is electrically connected to the drain region 1i through a contact hole 71h formed in the interlayer insulating layer 71. A pixel electrode 9 a made of an ITO film is formed on the surface of the interlayer insulating layer 73. The pixel electrode 9a is electrically connected to the drain electrode 6h through a contact hole 73g formed in the interlayer insulating layers 72 and 73.

  In addition, on the upper layer of the pixel electrode 9a, a partition layer 5a made of a silicon oxide film or the like having an opening for defining a light emitting region, and a thick partition layer 5b made of a photosensitive resin or the like are formed. In the region surrounded by the partition wall layer 5a and the partition wall layer 5b, the hole injection layer 81 made of 3,4-polyethylenediosithiophene / polystyrene sulfonic acid (PEDOT / PSS) or the like is formed on the upper layer of the pixel electrode 9a, and An organic functional layer composed of the light emitting layer 82 is formed, and a cathode layer 85 is formed on the light emitting layer 82. In this way, the organic EL element 80 is configured by the pixel electrode 9a, the hole injection layer 81, the light emitting layer 82, and the cathode layer 85. The light-emitting layer 82 is made of, for example, a polyfluorene derivative, a polyphenylene derivative, polyvinylcarbazole, a polythiophene derivative, or a polymer material thereof. It is composed of a material doped with anthracene, tetraphenylbutadiene, Nile red, coumarin 6, quinacridone and the like. Further, as the light-emitting layer 82, a π-conjugated polymer material in which double-bonded π electrons are non-polarized on the polymer chain is also a conductive polymer, so that it is excellent in light-emitting performance. It is done. In particular, a compound having a fluorene skeleton in the molecule, that is, a polyfluorene compound is more preferably used. In addition to such materials, it is also possible to use a composition comprising a conjugated polymer organic compound precursor and at least one fluorescent dye for changing light emission characteristics. In this embodiment, the organic functional layer is formed by a coating method such as an inkjet method. As a coating method, a flexographic printing method, a spin coating method, a slit coating method, a die coating method, or the like may be employed. In addition, the organic functional layer may be formed by a vapor deposition method or the like. Further, an electron injection layer made of LiF or the like may be formed between the light emitting layer 82 and the cathode layer 85.

  In the case of a top emission type organic EL device, light is extracted from the side where the organic EL element 80 is formed as viewed from the support substrate 10d. Therefore, the cathode layer 85 is attached with a thin aluminum film or a thin film such as magnesium or lithium. As a support substrate 10d, an opaque substrate as well as a transparent substrate such as glass can be used. Examples of the opaque substrate include ceramics such as alumina, a metal plate such as stainless steel that has been subjected to an insulation treatment such as surface oxidation, and a resin substrate. On the other hand, in the case of a bottom emission type organic EL device, since light is extracted from the support substrate 10d side, a transparent substrate such as glass is used as the support substrate 10d.

  Also in the electro-optical device 100 configured as described above, in the same manner as in the first and second embodiments, when the pixel region 10b faces the scanning line driving circuits 104a and 104b and is a curved portion, FIG. The scanning line driving circuits 104a and 104b may be configured by adopting the configuration described with reference to FIGS.

[Another embodiment]
FIGS. 13 and 14 are explanatory views showing the planar shapes of the pixel region 10b and the element substrate 10 of another electro-optical device to which the present invention is applied, respectively.

  In the above-described embodiment, the planar shape of the element substrate 10 has an irregular shape that combines an arc and a straight line, and the planar shape of the pixel region 10b is circular. The present invention may be applied to the case where the region 10b includes a deformed outer peripheral edge portion including a curved portion or a bent portion in a portion facing the scanning line driving circuits 104a and 104b. That is, the pixel region 10b has a circular shape, a triangular shape, a polygonal shape that is a pentagon or more, or an irregular shape that is a combination of a curved line and a straight line, and includes a curved portion or a bent portion at a portion facing the scanning line driving circuits 104a and 104b. The present invention may be applied to the case where a deformed outer peripheral portion is provided. In addition, the present invention may be applied to the case where the element substrate 10 has a circular shape, a triangular shape, a polygonal shape that is a pentagon or more, or an irregular shape that is a combination of a curve and a straight line.

  For example, as shown in FIG. 13A, an ellipse-shaped electro-optical device 100 in which the planar shapes of the element substrate 10 and the pixel region 10b both extend in the same direction, as shown in FIG. The electro-optical device 100 in which the planar shape of the substrate 10 is an octagon and the planar shape of the pixel region 10b is a perfect circle, as shown in FIG. 13C, the planar shape of the element substrate 10 is a horizontally long octagon, The present invention may be applied to the electro-optical device 100 having the oval shape in which the planar shape of the region 10b is horizontally long.

  Further, as shown in FIG. 14A, the electro-optical device 100 in which the element substrate 10 has an irregular shape combining a semicircle and a straight line and the pixel region 10b is an octagon, as shown in FIG. 14B. The element substrate 10 has a horizontally long oval shape and the pixel area 10b has a horizontally long octagonal electro-optical device 100. As shown in FIG. 14C, both the element substrate 10 and the pixel area 10b have an octagonal shape. The present invention may be applied to the electro-optical device 100 or the like.

  Furthermore, if both the element substrate 10 and the pixel region 10b are configured to have a bent portion facing a portion facing the scanning line driving circuits 104a and 104b, the element substrate 10 and / or the pixel region 10b are rectangular. The present invention may be applied to.

[Other embodiments]
In the above embodiment, the driving IC mounted on the element substrate 10 is arranged as the data line driving circuit 101 arranged in the signal output region for the data line 6a. However, the present invention is not limited to this, and the data line driving circuit is not limited thereto. The present invention may be applied to an electro-optical device in which 101 is configured using a thin film transistor formed on the element substrate 10. Further, the present invention is applied to an electro-optical device in which the data line driving circuit 101 is not configured on the element substrate 10 and signal output to the data line 6 a is performed from the outside via a flexible substrate connected to the element substrate 10. May be. In this case, a region (connection region) where a connection terminal (signal output circuit) with a flexible substrate or the like is disposed functions as a region where a signal output circuit for the data line 6a is disposed. The present invention may be applied to an electro-optical device having such a configuration.

  In the above embodiment, the scanning line driving circuits 104a and 104b are configured on both sides of the pixel region 10b. However, the scanning line driving circuits 104a and 104b are configured only on one side of the pixel region 10b. The present invention may be applied to an electro-optical device.

  Further, in the above embodiment, the present invention is applied to configure the scanning line driving circuits 104 a and 104 b, but the present invention may be applied to configure the data line driving circuit 101. That is, in the above embodiment, the scanning line 3a is the first signal line and the data line 6a is the second signal line. However, the scanning line 3a is the second signal line, and the data line 6a is the first signal line. The present invention may be applied to the electro-optical device.

  In the first embodiment, a polysilicon film is used as the semiconductor layer 1a of the thin film transistor 30a. However, in the electro-optical device 100 in which a single crystal silicon layer or an amorphous silicon film is used as the semiconductor layer 1a of the thin film transistor 30a. The present invention may be applied.

1 is a block diagram showing an electrical configuration of an electro-optical device (liquid crystal device) according to Embodiment 1 of the invention. (A), (b) is the top view of the electro-optical apparatus which concerns on Embodiment 1 of this invention, respectively, and the top view of an element substrate. (A), (b) is the top view of another electro-optical device based on Embodiment 1 of this invention, respectively, and the top view of an element substrate. FIGS. 4A and 4B are a plan view of two adjacent pixels and a cross-sectional view of one pixel in the element substrate used in the electro-optical device according to Embodiment 1 of the present invention. FIGS. 7A and 7B are a plan view schematically showing a state in which circuit blocks are arranged in an outer region of a pixel region in the element substrate of the electro-optical device according to the first embodiment of the present invention, and the circuit block 1; Explanatory drawing of one. FIG. 3 is a plan view schematically showing an enlarged connection portion between a circuit block and a scanning line arranged in an outer region of a pixel region in the element substrate of the electro-optical device according to the first embodiment of the invention. FIG. 6 is a plan view schematically showing a state in which circuit blocks are arranged in an outer region of a pixel region in an element substrate of an electro-optical device according to a second embodiment of the present invention. FIG. 10 is an enlarged plan view schematically showing a state in which a data line is routed to a data line driving circuit on an element substrate in an electro-optical device according to a third embodiment of the invention. FIG. 10 is an explanatory diagram of virtual reference lines and virtual reference points set for routing data lines to a data line driving circuit in the electro-optical device according to the third embodiment of the present invention. FIG. 10 is an explanatory diagram of virtual reference lines and virtual reference points set for routing data lines to a data line driving circuit in the electro-optical device according to the fourth embodiment of the present invention. FIG. 9 is a block diagram showing an electrical configuration of an electro-optical device (organic EL device) according to a fifth embodiment of the invention. (A), (b) is the top view for two adjacent pixels of the electro-optical device which concerns on Embodiment 5 of this invention, respectively, and sectional drawing for one pixel. FIG. 10 is an explanatory diagram illustrating a pixel region and a planar shape of an element substrate of another electro-optical device to which the present invention is applied. FIG. 9 is an explanatory diagram illustrating a planar shape of a pixel region and an element substrate of still another electro-optical device to which the present invention is applied. Explanatory drawing which shows the planar shape of the pixel region and element substrate which were used for the electro-optical apparatus which concerns on a reference example. (A), (b) is an explanatory view showing the rising speed of the voltage when there is a large difference in the interval between the adjacent data lines, and the rising speed of the voltage when there is no large difference in the interval between the adjacent data lines FIG.

Explanation of symbols

  3a ... scanning line (first signal line), 4 ... unit circuit block, 4a, 4b, 4c, 4d, 4x, 4y ... circuit block, 6a ... data line (second signal line), 9a ... pixel electrode, 10 ... Element substrate, 10b... Pixel region, 10x... Outside region of pixel region, 30a, 30b, 30c... Thin film transistor (pixel transistor), 40... Unit circuit, 44. Electro-optical device, 100a, pixel, 101, data line driving circuit, 104a, 104b, scanning line driving circuit, L, virtual reference line, P, virtual connection point, Q, virtual connection wiring.

Claims (10)

On the element substrate, a first signal line and a second signal line extending in a direction intersecting each other, a pixel region in which a pixel electrode is disposed corresponding to the intersection of the first signal line and the second signal line, In an electro-optical device having a signal output circuit that is disposed outside the pixel region and outputs a drive signal to a second signal line, and a connection wiring that connects the signal output circuit and the second signal line,
The outer peripheral edge of the pixel region includes a curved portion or a bent portion in a portion facing the signal output circuit,
The length dimension of the region in which the signal output circuit is arranged in the direction orthogonal to the second signal line is shorter than the width dimension of the pixel region in the direction orthogonal to the extending direction of the second signal line,
A plurality of virtual reference lines set across the area in a region where the connection wiring is routed, a plurality of virtual reference points set at predetermined intervals on the virtual reference line, and adjacent virtual reference lines If the virtual connection wiring that connects the virtual reference points is provided,
The electro-optical device, wherein the connection wiring passes through the virtual connection wiring or along the virtual connection wiring.   2. The electro-optical device according to claim 1, wherein the predetermined interval is an equal interval, and the plurality of virtual reference lines are set at four or more locations in a region where the connection wiring is provided. .   The electro-optical device according to claim 1, wherein the plurality of virtual reference lines are set in parallel to each other. In the element substrate, a region in which a second signal output circuit that outputs a drive signal to the first signal line is disposed outside the pixel region is formed.
4. The region where the connection wiring is wired is at least partially located between the pixel region and a region where the second signal output circuit is disposed. The electro-optical device according to any one of the above.   5. The electro-optical device according to claim 1, wherein the second signal line is a data line, and the signal output circuit is a data line driving circuit. 6.   5. The electro-optical device according to claim 1, wherein the second signal line is a scanning line, and the signal output circuit is a scanning line driving circuit. 6.   The electro-optical device according to claim 1, wherein the planar shape of the pixel region is a circle or a shape formed by combining a curve and a straight line.   8. The planar shape of the element substrate is a circle, a triangle, a pentagon or more polygon, or a shape formed by combining a curve and a straight line. Electro-optic device.   9. The electro-optical device according to claim 8, wherein the element substrate holds a liquid crystal layer between the element substrate and a counter substrate disposed to face the element substrate.   The electro-optical device according to claim 8, wherein the element substrate includes an organic electroluminescence element in the pixel region.

Images