JP2009080843A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To constitute a capacitor with a chip type ceramic capacitor, and to solder and connect the capacitor on a wiring board with an IC chip mounted thereon in an IC card having a parallel resonant circuit of the capacitor and a coil for an antenna as a non-contact interface. <P>SOLUTION: The wiring board 5 is provided with an antenna connection terminal connected to the capacitor C. When the wiring board 5 is embedded in a card main body constituting the IC card, the antenna connection terminal of the wiring board 5 is connected to the coil formed on the card main body. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effective when applied to an IC (Integrated Circuit) card.

An IC card is a card-type semiconductor device in which an IC chip is embedded in a flat rectangular thin plate (card body). When classified by communication method, for example, a contact type, a non-contact type, and a contact / non-contact type There is. The contact type IC card is an IC card capable of supplying power and exchanging signals through connection terminals exposed on the surface of the card body. The IC chip of the contact IC card is built in the card body in a state of being mounted on the back side of the wiring board having the connection terminals. The non-contact type IC card is an IC card capable of supplying electromagnetic waves (wireless) and exchanging signals through an antenna built in the card body. The contact / non-contact type IC card is a combination of the contact type and the non-contact type, and each of the contact and non-contact type IC chips is built in one card body or one IC chip. Some have both contact and non-contact interfaces. As an example of the contact / non-contact type IC card, on the component mounting surface of the substrate provided on the back surface of the connection terminal, an antenna of the size of the connection terminal, an IC chip, and a capacitor connected in parallel to the antenna are provided. An IC card structure having a mounted configuration is disclosed (for example, see Patent Document 1). As another example, a sealing resin for sealing the IC chip mounted on the component mounting surface of the IC module substrate has a partial opening that exposes the antenna connection terminal formed on the component mounting surface. An IC card structure having a configuration in which an antenna transmission / reception coil is connected to an exposed portion of the antenna connection terminal is disclosed (for example, see Patent Document 2).
JP 2002-207982 A JP 2003-67695 A

  However, in a card-type semiconductor device such as an IC card, one of the important issues is how to improve the communication characteristics.

  An object of the present invention is to provide a technique capable of improving the communication characteristics of a card type semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the present invention relates to a card body comprising a semiconductor chip on which an integrated circuit is formed, a wiring board on which the semiconductor chip is mounted, and a non-contact type interface electrically connected to the semiconductor chip through the wiring of the wiring board. The contactless interface includes a coil having a function as an antenna and a capacitor that is connected in parallel to the coil to form a resonance circuit, and the capacitor is connected to the wiring board by soldering It has the structure which is made.

  The effects obtained by typical ones of the embodiments disclosed by the present application will be briefly described as follows.

  That is, the card body includes a semiconductor chip in which an integrated circuit is formed, a wiring board on which the semiconductor chip is mounted, and a non-contact type interface electrically connected to the semiconductor chip through wiring of the wiring board, The non-contact type interface includes a coil having a function as an antenna and a capacitor connected in parallel to the coil to form a resonance circuit, and the capacitor is connected to the wiring board by soldering. By having it, it becomes possible to improve the communication characteristics of the card-type semiconductor device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.

(Embodiment 1)
The semiconductor device of the first embodiment includes, for example, a credit card, a cash card, an ETC (Electronic Toll Collection system) system card, a commuter pass, a public phone card, a mobile phone card or an authentication card, etc. IC (Integrated Circuit) cards are being used in various fields such as distribution and authentication.

  FIG. 1 shows an example of an overall plan view of the IC card 1 according to the first embodiment. 2 shows an enlarged cross-sectional view of a main part taken along line X1-X1 in FIG. 3 is an overall plan view showing the IC module 2 removed from the IC card 1 shown in FIG. 1, and FIG. 4 is an enlarged cross-sectional view taken along line X1-X1 in FIG.

  The IC card 1 according to the first embodiment is, for example, a type in which a contact type and a non-contact type are integrated, and the outer shape thereof is a thin plate having a rectangular plane slightly smaller than a business card size (91 mm × 55 mm). ing. The external dimensions of the IC card 1 are, for example, vertical (longitudinal dimension) × horizontal (short dimension) 85.6 mm × 54 mm and thickness 0.76 mm.

  The IC module 2 of the IC card 1 is a main circuit part having an IC chip (semiconductor chip) 3, with a plurality of module terminals 4 of the IC module 2 exposed to the outside, and the IC chip 3 and the like. Are firmly fixed to the card body 7 in such a state that the sealing portion 6a for sealing the wiring board 5 and the IC chip 3 and the like are fitted in the stepped recess 7a of the card body 7.

  Two antenna connection terminals 8 a are formed on the mounting surface of the wiring substrate 5 on which the IC chip 3 is mounted. The antenna connection terminal 8a is joined and electrically connected to the connection terminals Lt at both ends of the antenna coil L via a conductive adhesive 10 such as a paste containing silver (Ag). The antenna coil L is formed in a loop shape along the outer periphery of the card body 7 (see the broken line in FIG. 3). By providing the coil L in the card body 7 in this way, a large loop of the coil L can be taken, so that the gain of the antenna can be improved, and the IC card 1 and an external transmission / reception unit (reader / writer). The range (directivity) of wireless signal exchange with can be expanded. Therefore, wireless signals can be exchanged even if the IC card 1 is separated from the external transmission / reception unit to some extent. Most of the coil L is embedded in the card body 7, but one surface of the connection terminal Lt at both ends of the coil L is exposed to the stepped portion of the recess 7 a of the card body 7 for connection with the wiring board 5. Has been.

  The card body 7 is made of a plastic such as polyvinyl chloride resin, polyolefin (polypropylene, etc.), polyethylene terephthalate (PET), polyethylene terephthalate glycol (PET-G), or the like. By using such a relatively inexpensive plastic, the cost of the IC card 1 can be reduced. In addition, since no harmful substances are generated even if polypropylene, PET, or PET-G is burned, the environmental load can be reduced by using these as materials for the card body 7. Furthermore, since PET-G is amorphous and softer than PET, processing such as embossing can be facilitated by using PET-G as a material for the card body 2.

  Next, the structure of the IC module 2 will be described in detail with reference to FIGS.

  FIG. 5 shows an example of the contact surface (second surface) of the wiring board 5 of the IC module 2. The board body of the wiring board 5 is made of, for example, a glass epoxy resin, and, for example, eight module terminals 4 (4a to 4h) are arranged on the contact surface thereof in close proximity to each other. The module terminal 4 is formed by applying gold (Au) plating or the like to the exposed surface of a metal foil such as copper (Cu), and the connection terminal of an external transmission / reception device (reader / writer) is directly connected. It is a contact-type interface portion that electrically connects the transceiver device and the circuit in the IC module 2. Although not particularly limited, allocation of signals and the like of the module terminals 4a to 4h is as follows, for example. The module terminal 4a on the upper left side in FIG. 5 is, for example, a power supply voltage supply terminal on the high potential side. The lower module terminal 4b is, for example, a reset signal terminal. The lower module terminal 4c is a clock signal terminal. The relatively large module terminal 4e at the center is a terminal for supplying a low-potential-side power supply voltage (for example, ground voltage) lower than the high-potential-side power supply voltage, for example. The module terminal 4g is, for example, a data input / output signal terminal. The module terminals 4d, 4f, and 4h other than these are non-connect terminals that can be used in the future but are not assigned at present.

  FIG. 6 shows an example of the mold surface (first surface) of the wiring board 5 of the IC module 2. This mold surface is the surface opposite to the contact surface. The sealing portion 6 a is provided at the center of the mold surface of the wiring substrate 5. The sealing portion 6a is made of, for example, an epoxy resin, and is formed in, for example, a planar rectangular shape. In FIG. 6, the antenna connection terminal 8a and the wirings 8b and 8c are disposed on the left and right sides of the sealing portion 6a. The distance from each antenna connection terminal 8a to the side surface (outer periphery) of the sealing portion 6a adjacent to the antenna connection terminal 8a is designed to be, for example, 0.1 mm or longer. Thereby, even if a resin flash is generated on the outer peripheral portion of the sealing portion 6a by the forming process (molding process) of the sealing portion 6a, the resin flash can be prevented from covering the antenna connection terminal 8a. Therefore, contact failure between the antenna connection terminal 8a and the antenna coil L can be reduced or prevented, and the yield of the IC card 1 can be improved. Moreover, since the increase in contact resistance between the antenna connection terminal 8a and the antenna coil L can be suppressed or prevented, the communication characteristics of the IC card 1 during non-contact communication can be improved. The antenna connection terminal 8a and the wirings 8b and 8c are formed by integrally patterning gold on the exposed surface of a metal foil such as copper. The wiring 8c is a part of the lead-out wiring for energization when the exposed surfaces of the antenna connection terminal 8a and the wiring 8b are plated with gold by electrolytic plating.

  FIG. 7 shows an example of the mold surface from which the sealing portion 6a of FIG. 6 is removed. FIG. 8 is a cross-sectional view taken along the line Y1-Y1 in FIGS. Further, FIG. 9 shows a cross-sectional view taken along line X2-X2 of FIG. In FIG. 7, the sealing portion 6a is indicated by a broken line. The broken line area is sealed with a sealing portion 6a.

  The IC chip 3 is mounted at the center of the mold surface of the wiring substrate 5 with its main surface (device forming surface) facing upward. The IC chip 3 includes a semiconductor substrate made of, for example, silicon (Si) single crystal, and has, for example, a central processing unit, ROM (Read Only Memory), RAM (Random Access Memory), and EEPROM on its main surface. An integrated circuit such as (Electrically Erasable Programmable ROM) and other arithmetic circuits, and a plurality of bonding pads 12 for drawing out electrodes of the integrated circuit are formed. In the ROM, for example, an execution program, an encryption algorithm, and the like are stored. The RAM has a function as a memory for data processing, for example. The EEPROM has a function as a memory for storing data.

  7, a plurality of bonding holes 13 penetrating the upper and lower surfaces of the wiring substrate 5 are arranged at predetermined intervals along the vertical direction in FIG. A part of the back surface of the module terminal 4 is exposed from each bonding hole 13, and the exposed surface is plated with gold. One end of a bonding wire 14 made of, for example, a gold (Au) fine wire is bonded to the module terminal 4 exposed from the bonding hole 13. The other end of the bonding wire 14 is bonded to the bonding pad 12 of the IC chip 3. Thereby, the predetermined bonding pad 12 of the IC chip 3 is electrically connected to the module terminal 4.

  In FIG. 7, the antenna connection terminal 8 a is disposed further outside the row of bonding holes 13. Each wiring 8b formed integrally with each antenna connection terminal 8a extends across the row of the bonding holes 13 in the region of the sealing portion 6a and extends toward the center of the wiring substrate 5. . A wide portion 8d is formed integrally with the wiring 8b at a position in the middle of the extension of each wiring 8b (position of the row of the bonding holes 13). One end of the bonding wire 14 is joined to the wide portion 8d. The other end of the bonding wire 14 is bonded to the bonding pad 12 of the IC chip 3. Thereby, the predetermined bonding pad 12 of the IC chip 3 is electrically connected to the wiring 8b.

  The ends of the wirings 8b extend to positions close to each other and are terminated. A wide connection terminal 8e is formed integrally with the wiring 8b at the end of each wiring 8b. The left and right wirings 8b and the connection terminals 8e are formed symmetrically. A capacitor C is electrically connected between the connection terminals 8e so as to bridge the connection terminals 8e. FIG. 10 shows the connection relationship between the capacitor C and the coil L for the antenna. The capacitor C is connected to the coil L in parallel. The coil L and the capacitor C form a parallel resonance circuit. This parallel resonant circuit is a circuit part that forms a non-contact type interface of the IC card 1, and the communication characteristics of the IC card 1 can be improved by providing this resonant circuit. For example, the distance in which the IC card 1 can perform wireless communication can be increased, and the reliability of the wireless communication of the IC card 1 can be improved. The resonance frequency (that is, communication frequency) of this resonance circuit is set to 13.56 MHz, for example. The communication distance is, for example, about 0 to 70 cm.

  FIG. 11 shows an example of an enlarged cross-sectional view of the main part of the capacitor C (cross-sectional view taken along line X3-X3 in FIG. 7). As the capacitor C, for example, a chip type multilayer ceramic capacitor is used. That is, the capacitor C includes a plurality of layers of electrodes 17a electrically connected to one connection terminal 16a of the capacitor C, and a plurality of layers of electrodes 17b electrically connected to the other connection terminal 16b of the capacitor C. However, the ceramic dielectric 18 is interposed between the electrodes 17a and 17b, and the capacitor C is alternately stacked in the thickness direction. However, in the IC card 1, since the height of the sealing portion 6a is limited, a relatively thin chip type multilayer ceramic capacitor is used instead of a general-purpose chip type multilayer ceramic capacitor. The thickness of the capacitor C is, for example, about 250 μm.

  Thus, by using the capacitor C as a ceramic capacitor, for example, the following effects can be obtained.

  First, it is possible to improve the accuracy of the resonance frequency of the resonance circuit. That is, since the resonance frequency f of the resonance circuit formed by the capacitor C and the coil L can be expressed by f = 1 / (2π (LC) 1/2), the capacitance value of the capacitor C is accurate. Is preferred. The capacitor C can be formed of a sheet-like capacitor, but in this case, the capacitance value varies and the peak position of the resonance frequency may shift. On the other hand, ceramic capacitors have low stray capacitance, etc. and high capacitance value accuracy, and because they are composed of ceramic and metal, they are extremely stable with little deterioration under high and low temperature environments. By forming the capacitor C with a ceramic capacitor, circuit design close to the theoretical value (resonance circuit design) becomes possible.

  Second, the manufacturing process of the IC card 1 can be facilitated. That is, when the capacitor C is formed of a sheet-like capacitor, there are cases where the capacitance value varies greatly and trimming is required. On the other hand, a ceramic capacitor has a high capacitance value accuracy and does not require trimming. Therefore, by forming the capacitor C with a ceramic capacitor, the IC card 1 can be easily manufactured. The time can be reduced and the cost can be reduced.

  In the first embodiment, the connection terminals 16 a and 16 b of the capacitor C are joined and electrically connected to the connection terminal 8 e of the wiring board 5 by the solder 20. In a non-contact type IC card, a wiring board is basically unnecessary, and when a capacitor for a resonance circuit is provided, it is directly attached to a card body having low heat resistance (directly connected to an antenna coil provided in the card body). Therefore, a material that can be connected at a relatively low temperature, such as a conductive resin paste, is generally used as a connection material between the capacitor for the resonance circuit and the coil for the antenna because heat treatment at a very high temperature cannot be performed. Yes. However, when the conductive resin paste is used, the contact resistance between the capacitor for the resonance circuit and the coil for the antenna increases, resulting in loss in the resonance circuit. As a result, the Q (Quality factor) increases the resonance sharpness of the resonance circuit. The present inventor has found for the first time that there is a problem that the value that represents the amount that gives the bandwidth around the resonance frequency) decreases, that is, the sensitivity of the antenna decreases and the communication characteristics of the IC card deteriorate. It was. On the other hand, in the first embodiment, the capacitor C is mounted on the mold surface of the wiring board 5 made of glass epoxy resin having a relatively high heat resistance, and therefore the capacitor C is connected by the solder 20 accompanied by high temperature heat treatment. be able to. When the capacitor C is connected to the coil L with the solder 20, the resistance between the capacitor C and the coil L can be reduced as compared with the conductive resin paste, so that the loss of the resonance circuit can be reduced. As a result, the Q value of the resonance circuit can be improved and the sensitivity of the antenna can be improved. As described above, according to the first embodiment, by using a ceramic capacitor as the capacitor C and connecting the capacitor C with the solder 20, the communication characteristics of the IC card 1 can be further improved. For this reason, for example, the distance in which the IC card 1 can perform wireless communication can be increased, and the reliability of the wireless communication of the IC card 1 can be further improved.

  As the material of the solder 20, a material having a melting point higher than a temperature (for example, 180 degrees) at the time of forming the sealing portion 6a (molding process) is selected. This is because in the first embodiment, the capacitor C is sealed by the sealing portion 6a, so that the solder 20 does not melt during the molding process. Specific examples of the material of the solder 20 include lead (Pb) -tin (Sn) solder, tin-silver (Ag), tin-silver-copper, and tin-silver-copper-bismuth (Bi). A so-called lead-free solder such as tin-bismuth, tin-copper, or tin-zinc (Zn) can be used. By using the lead-free solder, the environmental load can be reduced.

  In the first embodiment, the capacitor C as described above is sealed by the sealing portion 6a in the same manner as the IC chip 3, the bonding wire 14, and the like. As described above, in the first embodiment, since the capacitor C is sealed with the sealing portion 6a, the capacitor C and its solder connection portion can be protected from the outside, and thus, for example, weather resistance and moisture resistance are improved. In addition, it is possible to improve the resistance to mechanical fatigue of the solder connection portion caused by the bending of the IC card 1 and the like, so that peeling of the capacitor C and the like can be suppressed or prevented. Therefore, the life of the IC card 1 can be improved.

  Next, FIG. 12 shows an overall plan view of the mold surface shown by removing the IC chip 3 and the capacitor C from FIG. FIG. 13 shows the arrangement of the antenna connection terminals 8a of the IC module 2 according to the first embodiment and the connection relationship between the antenna connection terminals 8a and the coil L. FIG. 14 shows another arrangement of the antenna connection terminals 8a examined by the present inventors for comparison.

  In the first embodiment, as shown in FIGS. 12 and 13, the two antenna connection terminals 8 a are not arranged on the same side of the IC chip 3, but are arranged on different sides of the IC chip 3. ing. Here, the two antenna connection terminals 8a are arranged on both left and right sides of the IC chip 3 so as to be symmetrical with respect to the IC chip 3, that is, in an opposite relationship to each other. . As shown in FIG. 14, if two antenna connection terminals 8a are arranged on the same side of the IC chip 3, they extend between the two antenna connection terminals 8a or from the two antenna connection terminals 8a to the IC chip 3 side. As a result of the formation of the stray capacitance Cs between the adjacent wires 8b or between the wires forming the antenna coil L, the capacitance value of the capacitor forming the resonance circuit differs from the design value. On the other hand, in the first embodiment, the stray capacitance Cs as described above is formed by arranging the antenna connection terminals 8a on different sides of the IC chip 3 and separating them from each other as described above. Therefore, the capacitance value of the capacitor C of the resonance circuit can be made close to the design value. Further, since the arrangement margins of the antenna connection terminal 8a for connecting the coil L, the connection terminal 8e for mounting the capacitor C, and the bonding hole 13 can be increased, the arrangement design of each can be facilitated.

  Next, an example of a method for manufacturing the IC card 1 according to the first embodiment will be described with reference to FIGS.

  First, the capacitor C, the IC chip 3 and the wiring board base are prepared (steps CP, CHP, MCBP in FIG. 15). The capacitor C and the IC chip 3 can be mass-produced by a known manufacturing process. The wiring board base is the base of the wiring board 5. FIG. 16 shows an example of a plan view of the main part of the wiring board base 5M. The wiring board base 5M is made of, for example, a thin glass epoxy resin having a tape shape. In the vicinity of both ends in the short direction of the wiring board base 5M, a plurality of sprocket holes 22 are regularly arranged along the longitudinal direction of the wiring board base 5M. The sprocket hole 22 is a feed hole for feeding the tape-shaped wiring board base 5M to the tape. The sprocket roller rotates in a state in which the sprocket hole of the sprocket roller on the assembly device side is fitted in the sprocket hole 22, so that the feeding operation of the tape-shaped wiring board base 5M is performed with good alignment. A plurality of unit regions UR are arranged in two rows along the longitudinal direction in the center of the wiring board base 5M. Each unit region UR is a region for obtaining the wiring substrate 5 of one IC module 2.

  FIG. 17 shows an example of an enlarged plan view of the main part of the contact surface of the wiring board base 5M, and FIG. 18 shows an example of an enlarged plan view of the main part of the mold surface of the wiring board base 5M. Here, four unit regions UR are illustrated. As shown in FIG. 17, the module terminal 4 has already been formed in each unit region UR on the contact surface of the wiring board base 5M. The wiring 23 is integrally connected to the module terminal 4 at this stage. The wiring 23 has a function as a lead-out wiring for energization during the plating process. The module terminal 4 and the wiring 23 are patterned simultaneously. As shown in FIG. 18, the antenna connection terminal 8a, the wirings 8b and 8c, the wide region 8d, and the connection terminal 8e are already integrally formed in each unit region UR on the mold surface of the wiring board base 5M. Since the antenna connection terminal 8a, the wirings 8b and 8c, the wide region 8d, and the connection terminal 8e are also patterned at the same time, the IC card 1 can be manufactured without increasing the cost. Such a wiring board base 5M is carried into the assembling apparatus while being wound around a reel.

  Next, the capacitor C is mounted on each unit region UR of the wiring board base 5M (step CB1 in FIG. 15). FIG. 19 shows an example of an assembly apparatus 25 used in this process. The mounting process of the capacitor C is performed until the wiring board base 5M of the first reel 26a is sent to the second reel 26b (reel-to-reel connection). First, in the solder application part 25a of the assembling apparatus 25, the solder 20 in the paste state is applied to the connection terminals 8e on the mold surface of the wiring board base 5M. The solder 20 is made of the above-described material and uses solder with a small amount of flux. Subsequently, the wiring board base body 5M portion on which the solder application has been completed is sent to the chip mounting portion 25b of the assembling apparatus 25. In the chip mounting portion 25b, the connection terminal of the capacitor C adsorbed by a vacuum suction pad or the like and the connection terminal 8e of the wiring board base 5M are aligned, and then the capacitor C is pressed against the connection terminal 8e to be temporarily connected. Thereafter, the wiring board base 5M portion for which the chip mounting process has been completed is sent to the reflow heating section 25c of the assembling apparatus 25. In the reflow heating unit 25c, the solder 20 is melted by heat treatment, and the connection terminal of the capacitor C and the connection terminal 8e of the wiring board base 5M are firmly fixed and electrically connected. The reflow heating unit 25c is provided with a shutter that blocks the heat of the reflow furnace. Accordingly, the heating amount can be adjusted by closing the shutter when trouble occurs or when stop and go is stopped. The stop-and-go refers to an operation in which, for example, when the capacitor C is mounted, the tape feeding is temporarily stopped (STOP), and after the mounting process of the capacitor C or the like, the tape feeding operation is performed again (GO). FIG. 20 shows an enlarged plan view of the main part of the mold surface of the wiring board base 5M after the above steps. A capacitor C is mounted between adjacent connection terminals 8e, 8e of each unit region UR. In the first embodiment, since the capacitor C is mounted on the wiring board base 5M made of a glass epoxy resin film having high heat resistance, the connection using the solder 20 is possible. After the mounting process of the capacitor C as described above, the assembling apparatus 25 can perform an electrical characteristic inspection (connection state, capacitance value measurement, etc.), an appearance inspection, and the like of the capacitor C. For this reason, the wiring (wiring 8c etc.) of the wiring board base 5M is routed so that electrical inspection can be performed. As described above, in the first embodiment, it is possible to inspect the electrical characteristics and the appearance of the capacitor C in the integrated line for mounting the capacitor by the feeding operation of the tape-shaped wiring board base 5M. In this case, workability and efficiency can be improved and product management can be facilitated as compared with the case where the above inspection is performed outside the consistent line. Therefore, the ease of the assembly process of the IC card 1 can be greatly improved. Further, the assembly time of the IC card 1 can be greatly shortened. Further, by performing the above inspection at the head of the consistent line, it is possible to grasp and sort out the characteristic failure and connection failure of the capacitor C in advance, so that the defect related to the capacitor C does not reach the IC card 1. That is, it is possible to prevent a non-defective IC chip from being defective due to a defect in the capacitor C. Therefore, the yield of the IC card 1 can be improved, and the cost of the IC card 1 can be reduced.

  Next, the IC chip 3 is mounted and molded in each unit region UR of the wiring board base 5M (steps CB2, WB, and PKG in FIG. 15). FIG. 21 shows an example of the assembling apparatus 27 used in this process. This process is performed until the wiring board base 5M of the second reel 26b is sent to the third reel 26c (reel-to-reel connection).

  First, in the adhesive material application part 27a of the assembling apparatus 27, it is applied to the IC chip mounting region on the mold surface of the wiring board base 5M using an epoxy adhesive or the like. Subsequently, in the chip mounting portion 27b of the assembling apparatus 27, the IC chip 3 sucked by the vacuum suction pad or the like is aligned, and then pressed against the wiring board base 5M to be temporarily connected. Thereafter, in the reflow heating unit 27c of the assembling apparatus 27, the adhesive is melted by heat treatment to firmly fix the IC chip 3 to the mold surface of the wiring board base 5M (COT (Chip On Tape), step CB2 in FIG. ).

  Subsequently, after the IC chip mounting process, the process proceeds to a wire bonding process without performing a water washing process. That is, in the wire bonding portion 27 d of the assembling apparatus 27, the bonding pad 12 of the IC chip 3 is connected to the module terminal 4 and the wide region 8 d by the bonding wire 14. The reason why the process is shifted to the wire bonding process without performing the water washing process is to avoid such a problem because the surface of the module terminal 4 may be contaminated with water when the water washing process is performed. . The reason why the solder with less flux is used as the solder 20 as described above is to eliminate the water washing step. FIG. 22 shows an enlarged plan view of the main part of the mold surface of the wiring board base 5M after the wire bonding step. The bonding pad 12 of the IC chip 3 in each unit region UR is electrically connected to the module terminal 4 and the wide region 8d by the bonding wire 14 (step WB in FIG. 15).

  Next, after the wire bonding step, in the mold part 27e of the assembling apparatus 27 in FIG. 21, the sealing parts 6a of the plurality of unit regions UR are collectively formed by the transfer molding method. That is, the mold surface and the contact surface of each of the plurality of unit regions UR of the wiring board base 5M are sandwiched between the lower mold 27e1 and the upper mold 27e2 of the mold, for example, in the mold cavity 27e3. A plurality of sealing portions 6a are collectively formed on the mold surface by pouring glass epoxy resin. The temperature at the time of a sealing process is about 180 degree | times at the maximum, for example. Since the solder 20 or the like having a melting point higher than the temperature at the time of the sealing process is used, the solder 20 is not melted by the sealing process. Further, in this sealing step, an arrangement is made such that the position of the injection port (gate) for pouring the sealing resin into the cavity 27e3 and the position of the capacitor C on the wiring board base 5M are separated in the mold. It is said that. That is, when the capacitor C is located near the injection port, the resin melted during the molding process may hit the capacitor C and cause voids due to entrainment. Therefore, in the first embodiment, by separating the position of the injection port and the capacitor C, it is possible to suppress or prevent the generation of voids in the sealing portion 6a. FIG. 23 shows an enlarged plan view of the main part of the mold surface of the wiring board base 5M after the molding process. The IC chip 3, the capacitor C, the bonding wire 14, the bonding hole 13, and the like in each unit region UR are covered with a sealing portion 6a. The antenna connection terminal 8a is exposed from the sealing portion 6a (step PKG in FIG. 15).

  After the IC module 2 is formed in each of the unit regions UR of the wiring board base 5M as described above, each IC module 2 is cut out from the wiring board base 5M (step CUT in FIG. 15). Thereafter, the cut out IC module 2 is fitted into the recess 7 a of the card body 7. At this time, the antenna connection terminal 8a of the IC module 2 and the coil L in the card body 7 are joined by an adhesive that can be joined at a relatively low temperature such as conductive resin paste containing silver (step MB in FIG. 15). ). In this way, the IC card 1 is manufactured.

  In the manufacturing process of the IC card 1 having the capacitor C for the resonance circuit that forms a general non-contact type interface, the capacitor C must be mounted on each of the card bodies 7, so that the manufacturing process is performed. Is complicated and causes an increase in cost. On the other hand, in the first embodiment, the capacitor C is mounted in the flow using the tape-shaped wiring board base 5M, and the capacitor C is incorporated into the IC module 2 during the manufacturing process. When the IC module 2 is attached to the card body 7, the capacitor C is also incorporated in the entire circuit of the IC card 1. For this reason, according to the first embodiment, it is possible to facilitate the assembly of the IC card 1 having the resonance circuit capacitor C forming the non-contact type interface. Moreover, the cost of the IC card 1 can be reduced.

(Embodiment 2)
In the second embodiment, a modified example of the sealing portion 6a of the IC card 1 will be described.

  FIG. 24 shows an example of a plan view of the mold surface of the wiring board 5 during the manufacturing process of the IC card 1 of the second embodiment. In the second embodiment, the shape of the sealing portion is different from that of the sealing portion 6a of the first embodiment, and the connection region (connection terminal 8e) of the capacitor for the resonance circuit is exposed from the sealing portion 6b. ing.

  FIG. 25 shows a plan view of the mold surface of the wiring board 5 after the capacitor C is mounted in FIG. 25 is the same as FIG. 7 except for the inside of the sealing portion 6b. In the second embodiment, the capacitor C is mounted outside the sealing portion 6b. Moreover, in the manufacturing process of the IC card 1, the capacitor C is mounted after the forming process of the sealing portion 6b. The mounting process of the capacitor C may be performed when the wiring board base 5M is in the state as in the first embodiment, or may be after the individual wiring boards 5 are cut out from the wiring board base 5M. The rest is the same as in the first embodiment. Further, since the material and forming process of the sealing portion 6b are the same as those of the sealing portion 6a, description thereof is omitted.

  Thus, according to the second embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained. That is, by allowing the capacitor C to be mounted after the sealing process, the value may be changed or the value may be shifted to the tuning value on the reader / writer side due to a change in the specification of the coil L of the card body 7 of the IC card 1. Even in the case where the capacitor C is generated, the capacitor C having the optimum capacitance value according to the value of the coil L and the reader / writer can be mounted. For this reason, the resonance frequency of the non-contact type interface of the IC card 1 can be set to an optimum value. Further, by mounting the capacitor C outside the sealing portion 6b, the solder 20 is not affected by the sealing temperature, so that the degree of freedom in selecting the material of the solder 20 can be improved. Furthermore, since the wiring board base 5M or the wiring board 5 in which the process up to the formation of the sealing portion 6b has been completed can be prepared, the manufacturing time of the IC card 1 can be greatly reduced.

(Embodiment 3)
In the third embodiment, the shape of the sealing portion 6a of the IC card 1 remains the same as that of the first embodiment, and the capacitor C for the resonance circuit can be mounted after the sealing process. An example will be described.

  FIG. 26 shows an example of a plan view of the mold surface of the wiring board 5 (wiring board base 5M) during the manufacturing process of the IC card 1 of the third embodiment. In the third embodiment, the sealing portion 6a is the same as that of the first embodiment, but the mounting area (connection terminal 8e) of the capacitor C is arranged outside the sealing portion 6a. In this case, the end of each wiring 8b of the wiring substrate 5 extends to the outside of the region of the sealing portion 6a, and the connection terminal 8e is integrally formed at the end of the wiring 8b.

  FIG. 27 shows an overall plan view of the mold surface after the capacitor C is mounted on the wiring board 5 of FIG. Also in the third embodiment, the capacitor C is mounted outside the sealing portion 6a. Also in the manufacturing process of the IC card 1, the capacitor C is mounted after the forming process of the sealing portion 6a. The mounting process of the capacitor C may be performed when the wiring board base 5M is in the state as in the first embodiment, or may be after the individual wiring boards 5 are cut out from the wiring board base 5M. The rest is the same as in the first embodiment.

  According to the third embodiment, in addition to the effects obtained in the first and second embodiments, the following effects can be obtained. That is, it is not necessary to change the mold (the lower mold 27e1 and the upper mold 27e2) of the mold part 27e, and the mold part 27e currently used can be used as it is.

(Embodiment 4)
In the fourth embodiment, an example of a configuration in which the shape of the sealing portion 6a is not changed, and the capacitance value of the resonance circuit capacitor can be changed (adjusted) after the sealing step will be described.

  FIG. 28 shows an example of a plan view of the mold surface of the wiring board 5 (wiring board base 5M) of the IC card 1 according to the fourth embodiment. In the fourth embodiment, there are, for example, two mounting areas for the capacitor C for the resonance circuit, one being arranged in the area of the sealing part 6a and the other being arranged outside the area of the sealing part 6a. Yes. In this case, the end of each wiring 8b is divided into two, and the connection terminal 8e1 formed integrally with the extending end of one wiring 8b1 is disposed in the region of the sealing portion 6a, The connection terminal 8e2 formed at the extending end of the wiring 8b2 is disposed outside the area of the sealing portion 6a.

  FIG. 29 shows an example of a plan view of a mold surface of the wiring board 5 (wiring board base 5M) after the IC chip 3 and the capacitor C1 (C) for the resonance circuit are mounted in FIG. 28 and subjected to the wire bonding process. ing. FIG. 30 shows an example of a plan view of the mold surface of the wiring board 5 (wiring board base 5M) after the sealing portion 6a is formed in FIG. This capacitor C1 is mounted in the region of the sealing portion 6a. Here, no capacitor is mounted on the connection terminal 8e2 outside the sealing portion 6a. It can also be used as the IC module 2 at this stage. However, there are cases where it is desired to adjust the capacitance value based on the relationship with the coil L and the reader / writer as described above. In that case, an adjustment capacitor is mounted on the connection terminal 8e2 outside the sealing portion 6a. FIG. 31 shows an example of a plan view of the mold surface of the wiring board 5 (wiring board base 5M) after mounting the capacitor C2 (C) for the resonance circuit in FIG. The capacitor C2 is mounted outside the sealing part 6a and is connected in parallel to the capacitor C1 in the sealing part 6a.

  According to the fourth embodiment, in addition to the effects obtained in the first, second, and third embodiments, the following effects can be obtained. That is, the capacitance value of the capacitor for the resonance circuit can be finely adjusted after the sealing step. In addition, since the wiring board base 5M or the wiring board 5 in which the process up to the formation of the sealing portion 6a including the capacitor C1 for the resonance circuit is completed can be prepared, the manufacturing time of the IC card 1 can be greatly reduced. It can be shortened.

(Embodiment 5)
In the fifth embodiment, the case where the sealing portion 6a of the fourth embodiment is replaced with the sealing portion 6b of the second embodiment will be described. 32 and 33 show an example of a plan view of the mold surface of the wiring board 5 (wiring board base 5M) of the IC card 1 of the fifth embodiment. 32 is the same as FIG. 29 except for the inside of the sealing portion 6b. In the fifth embodiment, the mounting area of the two capacitors C1 and C2 for the resonance circuit is arranged outside the sealing portion 6b. FIG. 32 illustrates a case where only one capacitor C1 is mounted. In some cases, the IC module 2 may be used at this stage. FIG. 33 illustrates the case where two capacitors C1 and C2 are mounted. In some cases, the IC module 2 may be used at this stage. The capacitors C1 and C2 may be mounted when the wiring board base 5M is in the same manner as in the first to fourth embodiments, or may be mounted on the wiring board 5 after being cut out from the wiring board base 5M. .

  According to the fifth embodiment, it is possible to obtain the same effects as those obtained in the first, second, third, and fourth embodiments (excluding the effect that the current mold can be used).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first to fifth embodiments, the wiring board is not limited to the glass epoxy resin, and for example, a polyimide resin having higher flexibility than the glass epoxy resin may be used.

  In the first to fifth embodiments, the case where the IC chip 3 and the capacitor C are mounted has been described. However, other electronic components can also be mounted. For example, when a USB (Universal Serial Bus) function is attached to an IC card, an oscillator is required, but it can be mounted on the wiring board 5.

  In the first to fifth embodiments, the case where the present invention is applied to a non-contact type and contact type dual interface IC card has been described. However, the present invention is not limited to this, and can be applied to a non-contact type IC card, for example. . In a general non-contact type IC card, a wiring board is not used. However, in the case of this embodiment, the wiring board is built into the card body as in the first to fifth embodiments. However, the module terminal 4 is not formed on the exposed surface of the wiring board in this case.

  In the above description, the case where the invention made mainly by the present inventor is applied to an IC card which is a field of use that is the background of the invention has been described. However, the present invention is not limited to this and has a non-contact interface resonant circuit. It can also be applied to other semiconductor devices.

  As described above, the semiconductor device according to the present invention includes, for example, a credit card, a cash card, an ETC (Electronic Toll Collection system) system card, a commuter pass, a public phone card, a mobile phone card or an authentication card, It is suitable for use in IC (Integrated Circuit) cards that are being used in various fields such as transportation, communication, distribution and authentication.

It is a whole top view of an example of the semiconductor device which is one embodiment of the present invention. It is a principal part expanded sectional view of the X1-X1 line | wire of FIG. FIG. 2 is an overall plan view showing a main part removed from the semiconductor device of FIG. 1. FIG. 4 is an essential part enlarged cross-sectional view taken along line X1-X1 in FIG. 3. FIG. 2 is an overall plan view of an example of a contact surface of a main part of the semiconductor device of FIG. 1. FIG. 2 is an overall plan view of an example of a mold surface of a main part of the semiconductor device of FIG. 1. It is a whole top view of an example of the mold surface which removed the sealing part of FIG. It is sectional drawing of the Y1-Y1 line | wire of FIG. 6 and FIG. It is sectional drawing of the X2-X2 line | wire of FIG. FIG. 2 is a circuit diagram showing a connection relationship between a capacitor and a coil constituting a non-contact type interface of the semiconductor device of FIG. 1. FIG. 7 is an enlarged cross-sectional view of an example of the capacitor of the semiconductor device of FIG. 6 (taken along line X3-X3 in FIG. 7). FIG. 8 is an overall plan view of the mold surface shown by removing the semiconductor chip and the capacitor of the semiconductor device from FIG. 7. It is explanatory drawing which shows the mode of arrangement | positioning of the antenna connection terminal in the principal part of the semiconductor device of FIG. 1, and the mode of the connection relation of the antenna connection terminal and a coil. It is explanatory drawing which showed the mode of other arrangement | positioning of the antenna connection terminal which this inventor examined for the comparison. FIG. 2 is a flowchart of an example of a manufacturing process of the semiconductor device of FIG. 1. FIG. 2 is an enlarged plan view of a main part of an example of a wiring board matrix used in the manufacturing process of the semiconductor device of FIG. 1. FIG. 17 is an enlarged plan view of a main part of an example of a contact surface of the wiring board base body of FIG. 16. It is a principal part enlarged plan view of an example of the mold surface of the wiring board mother body of FIG. It is explanatory drawing of an example of the assembly apparatus used at the capacitor | condenser mounting process of the semiconductor device of FIG. FIG. 2 is an enlarged plan view of a main part of a wiring board base body during a manufacturing process of the semiconductor device of FIG. It is explanatory drawing of an example of the assembly apparatus used at the semiconductor chip mounting process of the semiconductor device of FIG. FIG. 2 is an enlarged plan view of a main part of a wiring board base body after a wire bonding step of the semiconductor device of FIG. 1. FIG. 2 is an enlarged plan view of a main part of a wiring board base body after a molding process of the semiconductor device of FIG. 1. It is a top view of an example of the mold surface of the wiring board in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 25 is a plan view of the mold surface of the wiring board after mounting the capacitor in FIG. 24. It is a top view of an example of the mold surface of the wiring board in the manufacturing process of the semiconductor device which is further another embodiment of this invention. FIG. 27 is a plan view of the mold surface of the wiring board after the capacitor is mounted in FIG. 26. It is a top view of an example of the mold surface before chip | tip mounting of the wiring board in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 28 is a plan view of an example of a mold surface of a wiring board after mounting a semiconductor chip and an internal capacitor. It is a top view of an example of the mold surface of the wiring board after forming the sealing part in FIG. FIG. 30 is a plan view of an example of a mold surface of a wiring board after mounting an external capacitor in FIG. 30. It is a whole top view of an example of the mold surface after mounting one capacitor | condenser on the wiring board in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is a whole top view of an example of the mold surface after mounting two capacitors on the wiring board in the manufacturing process of the semiconductor device which is other embodiments of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 IC card 2 IC module 2 Card main body 3 IC chip 4 (4a-4h) Module terminal 4h Non-connect terminal 5 Wiring board 5M Wiring board mother body 6a, 6b Sealing part 7 Card main body 7a Recessed part 8a Antenna connection terminal 8b, 8b1, 8b2, 8c Wiring 8d Wide part 8d Wide area,
8e (8e1, 8e2) Connection terminal 10 Conductive adhesive 12 Bonding pad 13 Bonding hole 14 Bonding wire 16a, 16b Connection terminal 17a, 17b Electrode 18 Ceramic dielectric 20 Solder 22 Sprocket hole 23 Wiring 25 Assembly device 25a Solder coating part 25b Chip mounting part 25c Reflow heating part 26a First reel 26b Second reel 26c Third reel 27 Assembly device 27a Adhesive material application part 27b Chip mounting part 27c Reflow heating part 27d Wire bonding part 27e Mold part 27e1 Lower mold 27e2 Upper mold 27e3 Cavity C, C1, C2 Capacitors CB1, CB2, CP, CUT, MB, PKG, WB Process Cs Floating capacitance L Coil Lt Connection terminal UR Unit region f Resonance frequency

Claims (8)

A semiconductor device mounted on a card body having an antenna coil for performing wireless communication with an external transmission / reception device,
The semiconductor device includes:
A wiring board having a main surface and a back surface opposite to the main surface;
A first connection terminal provided on a main surface of the wiring board and electrically connected to one end of the antenna coil via a first conductive material;
A second connection terminal provided on the main surface of the wiring board and electrically connected to the other end of the antenna coil via the first conductive material;
A semiconductor chip mounted on the main surface of the wiring board and further electrically connected to the first connection terminal and the second connection terminal and processing data;
A third connection terminal provided on a main surface of the wiring board and electrically connected to the first connection terminal by wiring of the wiring board;
A fourth connection terminal provided on a main surface of the wiring board and electrically connected to the second connection terminal by the wiring;
A capacitor that forms a resonance circuit by electrically connecting one end to the third connection terminal and the other end to the fourth connection terminal via a second conductive material;
The semiconductor device according to claim 1, wherein the first connection terminal and the second connection terminal are arranged on different sides of the semiconductor chip.   The semiconductor device according to claim 1, wherein the first connection terminal and the second connection terminal are arranged so as to sandwich the semiconductor chip.   3. The semiconductor chip according to claim 2, wherein the semiconductor chip has a sealing portion sealed with resin, and the first connection terminal and the second connection terminal are arranged so as to sandwich the sealing portion. The semiconductor device described.   The semiconductor device according to claim 3, wherein the capacitor is a chip-type ceramic capacitor. The semiconductor chip is
A central processing unit for processing the data;
ROM storing execution programs, encryption algorithms, etc. in the central processing unit;
A RAM having a function as a memory for data processing;
An EEPROM having a function as a memory for storing data;
The semiconductor device according to claim 1, further comprising: another arithmetic circuit. A first land portion provided on a main surface of the wiring board and electrically connected to the first connection terminal by the wiring;
A second land portion provided on a main surface of the wiring board and electrically connected to the second connection terminal by the wiring;
The first land portion and the second land portion are each connected by a bonding pad and a bonding wire provided on the main surface of the semiconductor chip, and the first connection terminal and the second connection terminal are: The semiconductor device according to claim 1, wherein the semiconductor device is electrically connected to the semiconductor chip. On the back surface of the wiring board, there is an external terminal for communicating with a corresponding terminal of an external transmission / reception device,
A through hole is provided from the main surface of the wiring board to the back surface so that a part of the back surface of the external terminal is exposed,
The semiconductor device according to claim 6, wherein the bonding pad and the back surface of the external terminal are electrically connected to each other by a bonding wire through the through hole. A semiconductor device mounted on a card body having an antenna coil for performing wireless communication with an external transmission / reception device,
The semiconductor device includes:
A wiring board having a main surface and a back surface opposite to the main surface;
A first connection terminal provided on a main surface of the wiring board and electrically connected to one end of the antenna coil via a first conductive material;
A second connection terminal provided on the main surface of the wiring board and electrically connected to the other end of the antenna coil via the first conductive material;
A semiconductor chip mounted on the main surface of the wiring board and further electrically connected to the first connection terminal and the second connection terminal and processing data;
A third connection terminal provided on a main surface of the wiring board and electrically connected to the first connection terminal by wiring of the wiring board;
A fourth connection terminal provided on a main surface of the wiring board and electrically connected to the second connection terminal by the wiring;
A capacitor that forms a resonance circuit by electrically connecting one end to the third connection terminal and the other end to the fourth connection terminal via a second conductive material;
A sealing portion in which the semiconductor chip is resin-sealed,
The semiconductor device, wherein the first connection terminal and the second connection terminal are arranged so as to sandwich the sealing portion.

Images