JP2009065099A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2009065099A JP2009065099A JP2007233989A JP2007233989A JP2009065099A JP 2009065099 A JP2009065099 A JP 2009065099A JP 2007233989 A JP2007233989 A JP 2007233989A JP 2007233989 A JP2007233989 A JP 2007233989A JP 2009065099 A JP2009065099 A JP 2009065099A
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- fin
- drain
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
【解決手段】埋め込み酸化膜2の上に互いに分離して形成される複数のフィン3と、これらフィン3の一端側を共通に接続する第1のコンタクト領域4と、これらフィン3の他端側を共通に接続する第2のコンタクト領域5と、これらフィン3に跨るように配置されるゲート電極6と、ゲート電極6よりも第1のコンタクト領域4側のフィン3と第1のコンタクト領域4とを含むソース領域7と、ゲート電極6よりも第2のコンタクト領域5側のフィン3と第2のコンタクト領域5とを含むドレイン領域8と、を備えている。ドレイン側のフィン3における抵抗Rdがソース側のフィン3における抵抗Rsよりも10倍以上大きくなるようにしたため、トランジスタのコンダクタンスgmと出力抵抗routの積で表されるgm*routを大きくすることができ、耐ノイズ性能が向上する等、電気的特性がよくなる。
【選択図】図1
Description
vout/vin=gm*rout …(1)
ここで、gmはトランスコンダクタンス、routは出力抵抗を表している。
(1)ドレイン側のフィン3の幅をソース側のフィン3の幅よりも狭くする。
(2)ドレイン側のフィン3の長さをソース側のフィン3の長さよりも長くする。
(3)ドレイン側のフィン3の高さを低くする。
(4)ドレイン側のフィン3のみシリサイド層を形成しない。
(5)ドレイン側のフィン3の不純物濃度を下げる。
2 埋め込み酸化膜
3 フィン
4 第1のコンタクト領域
5 第2のコンタクト領域
6 ゲート電極
7 ソース領域
8 ドレイン領域
9 ゲート絶縁膜
Claims (5)
- 半導体基板上に互いに分離して形成される複数のフィンと、
前記複数のフィンの一端側を共通に接続する第1のコンタクト領域と、
前記複数のフィンの他端側を共通に接続する第2のコンタクト領域と、
前記複数のフィンそれぞれの少なくとも両側面にゲート絶縁膜を挟んで対向配置されるゲート電極と、
前記ゲート電極よりも前記第1のコンタクト領域側の前記複数のフィンと前記第1のコンタクト領域とを含むソース領域と、
前記ゲート電極よりも前記第2のコンタクト領域側の前記複数のフィンと前記第2のコンタクト領域とを含むドレイン領域と、を備え、
前記ドレイン領域内の各フィンにおける抵抗値Rdと前記ソース領域内の各フィンにおける抵抗値Rsとの比の値Rd/Rsは、10以上であることを特徴とする半導体装置。 - 前記ソース領域内の前記フィンの幅は、前記ドレイン領域内の前記フィンの幅より太いことを特徴とする請求項1に記載の半導体装置。
- 前記ソース領域内の前記フィンの長さは、前記ドレイン領域内のフィンの長さより短いことを特徴とする請求項1または2に記載の半導体装置。
- 前記ソース領域内の前記フィンの高さは、前記ドレイン領域内の前記フィンの高さより高いことを特徴とする請求項1乃至3のいずれかに記載の半導体装置。
- 前記ソース領域および前記ドレイン領域内の前記フィンは、半導体層を有し、
前記ソース領域および前記ドレイン領域内の前記フィンのうち、前記ソース領域のみに対応して、前記半導体層の上に形成されるシリサイド層を有することを特徴とする請求項1乃至4のいずれかに記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007233989A JP4455632B2 (ja) | 2007-09-10 | 2007-09-10 | 半導体装置 |
US12/207,121 US7923788B2 (en) | 2007-09-10 | 2008-09-09 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007233989A JP4455632B2 (ja) | 2007-09-10 | 2007-09-10 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009065099A true JP2009065099A (ja) | 2009-03-26 |
JP4455632B2 JP4455632B2 (ja) | 2010-04-21 |
Family
ID=40430928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007233989A Expired - Fee Related JP4455632B2 (ja) | 2007-09-10 | 2007-09-10 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7923788B2 (ja) |
JP (1) | JP4455632B2 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014068017A (ja) * | 2012-09-26 | 2014-04-17 | Samsung Electronics Co Ltd | 非対称シリサイド構造を含む電界効果トランジスタ及び関連した装置 |
JP2016046394A (ja) * | 2014-08-22 | 2016-04-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2018160704A (ja) * | 2018-07-18 | 2018-10-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010040630A (ja) * | 2008-08-01 | 2010-02-18 | Toshiba Corp | 半導体装置 |
US9385050B2 (en) | 2011-01-06 | 2016-07-05 | Globalfoundries Inc. | Structure and method to fabricate resistor on finFET processes |
JP2013045901A (ja) * | 2011-08-24 | 2013-03-04 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP5580355B2 (ja) | 2012-03-12 | 2014-08-27 | 株式会社東芝 | 半導体装置 |
US9231106B2 (en) | 2013-03-08 | 2016-01-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with an asymmetric source/drain structure and method of making same |
CN103219384B (zh) * | 2013-04-03 | 2015-05-20 | 北京大学 | 一种抗单粒子辐射的多栅器件及其制备方法 |
US9349863B2 (en) * | 2013-08-07 | 2016-05-24 | Globalfoundries Inc. | Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet |
KR102380818B1 (ko) * | 2015-04-30 | 2022-03-31 | 삼성전자주식회사 | 반도체 소자 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0786307A (ja) | 1993-09-13 | 1995-03-31 | Toshiba Corp | 電界効果トランジスタ及びその製造方法 |
US7358121B2 (en) * | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
US6909151B2 (en) * | 2003-06-27 | 2005-06-21 | Intel Corporation | Nonplanar device with stress incorporation layer and method of fabrication |
US7388258B2 (en) * | 2003-12-10 | 2008-06-17 | International Business Machines Corporation | Sectional field effect devices |
US7115947B2 (en) * | 2004-03-18 | 2006-10-03 | International Business Machines Corporation | Multiple dielectric finfet structure and method |
JP3905098B2 (ja) | 2004-07-02 | 2007-04-18 | 旭化成マイクロシステム株式会社 | 半導体装置の製造方法 |
KR100682892B1 (ko) * | 2004-09-25 | 2007-02-15 | 삼성전자주식회사 | 박막 트랜지스터의 제조방법 |
JP4064955B2 (ja) | 2004-09-30 | 2008-03-19 | 株式会社東芝 | 半導体装置及びその製造方法 |
EP1892765A1 (en) * | 2006-08-23 | 2008-02-27 | INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM vzw (IMEC) | Method for doping a fin-based semiconductor device |
US7838948B2 (en) * | 2007-01-30 | 2010-11-23 | Infineon Technologies Ag | Fin interconnects for multigate FET circuit blocks |
-
2007
- 2007-09-10 JP JP2007233989A patent/JP4455632B2/ja not_active Expired - Fee Related
-
2008
- 2008-09-09 US US12/207,121 patent/US7923788B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014068017A (ja) * | 2012-09-26 | 2014-04-17 | Samsung Electronics Co Ltd | 非対称シリサイド構造を含む電界効果トランジスタ及び関連した装置 |
JP2016046394A (ja) * | 2014-08-22 | 2016-04-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10446655B2 (en) | 2014-08-22 | 2019-10-15 | Renesas Electronics Corporation | Semiconductor device |
JP2018160704A (ja) * | 2018-07-18 | 2018-10-11 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20090065869A1 (en) | 2009-03-12 |
JP4455632B2 (ja) | 2010-04-21 |
US7923788B2 (en) | 2011-04-12 |
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