JP2009050139A - Dc/dc converter and drive device using it - Google Patents

Dc/dc converter and drive device using it Download PDF

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Publication number
JP2009050139A
JP2009050139A JP2007336878A JP2007336878A JP2009050139A JP 2009050139 A JP2009050139 A JP 2009050139A JP 2007336878 A JP2007336878 A JP 2007336878A JP 2007336878 A JP2007336878 A JP 2007336878A JP 2009050139 A JP2009050139 A JP 2009050139A
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terminal
current
voltage
led
converter
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JP2007336878A
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JP5097534B2 (en
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Masataka Oomi
昌貴 大参
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Rohm Co Ltd
ローム株式会社
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Priority claimed from US12/178,793 external-priority patent/US8405321B2/en
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    • Y02B20/42

Abstract

<P>PROBLEM TO BE SOLVED: To provide a DC/DC converter capable of reducing a singing sound of an input bypass capacitor. <P>SOLUTION: In this DC/DC converter, an input voltage is smoothed by using the input bypass capacitor connected between the application end of the input voltage and the grounding end, and the smoothed voltage is converted to a desired output voltage to be supplied to a load. The input bypass converter is constituted by connecting a plurality of capacitors in parallel. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a DC / DC converter that converts an input voltage into a desired output voltage and supplies the converted voltage to a load (such as a light emitting diode), and a drive device using the DC / DC converter.

Currently, cold cathode fluorescent lamps (CCFLs) are mainly used as backlights for LCD [Liquid Crystal Display] panels (for example, car navigation monitors). In recent years, white LEDs [Light Emitting Diodes] have been put into practical use because of advantages such as a wide brightness adjustment range, power saving, long life, low drive voltage, and Hg-free, and an LED drive device that performs drive control (so-called so-called Various techniques have also been disclosed and proposed for LED drivers (see, for example, Patent Document 1).
JP 2007-13183 A

  With the use of such backlights as LEDs, there is a demand for LED drivers that drive the backlights to further extend battery life and to reduce power consumption by dimming the screen. The driving device is required to have the ability to control the LED luminance to a low luminance range with high accuracy.

  Note that a drive device that drives a load other than the LED is also required to have the ability to control the load with high accuracy up to a low drive range, as described above.

  Further, in a DC / DC converter that converts an input voltage into a desired output voltage and supplies it to a load, when voltage fluctuation is applied to an input bypass capacitor that is an input smoothing means, the substrate is shaken by expansion and contraction of the element. May cause noise. In particular, when the capacitance value of the input bypass capacitor is large, the element size is increased, and it is easy to generate noise.

  An object of this invention is to provide the DC / DC converter which can reduce the sound of an input bypass capacitor, and a drive device using the same in view of said problem.

  In order to achieve the above object, a DC / DC converter according to the present invention smoothes the input voltage by using an input bypass capacitor connected between an input voltage application terminal and a ground terminal, and converts the input voltage to a desired value. A DC / DC converter that converts an output voltage and supplies the load to a load, wherein the input bypass capacitor has a configuration in which a plurality of capacitors are connected in parallel (first configuration).

  In the DC / DC converter having the first configuration, the plurality of capacitors forming the input bypass capacitor may all be the same type of capacitor (second configuration).

  Further, in the DC / DC converter having the first or second configuration, the plurality of capacitors forming the input bypass capacitor may all be arranged in the same direction (third configuration). .

  Alternatively, in the DC / DC converter having the first or second configuration, the plurality of capacitors forming the input bypass capacitor may be arranged in different directions (fourth configuration).

  In the DC / DC converter having any one of the first to fourth configurations, the plurality of capacitors forming the input bypass capacitor are distributed on the front surface side and the back surface side of the substrate. (Fifth configuration) is preferable.

  The DC / DC converter having any one of the first to fifth configurations includes a coil having one end connected to the input voltage application end, a transistor having one end connected to the other end of the coil, and an anode Is connected to the other end of the coil, a cathode is connected to one end of the load, an output capacitor connected between the cathode of the diode and a ground terminal, and a feedback voltage drawn from the other end of the load A control unit that performs on / off control of the transistor on the basis of the distance between the connection of the diode and the output capacitor, the distance between the connection of the coil and the diode A configuration shorter than the distance (sixth configuration) may be used.

  The drive device according to the present invention is a drive device including a battery and a DC / DC converter that converts an input voltage supplied from the battery into a desired output voltage and supplies the output voltage to a load. The DC / DC converter includes a DC / DC converter having any one of the first to sixth configurations (seventh configuration).

  Note that the drive device having the seventh configuration may have a configuration (eighth configuration) including a noise reduction capacitor connected in parallel with the load.

  According to the present invention, it is possible to reduce the noise of the input bypass capacitor.

  FIG. 1 is a block diagram showing an embodiment of a semiconductor device according to the present invention.

  First, an outline of the semiconductor device 10 of this embodiment will be described.

  The semiconductor device 10 of the present embodiment shown in FIG. 1 includes a PWM [Pulse Width Modulation] DC / DC converter capable of boosting up to 42.5 [V] and a current driver capable of driving up to 25 [mA]. This is an integrated white LED driver IC. By controlling the power control terminal (PWMPOW terminal) of the IC or the power control terminal (PWMDRV terminal) of the current driver with an external PWM signal, it is possible to perform a wide range and high-precision luminance control. In addition, a current driver with high specific accuracy is employed, and there is little error between columns of the current driver, which is optimal for reducing luminance unevenness of the display. In addition, the semiconductor device 10 is a small package that is advantageous in reducing the size and space of the substrate.

  Next, features of the semiconductor device 10 of this embodiment will be described.

  The first feature is that a high-efficiency PMW DC / DC converter (fsw = 1 [MHz], maximum efficiency 93 [%]) is incorporated. The second feature is that a high-precision and high-matching (± 3%) current driver (6 channels) is incorporated. The third feature is that it can drive a maximum of 72 white LEDs (= 12 series × 6 parallel). The fourth feature is that it corresponds to a wide input voltage range (2.7 to 22 [V]). The fifth feature is that abundant protection circuits (overvoltage protection unit, overcurrent protection unit, external SBD disconnection protection unit, thermal shutdown unit) are incorporated. The sixth feature is that it is a small package (4.0 × 4.0 × 1.0 [mm]).

  The semiconductor device 10 of the present embodiment is preferably used as a backlight driving unit for a medium-sized LCD panel mounted on a mobile notebook PC, a portable DVD player, a car navigation system, or the like.

  As shown in FIG. 1, the semiconductor device 10 of the present embodiment having the above features includes an internal voltage generation unit 101 (hereinafter referred to as a REG unit 101) and a temperature protection unit 102 (hereinafter referred to as TSD [Thermal Shutdown]. Dwom] unit 102), internal voltage detection unit 103, voltage drop protection unit 104 (hereinafter referred to as UVLO [Under Voltage Lock Out] unit 104), and Schottky barrier diode removal protection unit 105 (hereinafter referred to as SBD). [Shotkey Barrier Diode] disconnect protection unit 105), overvoltage protection unit 106 (hereinafter referred to as OVP [Over Voltage Protection] unit 106), error amplifier 107, PWM comparator 108, soft start unit 109, An oscillator unit 110, a slope voltage generation unit 111, a current detection unit 112, a control logic unit 113, an SR flip-flop 114, a driver Bar 115, LED terminal detection unit 116, LED terminal overvoltage protection unit 117, first current (ISETH) setting unit 118, second current (ISETL) setting unit 119, switch 120, inverter 121, and switch 122 and a current driver 123 are integrated.

  In addition, the semiconductor device 10 of the present embodiment has 24 external terminals (1 to 24 pins) as means for establishing electrical connection with the outside.

  2 is a correspondence table showing pin numbers of external terminals, terminal names, input / output classifications, functions, and group classifications of terminal equivalent circuit diagrams, and FIG. 3 is an input / output equivalent circuit diagram of external terminals. (Groups A to G). As shown in FIG. 3, an electrostatic protection diode is connected to each external terminal of the semiconductor device 10.

  Next, terminal processing of the external terminals will be described in detail with reference to application examples shown in FIGS.

  FIG. 4 is a diagram showing a PWM application of a current driver dimming method when 10 lights × 6 parallel, LED current 20 [mA], and starting current 8.8 [μA] are set.

  FIG. 5 is a diagram showing an application of the current driver PWM dimming method when 10 lamps × 4 parallel, LED current 20 [mA], and starting current 6 [μA] are set.

  FIG. 6 is a diagram showing an application of the power control PWM dimming method when 10 lamps × 6 parallel and LED current 20 [mA] is set.

  FIG. 7 is a diagram showing an application when the internal REG is not used or is driven at 5 [V] or less.

  Since the TEST terminal (pin 6) is an external terminal for testing, it should be connected to the GND terminal of the semiconductor device 10 during normal use (see FIGS. 4 to 7).

  N. C. The terminal (pin 2) is not particularly specified, but is preferably open.

  The VREG terminal (pin 22) is short-circuited with the VBAT terminal (pin 24) when the semiconductor device 10 is driven from 2.7 to 5.5 [V] from the outside, and a desired voltage is applied to the VREG terminal. Good (see FIG. 7).

  When the FAILSEL terminal (pin 19) and the PWMDRV terminal (pin 11) are fixed at a low level, they may be grounded (see FIGS. 4 to 6). On the other hand, when the FAILSEL terminal and the PWMDRV terminal are fixed at a high level, each may be connected to a VREG terminal or a power supply line of 1.4 [V] or more (see FIG. 7).

  Of the LED1 terminal (12 pin), LED2 terminal (13 pin), LED3 terminal (14 pin), LED4 terminal (16 pin), LED5 terminal (17 pin), LED6 terminal (18 pin) And grounding (see FIG. 5).

  The GND terminals (3 pins, 8 pins, 15 pins, and 20 pins) are connected to each other inside the semiconductor device 10 and may be connected to the ground line of the substrate (see FIGS. 4 to 7).

  In any of the application examples shown in FIGS. 4 to 7, it is desirable to select a capacitor having a small bias variation as a capacitor externally connected to the semiconductor device 10.

  The current driver dimming method shown in FIGS. 4 and 5 and the power control dimming method shown in FIGS. 6 and 7 will be described in detail later.

  FIG. 8 is a table showing the electrical characteristics of the semiconductor device 10 configured as described above. The electrical characteristics shown in FIG. 8 are numerical values at power supply voltage VBAT = 12 [V], high level input voltage RSTB = 2.5 [V], and ambient temperature Ta = + 25 [° C.] unless otherwise specified. Is shown.

  Next, the step-up DC / DC converter of the semiconductor device 10 will be described in detail with reference to FIG. 1 and FIGS.

  First, regarding the external connection of the semiconductor device 10, in particular, details of circuit elements (N-channel field effect transistor N1, coil L1, Schottky barrier diode D1, resistor RCS, capacitors C1, C2) related to the step-up DC / DC converter. Give a simple explanation.

  As shown in FIGS. 4 to 7, the gate of the transistor N1 is connected to the SW terminal (pin 4). The drain of the transistor N1 is connected to one end of the coil L1 and the anode of the diode D1. The other end of the coil L1 is connected to the application end of the battery voltage VBAT. The cathode of the diode D1 is connected to the anode of the LED string that is a load. The source of the transistor N1 is connected to the ground terminal via the resistor RCS. One end (high potential end) of the resistor RCS is connected to the SENSP terminal (pin 5). The other end (low potential end) of the resistor RCS is connected to a SENSN terminal (pin 7). One end of the capacitor C1 is connected to the application end of the battery voltage VBAT. The other end of the capacitor C1 is connected to the ground terminal. One end of the capacitor C2 is connected to the cathode of the diode D1. The other end of the capacitor C2 is connected to the ground terminal.

  Next, the basic operation (DC / DC conversion operation) of the step-up DC / DC converter will be described in detail.

  The transistor N1 is an output power transistor that is on / off controlled according to the terminal voltage of the SW terminal.

  When the transistor N1 is turned on, a switch current flows to the coil L1 toward the ground terminal via the transistor N1, and the electrical energy is stored. Note that if the charge has already been accumulated in the capacitor C2 during the ON period of the transistor N1, the current from the capacitor C2 flows through the LED string as the load. At this time, since the anode potential of the diode D1 is lowered to almost the ground potential via the transistor N1, the diode D1 is in a reverse bias state, and no current flows from the capacitor C2 toward the transistor N1.

  On the other hand, when the transistor N1 is turned off, the electric energy stored therein is released by the counter electromotive voltage generated in the coil L1. At this time, since the diode D1 is in the forward bias state, the current flowing through the diode D1 flows into the LED string as a load, and also flows into the ground terminal via the capacitor C2, thereby charging the capacitor C2. . By repeating the above operation, the LED array that is a load is boosted by the capacitor C2 and supplied with the smoothed DC output.

  As described above, the semiconductor device 10 of this embodiment drives the coil L1 that is an energy storage element by the on / off control of the transistor N1, thereby boosting the battery voltage VBAT and generating the output voltage VOUT. It functions as a component of the circuit.

  Next, the output feedback control of the peak current mode control method will be described in detail.

  The error amplifier 107 includes a minimum value of the LED terminal voltages V1 to V6 applied to the first to sixth inverting input terminals (−) and a predetermined LED control voltage VLED input to the non-inverting input terminal (+). And an error voltage Verr is generated. That is, the voltage level of the error voltage Verr becomes higher as the output voltage VOUT is lower than the target set value.

  The PWM comparator 108 has a lower one of the error voltage Verr applied to the first inverting input terminal (−) and the soft start voltage Vss applied to the second inverting input terminal (−), and the non-inverting input terminal (+ ) Applied to the slope voltage Vslp (addition voltage of the triangular wave voltage generated by the oscillator unit 110 and the current detection voltage generated by the current detection unit 112 (current detection signal generated by the resistor RCS)). Thus, a comparison signal having a duty ratio corresponding to the comparison result is generated. That is, the logic of the comparison signal is low level if the error voltage Verr (or soft start voltage Vss) is higher than the slope voltage Vslp, and high level if it is low. The oscillator unit 110 prevents subharmonic oscillation when generating the triangular wave voltage.

  Note that the on-duty of the comparison signal during the steady operation (ratio of the on-period of the transistor N1 in the unit period) varies depending on the relative level of the error voltage Verr and the slope voltage Vslp.

  The control unit 113 is a unit that receives the above comparison signal, generates a set signal and a reset signal for the SR flip-flop 114, and performs switching control of the transistor N1. Specifically, a high level is output to the gate of the transistor N1 during the period in which the comparison signal is at a low level, and conversely, during the period in which the comparison signal is at a high level, A set signal and a reset signal are generated so as to output a low level to the gate. Further, the control unit 113 monitors various protection signals built in the semiconductor device 10 and immediately stops the switching operation of the transistor N1 when it is determined that some abnormality has occurred.

  Thus, in the DC / DC converter of the peak current mode control system, based on the monitoring result of the switch current flowing in the transistor N1, as well as the monitoring result of the LED terminal voltages V1 to V6 (and thus the output voltage VOUT), Drive control of the transistor N1 is performed. Therefore, with the semiconductor device 10 of the present embodiment, the transistor N1 can be directly driven and controlled according to the monitoring result of the switch current flowing through the transistor N1, even if the error voltage Verr cannot follow the steep load fluctuation. Therefore, it is possible to effectively suppress fluctuations in the output voltage VOUT. That is, in the semiconductor device 10 of the present embodiment, it is not necessary to increase the capacity of the capacitor C2, and therefore it is possible to avoid unnecessary cost increase and increase in the size of the capacitor C2.

  Next, soft start control of the step-up DC / DC converter will be described.

  Immediately after the semiconductor device 10 is activated, the error voltage Verr becomes extremely large because the output voltage VOUT is zero. Therefore, when the error voltage Verr and the slope voltage Vslp are compared with each other, the duty of the comparison signal becomes excessive, and an excessive current flows through the LED array and the coil L1 that are loads.

  Therefore, in the semiconductor device 10 of this embodiment, the soft start voltage Vss is input to the PWM comparator 108 separately from the error voltage Verr, and depends on the error voltage Verr when the soft start voltage Vss is lower than the error voltage Verr. Instead, the duty of the PWM signal is determined in accordance with the comparison result between the lower soft start voltage Vss and the slope voltage Vslp.

  In the semiconductor device 10 of the present embodiment, the soft start circuit 109 is configured to generate a soft start voltage Vss that starts to rise gradually after the device is started by flowing a predetermined constant current into the capacitor. Yes.

  Thus, with the configuration including the soft start circuit 109, it is possible to prevent an excessive current to the load and the coil L1 when the apparatus is started up.

  In the semiconductor device 10 of the present embodiment, after the RSTB terminal (21 pin) is changed from the low level to the high level, the PWMPOW terminal (23 pin) is changed from the low level to the high level. ms]), the soft start function is valid. After that, even if the PWMPOW terminal is changed from low level to high level, the soft start function is not valid. When the high level section of the PWMPOW terminal is within 1 [ms], the soft start function is disabled when a pulse is input three times or more to the PWMPOW terminal. Also, the soft start function is disabled by dropping the RSTB terminal from the high level to the low level. Such soft start function enable / disable control will be described in detail later.

  Next, the FAILSEL terminal (19 pins) will be described.

  The semiconductor device 10 according to the present embodiment includes various abnormality protection units, and when an abnormal state occurs, the boosting operation is stopped by the above-described protection function to avoid element destruction and heat generation / ignition. At that time, a method for stopping the boosting operation by the protection function can be selected by the FAILSEL terminal. The protection functions to be controlled are overvoltage protection, SBD disconnection protection, thermal shutdown, LED terminal overvoltage protection, and overcurrent protection.

  FIG. 9 is a diagram for explaining the operation of the FAILSEL terminal.

  As shown in the upper part of FIG. 9, when the FAILSEL terminal is at a high level, when the protection function is activated, the boosting operation is stopped, and thereafter, the stopped state is maintained. Note that if the RSTB terminal is set to the low level, the stop state is released, and the boosting operation is resumed.

  On the other hand, as shown in the lower part of FIG. 9, when the FAILSEL terminal is at a low level, when the protection function is activated, the boosting operation is temporarily stopped. However, when no abnormality is detected, the boosting operation is automatically resumed. Will be restored. That is, the semiconductor device 10 does not continue to hold the boost operation stop state.

  Further, as shown in FIG. 9, the protection function is disabled during a predetermined period (about 1 [ms]) after power-on. As a result, it is possible to prevent the boosting operation from being stopped due to erroneous detection of a transient current or insufficient boosting that occurs when the semiconductor device 10 is started up as an abnormal state, and the semiconductor device 10 being unable to start up.

  When PWM adjustment of LED luminance is performed using the PWMDRV terminal (that is, when the current driver dimming method is adopted), the abnormal latch selection function of the FAILSEL terminal cannot be used.

  When PWM adjustment of LED brightness is performed using the PWMPOW terminal (that is, when the power control dimming method is adopted), when the LED is turned off for 10 [ms] or more, it is turned off using the PWMPOW terminal. Instead of providing a period, it is desirable to provide an off period using the RSTB terminal. By performing such control, it is possible to prevent the boost operation from being stopped due to unintentional overcurrent protection after the above-described off period ends (compare the upper and lower stages in FIG. 10). See).

  Next, external SBD disconnection protection and overvoltage protection will be described.

  The semiconductor device 10 incorporates an over-boosting protection function unit (SBD disconnection protection unit 105) due to an external SBD disconnection and an overvoltage protection function unit (OVP unit 106). They detect the terminal voltage of the VDET terminal (1 pin) or its divided voltage, and send an abnormality detection signal to the control unit 113 so as to stop the transistor N1 in the event of an abnormality. Details are as follows.

  With regard to external SBD disconnection protection, when the connection between the DC / DC output terminal (output voltage VOUT extraction terminal) and the diode D1 is open, over-boosting may occur and the coil L1 and the transistor N1 may be destroyed. is there. Therefore, when the output voltage VOUT becomes 0.1 [V] or less, the external SBD disconnection protection is activated and the transistor N1 is turned off to prevent the coil L1 and the transistor N1 from being destroyed. Further, the semiconductor device 10 is switched from the operating state to the non-operating state, so that no current flows through the coil L1.

  On the other hand, for overvoltage protection, when the connection between the DC / DC output terminal and the load (LED string) is opened, an over boost occurs and a voltage exceeding the absolute maximum rating is applied to the transistor N1 or VDET terminal, The transistor N1 and the semiconductor device 10 may be destroyed. Therefore, when an abnormality occurs such that the VDET terminal becomes equal to or higher than the predetermined detection voltage Vth1, overvoltage protection is activated, and the transistor N1 is turned off to prevent the transistor N1 and the semiconductor device 10 from being destroyed. At this time, the semiconductor device 10 is switched from the operating state to the non-operating state, and the output voltage VOUT decreases slowly. When the output voltage VOUT drops below the predetermined detection voltage Vth2 (where Vth2 <Vth1), the output voltage VOUT is boosted again to the detection voltage, and this operation is repeated unless the application abnormality is recovered.

  Next, thermal shutdown will be described.

  The semiconductor device 10 includes a thermal shutdown function unit (TSD unit 102). The thermal shutdown operates at 175 [° C.] or higher, and the semiconductor device 10 is switched from the operating state to the non-operating state. In the non-operating state, unlike the case where the RSTB terminal is at the low level, the internal reset of the semiconductor device 10 is not performed. That is, even if the thermal shutdown function is activated, various settings related to the RSTB terminal (soft start function enable / disable setting, FAILSEL terminal abnormal latch selection setting, current driver 123 column number selection setting, and PWMDRV terminal are low. Any start-up current setting at the time of level is maintained.

  Next, overcurrent protection will be described.

  When overcurrent flows through the current detection resistor RCS connected between the source of the transistor N1 and the ground terminal, and the terminal voltage of the SENSP terminal (pin 5) becomes equal to or higher than the detection voltage, the overcurrent protection is activated and the voltage is increased. Without stopping the operation, the on-duty of the transistor N1 is reduced to prevent overcurrent exceeding the detection current. Since the current detector 112 of the semiconductor device 10 detects the peak current, no current exceeding the overcurrent set value flows. Further, it is possible to freely set the overcurrent detection value by changing the overcurrent detection resistor RCS.

  Next, a method for deriving the resistance value of the resistor RCS will be described.

  The resistance value of the resistor RCS is calculated by dividing the overcurrent detection voltage by the overcurrent setting value. At this time, after determining the overcurrent set value based on the current value necessary for normal operation, the resistance value of the resistor RCS can be derived by using the minimum value in consideration of the variation in the overcurrent detection voltage. That's fine. For example, when the ideal value of the overcurrent detection voltage is 100 [mV], the minimum value is 70 [mV], the maximum value is 130 [mV], and the overcurrent set value is 1 [A], the resistance of the resistor RCS The value is calculated as 70 [mΩ] (= 70 [mV] / 1 [A]). When such a resistance value is set, the variation width of the current is 1 [A] to 1.86 [A] (= 130 [mV] / 70 [mΩ]).

  Next, estimation of a current value necessary for normal operation will be described.

  Since the current detection unit 112 of the semiconductor device 10 detects the peak current, it is necessary to estimate the peak current Ipeak flowing in the coil L1 according to the use conditions of the semiconductor device 10. Here, the power supply voltage VIN of the coil L1, the inductance value L of the coil L1, the switching frequency fsw (minimum value: 0.8 [MHz], ideal value: 1 [MHz], maximum value: 1.2 [MHz]), When the output voltage VOUT, the total LED current IOUT, and the efficiency eff are used, the peak current Ipeak of the coil L1, the average current Iave of the coil L1, and the switching time Ton are expressed by the following equations (1a) and (1b), respectively. , (1c).

  Moreover, since the peak current detected by the current detection unit 112 varies depending on whether or not there is DC superimposition, the determination based on the following equations (2a) and (2b) is performed.

  For example, when VIN = 6.0 [V], L = 4.7 [μH], fsw = 1 [MHz], VOUT = 39 [V], IOUT = 80 [mA], eff = 85 [%] From the above equations (1a), (1b), and (1c), Ipeak = 1.08 [A], Iave = 0.61 [A], and Ton = 0.90 [μs] are calculated. From the equation (2a), the peak current = 1.15 [A] is calculated.

  On the other hand, when VIN = 12.0 [V], L = 4.7 [μH], fsw = 1 [MHz], VOUT = 39 [V], IOUT = 80 [mA], eff = 85 [%] From the above equations (1a), (1b), and (1c), Ipeak = 1.77 [A], Iave = 0.31 [A], Ton = 0.41 [μs] From the equation (2b), peak current = 1.05 [A] is calculated.

  However, if the peak current is set to a very large value, output overshoot occurs, and in the worst case, the semiconductor device 10 is destroyed.

  Next, the operation at the time of an application failure will be described.

  When one LED or one row of LEDs is open during operation, if the FAILSEL terminal is at a low level, the opened LED row is not lit, but the other LED rows are lit normally. At this time, since the LED terminal voltage becomes 0 [V], the output voltage VOUT is boosted to 44.7 [V] which is the overvoltage protection voltage, or the LED terminal voltage is the overvoltage protection voltage. The voltage is boosted until it reaches 5 [V] or until it is limited by the overcurrent limit. On the other hand, if the FAILSEL terminal is at a high level, when the LEDs are opened, the boosting operation is stopped and all the LEDs are turned off.

  When a plurality of LEDs are short-circuited, if the FAILSEL terminal is at a low level, all LEDs are lit as usual unless the LED terminal voltage becomes 11.5 [V] which is the overvoltage protection voltage or higher. When the LED terminal voltage becomes 11.5 [V] or more, only the shorted column is normally lit, and the other columns are darkened or turned off due to the decrease in the LED current. On the other hand, if the FAILSEL terminal is at a high level, when the LED terminal voltage becomes 11.5 [V] or higher, the boosting operation is stopped and all the LEDs are turned off.

  When the Schottky barrier diode D1 is disconnected, all LEDs are not lit regardless of the voltage level of the FAILSEL terminal. Further, since the boosting operation is stopped by the SBD disconnection protection function, the semiconductor device 10 and the transistor N1 are not destroyed.

  When the overcurrent detection resistor RCS is removed, all LEDs are not lit regardless of the voltage level of the FAILSEL terminal. This is because a resistance of 100 [kΩ] is inserted between the SENSP terminal and the SENSN terminal, and the overcurrent protection is immediately applied so that the LED current cannot flow.

  Next, the input timing of the control signals (RSTB signal, PWMPOW signal, PWMDRV signal) will be described with reference to FIG.

  FIG. 11 is a timing chart of the control signal.

  When a control signal such as an RSTB signal, a PWMPOW signal, or a PWMDRV signal is input in a state where the rising of the power supply voltage VBAT is not completed, the following points should be noted.

  First, it is desirable to input each control signal after the power supply voltage VBAT exceeds 2.7 [V].

  Second, it is desirable to input each control signal after the power supply voltage VBAT exceeds the high level voltage (5 [V]) of each control signal.

  Third, when a high level voltage is input to the RSTB signal and the PWMPOW signal during the rise of the power supply voltage VBAT, the rise time from the power supply voltage VBAT of 2.7 [V] to the stable voltage is at least 100 [μs]. Is desirable.

  There is no timing limitation between the control signals of the RSTB signal, the PWMPOW signal, and the PWMDRV signal.

  Further, when the voltage level of each control signal is higher than the power supply voltage VBAT, it is intended toward the supply line of the power supply voltage VBAT via the electrostatic protection diode on the power supply voltage VBAT side internally connected to each terminal. Current may flow, causing malfunction or device destruction. In order to avoid such a state, it is desirable to limit the current by inserting a resistor of about 10 [kΩ] into the signal line as shown in FIG. Further, as shown in FIG. 1, it is desirable to provide an internal pull-down resistor as appropriate for each terminal.

  Next, the column number selection method of the current driver 123 will be described.

  When it is desired to reduce the number of columns of the current driver 123, unnecessary LED1 to LED6 terminals can be unselected by connecting them to the ground terminal. When using 4 rows, etc., it can be dealt with by connecting 2 unnecessary rows to the ground terminal.

  In the semiconductor device 10 of this embodiment, the terminal voltage (5 [V]) of the RSTB terminal is used as the power source of the LED terminal detection unit 116 that determines the above. By adopting such a configuration, when the power control dimming method is employed, the LED terminal detection unit 116 is connected to the terminal of the RSTB terminal even when the operation of the REG unit 101 is controlled to be turned on / off. It becomes possible to always hold the detection result of the LED terminal using the voltage.

  Regardless of the logic of the PWMPOW signal and the PWMDRV signal, the selection of the LED terminal is determined, and once it is determined that the terminal is necessary, it is not determined that the LED string is unnecessary even if it is connected to the ground terminal. This information can be reset by setting the RSTB terminal to 0 [V]. In addition, since the power supply current which flows into an RSTB terminal increases by connecting an unnecessary LED terminal to a ground end, attention should be paid to the current capacity connected to the RSTB terminal. FIG. 13 is a table showing an example of current consumption when RSTV = 5 [V]. These application examples are as shown in FIG.

  Next, start-up control and selection of LED current will be described with reference to FIG.

  The semiconductor device 10 can control the power of the semiconductor device 10 by using the RSTB terminal, and the semiconductor device 10 can be controlled by setting the RSTB terminal to 0.2 [V] or less (RSTB = “0”). Power off can be forced. In addition, when the PWMPOW terminal is 1.4 [V] or higher (PWMPOW = “1”) and the RSTB terminal is 2.25 [V] or higher (RSTB = “1”), the semiconductor device 10 is powered on.

  When RSTB = PWMPOW = “1”, if PWMDRV = “1”, the first current ISETH is selected as the LED current ILED, and if PWMDRV = “0”, the second current ISETL is selected as the LED current. . Note that the startup current when PWMDRV = “0” is turned off at the second rise of PWMDRV, and thereafter, is set to 0 [mA]. By setting RSTB once to a low level and switching it to a high level, the starting current can be supplied again.

  That is, when the current driver dimming method is adopted as the LED luminance dimming method, the PWMPOV terminal is fixed to “1” and the PWMDRV terminal is driven by “0” / “1”. When the power control dimming method is adopted, the PWMDRV terminal is fixed to “1” and the PWMPOW terminal is driven at “0” / “1”.

  Next, a start-up operation and a PWM operation when the PWMPOW terminal is used for PWM control of LED luminance (that is, when a power control dimming method is adopted) will be described.

  When the PWMPOW terminal is used for LED luminance PWM control, the RSTB terminal and the PWMDRV terminal are raised from a low level to a high level, and then a pulse voltage that is PWM-driven may be input to the PWMPOW terminal. There is no restriction on the voltage application order of the RSTB terminal and the PWMDRV terminal.

  In addition, in order to support PWM drive with an on-time shorter than the soft start time (1 [ms]), if a high level is input to the PWMPOW terminal three times or more, the soft start function is invalidated and high speed drive is supported. Make it possible. Once the soft start function is disabled, the soft start function is not disabled until the RSTB terminal is lowered to a low level.

  Therefore, when using the PWMPOW terminal to control the LED to turn on, turn off, turn on, etc., after turning off the LED with the PWMPOW terminal low level, the LED is turned on again with the PWMPOW terminal high level. In that case, it starts without soft start. As a result, the peak current Ipeak of the coil L1 changes due to the discharge of the output capacitor C2, but as shown in FIG. 15, the peak current Ipeak may flow to the overcurrent limit value.

  On the other hand, as shown in FIG. 16, by setting the RSTB terminal to a low level, when the LED is turned off, the soft start function becomes effective again, and the peak current Ipeak of the coil L1 can be suppressed. Become. Therefore, when the LED is turned off, it is desirable to provide an off period using the RSTB terminal, instead of providing an off period using the PWMPOW terminal.

  Next, a start-up operation and a PWM operation when the PWMDRV terminal is used for PWM control of LED luminance (that is, when a current driver dimming method is adopted) will be described.

  When the PWMDRV terminal is used for PWM control of LED brightness, the pulse voltage that is PWM-driven may be input to the PWMDRV terminal after the RSTB terminal and the PWMPOW terminal are raised from the low level to the high level. There is no restriction on the voltage application order of the RSTB terminal and the PWMPOW terminal.

  As shown in FIG. 17, after the RSTB terminal and the PWMPOW terminal are raised from the low level to the high level, there may be a situation in which the pulse voltage is not input to the PWMDRV terminal and the low level voltage is input. In such a case, if the current driver 123 is configured such that the LED current ILED is not drawn at all while the PWMDRV terminal is at a low level, the DC / DC converter cannot perform a stable boosting operation.

  In order to avoid such a state, as shown in FIG. 17, in the semiconductor device 10 of the present embodiment, when the semiconductor device 10 is started, a predetermined start-up current is applied to each LED terminal even during a period when the PWMDRV terminal is at a low level. By pulling from, the boosting operation is stabilized. In addition, the current value of the starting current can be arbitrarily set by a resistance value (RISETL) connected to the ISETL terminal. Therefore, when the semiconductor device 10 is started, the LED current ILED is set to the first current ISETH (for example, 20 [mA]) set by the first current setting unit 118 and the second current set by the second current setting unit 119. PWM driving is performed between the current ISETL (for example, 100 [μA]).

  On the other hand, after the semiconductor device 10 is normally activated, the above-described activation current becomes unnecessary when the LED brightness is adjusted by PWM. Therefore, as shown in FIG. 17, the starting current is automatically set to 0 [mA] at the second rise of the PWMDRV terminal. Therefore, during the steady operation of the semiconductor device 10, the LED current ILED is PWM driven between the first current ISETH (for example, 20 [mA]) set by the first current setting unit 118 and 0 [mA]. It becomes a shape.

  Note that only the behavior of the starting current in the current driver 123 is depicted at the bottom of FIG.

  When the LED is turned on, turned off, turned on, etc. using the PWMDRV terminal, the LED is turned off with the PWMDRV terminal at a high level and then the LED is turned on again. At that time, since the soft start period has expired, it starts without soft start. As a result, the peak current Ipeak of the coil L1 changes due to the discharge of the output capacitor C2, but as shown in FIG. 18, the peak current Ipeak may flow to the overcurrent limit value.

  On the other hand, as shown in FIG. 19, when the LED is turned off by setting the RSTB terminal to the low level, the soft start function becomes effective again, and the peak current Ipeak of the coil L1 can be suppressed. Become. Therefore, when the LED is turned off, it is desirable to provide an off period using the RSTB terminal instead of providing an off period using the PWMDRV terminal.

  Next, the setting range of the LED current ILED will be described.

  For the LED current ILED, a normal current and a starting current can be set respectively. A normal current is set by a resistor (RISETH) connected to the ISETH terminal (pin 9), and a starting current is set by a resistor (RISETL) connected to the ISETL terminal (pin 10). Note that the normal current and the startup current are calculated based on the following equations (3a) and (3b), respectively.

  The normal current setting range is 10 to 25 [mA], and the starting current setting range is OFF setting or 1 to 100 [μA]. By connecting the ISETL terminal to the VREG terminal, the starting current can be set to OFF. The LED current ILED at the time of off setting is only a leakage current (maximum: 1 [μA]).

  Next, LED brightness control will be described.

  By applying a PWM pulse voltage to the PWMPOW terminal or the PWMDRV terminal, the brightness of the LED can be adjusted by PWM. That is, in the semiconductor device 10 of the present embodiment, two techniques can be used as the LED brightness PWM adjustment method. One is a PWM dimming method (current driver dimming method described above) that adjusts the LED luminance by performing on / off control of the LED current ILED using the current driver 12, and the other is a semiconductor. This is PWM dimming (the power control dimming method described above) that adjusts the LED brightness by performing on / off control of each part of the device 10. The characteristics of these two types of PWM dimming are shown in FIG. Any PWM adjustment method may be selected according to the application. For example, if importance is attached to the efficiency at low luminance that affects the battery life, a power control dimming method may be employed. Further, if importance is attached to LED current variation during PWM luminance adjustment, a current driver dimming method may be employed.

  The current driver dimming method is realized by applying a PWM signal to the PWMDRV terminal as shown in FIGS. In the high level section of the PWMDRV terminal, the first current ISETH set by the ISETH terminal is selected as the LED current ILED, and in the low level section, the LED current ILED is turned off. That is, the average value of the LED current ILED increases in proportion to the duty of the PWM signal applied to the PWMDRV terminal.

  Since this PWM dimming method uses current control by the current driver 123, there is little current variation at the time of PWM brightness adjustment, and a minimum duty of 1 [% when the ON time is 50 [μs] (PWM frequency 200 [Hz]). ]) Is possible. It should be noted that the ON time less than 50 [μs] and the OFF time less than 50 [μs] have a large influence at the time of current switching, so it is desirable not to use them for adjusting the brightness of the LED. The standard PWM frequency is 100 [Hz] to 10 [kHz]. When the RSTB terminal is lowered from the high level to the low level, the starting current becomes effective as described above. Therefore, after the RSTB terminal is raised from the low level to the high level, the PWM signal rises up to two times. PWM drive is performed between the first current ISETH and the starting current (second current ISETL).

  On the other hand, the power control dimming method is realized by applying a PWM signal to the PWMPOW terminal as shown in FIGS. In the high level section of the PWMPOW terminal, the current selected by the logic of the PWMDRV terminal is set as the LED current ILED, and in the low level section, the LED current ILED is turned off. That is, the average value of the LED current ILED increases in proportion to the duty of the PWM signal applied to the PWMPOW terminal.

  Since this PWM dimming method can power off the semiconductor device 10 when it is turned off, current consumption can be suppressed, it is highly efficient, and the minimum duty when the on time is 50 [μs] (PWM frequency 200 [Hz]). 1 [%]) brightness adjustment is possible. It should be noted that the ON time less than 50 [μs] and the OFF time less than 50 [μs] are preferably not used for brightness adjustment because of the large influence at the time of power on / off. The standard PWM frequency is 100 [Hz] to 1 [kHz]. Also, the RSTB terminal and the PWMPOW terminal cannot be PWM controlled simultaneously. After setting the RSTB terminal to the high level, the PWM control may be performed only by the PWMPOW terminal.

  Note that, regardless of which of the current driver dimming method and the power control dimming method is used, the current value of the normal current set by the resistor RISETH is a guaranteed set current in which the luminance variation of the LED is guaranteed. It is desirable to set a value (for example, 20 [mA]). By adopting such a configuration, the current region in which the LED luminance variation is not guaranteed is not used, and therefore, it is not necessary to consider the LED luminance variation even when realizing the LED luminance adjustment 1 [%]. LED sorting becomes unnecessary.

  Next, separation of the IC power source and the coil power source will be described.

  The semiconductor device 10 can operate separately from the power supply to the internal circuit and the coil power supply. Applications include reduction of power consumption of the semiconductor device 10 and application of a voltage exceeding the rating 22 [V] of the semiconductor device 10. The application is shown in FIG. A high voltage source (7 to 28 [V]) supplied from an adapter or the like is connected to the coil power supply. Next, a power supply different from the coil power supply is connected as a power supply for the semiconductor device 10. Under the condition that 2.7 to 5.5 [V] is input to the VBAT terminal of the semiconductor device 10, the VBAT terminal and the VREG terminal may be shorted outside the semiconductor device 10 as shown in FIG. Even if the power supply of the semiconductor device 10 is 0 [V] in a state where the coil power supply is applied, there is no problem in use. Even when the power supply of the semiconductor device 10 is set to 0 [V], a power-off pull-down resistor that cuts off the leakage path from the coil power supply is arranged inside the semiconductor device 10 and cuts off the leakage path. is there. Further, there is no order for starting up the coil power supply and the power supply of the semiconductor device 10.

  Next, the layout pattern of the semiconductor device 10 will be described with reference to FIGS.

  FIG. 22 is a diagram showing a layout of the semiconductor device 10, and FIGS. 23 and 24 are diagrams showing examples of actual layout patterns. FIG. 23 shows a layout pattern on the front surface of the substrate, and FIG. 24 shows a layout pattern on the back surface of the substrate. FIG. 24 shows a state where the layout pattern on the back surface side is transmitted from the front surface side of the substrate.

  The layout pattern is very important for fully exploiting the performance of the semiconductor device 10. Since characteristics such as efficiency and ripple vary greatly depending on the layout pattern, sufficient attention must be paid.

  The input bypass capacitor C3 is preferably connected in the immediate vicinity of the coil L1. It is desirable to wire the power supply line with a low resistance from the input bypass capacitor C3 to the VBAT terminal. Thereby, the input voltage ripple of the semiconductor device 10 can be reduced.

  It is desirable that the smoothing capacitor C4 of the REG unit 101 be connected immediately between the VREG terminal and the GND terminal. The diode D1 is desirably connected most recently between the coil L1 and the transistor N1. It is desirable that the output capacitor C2 be connected immediately between the cathode of the diode D1 and one end (GND side) of the input bypass capacitor C3. Thereby, output voltage ripple can be reduced.

  In particular, it is desirable to perform wiring layout so that the distance between the connection between the coil L1 to which the pulse waveform is applied and the diode D1 (or the distance between the connection between the coil L1 and the transistor N1) is shortened with the highest priority. That is, it is desirable that the connection distance between the coil L1 and the diode D1 is shorter than the connection distance between the diode D1 and the output capacitor C2. In the case where the diode D1 and the transistor N1 are built in the semiconductor device 10, the connection node between the anode of the diode D1 and the drain of the transistor N1 and the cathode of the diode D1 serve as first and second external terminals, respectively. It will be in the form of being pulled out. In this case, it is desirable that the connection distance between the coil L1 and the first external terminal be shorter than the connection distance between the second external terminal and the output capacitor C2.

  The transistor N1 is preferably connected in the immediate vicinity of the SW terminal. It is desirable that the coil L1, the transistor N1, and the resistor RCS are wired close to each other and with a low resistance. The wiring to the SENSP terminal is preferably connected not from the transistor N1 side but from the resistor RCS side. This is because wiring from the transistor N1 side may reduce the overcurrent value.

  One end (GND side) of the resistor RCS is desirably wired independently to the SENSN terminal. Wiring from the resistor RCS to the ground terminal should not be performed between the resistor RCS and the SENSN terminal. Further, it is desirable that the GND wiring is singly wired up to one end (GND side) of the capacitor C2. This is because if another element is connected to one end (GND side) of the capacitor C2, there is a possibility that the current drive performance may be limited due to the influence of noise.

  It is desirable that the resistor RISETH for setting the LED current is connected immediately to the ISETH terminal. Since there is a possibility of oscillation when a capacitor is attached to the ISETH terminal, care should be taken not to attach a capacitor. Further, it is desirable that one end (GND side) of the resistor RISETH is connected to the ground end alone.

  If these pins are not directly connected in the immediate vicinity of the semiconductor device 10, the performance of the semiconductor device 10 is affected and current drive performance may be limited. The wiring to the coil L1 desirably has a small resistance component in order to reduce power consumption and increase the overall efficiency.

  Further, when a voltage fluctuation is applied to the output capacitor C2, as shown in FIG. 25, the substrate may be shaken due to the expansion and contraction of the element, and a noise may be generated. In particular, when the capacitance value of the output capacitor C2 is large, the element size becomes large, and it is easy to generate noise. In order to reduce such noise, it is desirable to reduce the element size of the output capacitor C2 as much as possible. For example, as shown in FIG. 26, capacitors C2a and C2b having a capacitance value half the desired value are provided. It is possible to connect in parallel. However, as shown in FIG. 26, if the capacitors C2a and C2b are arranged in the same direction, resonance may occur in both vibrations, which may promote sound. Therefore, as shown in FIG. 27, by arranging the capacitors C2a and C2b in different directions, it is possible to avoid resonance between them and reduce noise. In addition, as shown in FIG. 28, it is possible to reduce noise by disposing the capacitor C2a on the front surface side of the substrate and disposing the capacitor C2b on the back surface side of the substrate.

  In particular, the above configuration is effective when the drive frequency of the PWM signal is in the human audible range (generally 20 [Hz] to 20 [kHz]).

  Further, the above configuration is effective not only for the output capacitor C2 but also as a countermeasure against noise from the input bypass capacitors C1 and C3.

  Next, the internal configuration of the REG unit 101 will be described with reference to FIG.

  FIG. 29 is a block diagram showing an internal configuration of the REG unit 101.

  As shown in the figure, the REG unit 101 includes a first level shifter 101b and a second level shifter 101c in addition to the internal voltage generation circuit 101a that generates the internal voltage VIN.

  The first level shifter 101b receives an input of the terminal voltage (coil power source) of the VBAT terminal, and performs a level shift of the PWM signal (0-1.4 [V]) input from the PWMPOW terminal, whereby an internal voltage generation circuit This is means for generating a first enable signal EN1 (0-20 [V]) for performing on / off control of 101a.

  The second level shifter 101c receives the input of the terminal voltage (IC power supply) of the VREG terminal and performs level shift of the PWM signal input from the PWMPOW terminal, thereby turning on / off the internal circuit (circuits other than the REG unit 101). This is means for generating a second enable signal EN2 (0-5 [V]) for performing off control.

  By incorporating the REG unit 101 having the above-described configuration, the semiconductor device 10 of the present embodiment can be used based on the PWM signal input from the PWMPOW terminal, whether the coil power supply and the IC power supply are separated or not. The power control dimming described above can be realized.

  Next, advantages of using a white LED as a backlight of a liquid crystal display mounted on a notebook computer will be described.

  The first advantage is that, unlike a cold cathode fluorescent tube (CCFL), a white LED is a surface-mounted chip, so that the panel can be made thinner, lighter, and improved in vibration and shock resistance. . A second advantage is that since the luminance adjustment range is wide, battery saving can be achieved by reducing the luminance in a dark environment. The third advantage is that it is possible to respond to the RoHS command by Hg-less. A fourth advantage is that a high voltage having an effective value of 1000 [Vrms] is not required, and acquisition of each safety standard is facilitated.

  Along with the use of LEDs for such backlights, there is a demand for LED drivers that drive the backlights to further extend battery life and darken the screen to reduce power consumption. There is a demand for the ability to adjust the brightness to the limit of 1% where the panel picture can be seen. Note that it is difficult for the cold cathode fluorescent tube (CCFL) to adjust the brightness to 10% or less due to its characteristics (see the comparison between the square mark (LED) and the triangular mark (CCFL) in FIG. 30). .

  Therefore, the semiconductor device 10 according to the present embodiment has a configuration capable of realizing an adjustment range up to a luminance of 1 [%] in performing the above minimum luminance setting, and further realizing high efficiency even at a low luminance setting. Has been. Below, the structure is demonstrated in detail.

  First, the LED driving method that should be adopted in order to achieve the above target will be examined. A problem in examining this is how to deal with LED luminance variations. As shown in FIG. 31, in the current range over the guaranteed set current value (for example, 20 [mA]), the luminance variation of the LED is guaranteed. In this case, the luminance variation of the LED is not guaranteed, and the luminance variation becomes easy to understand. Therefore, it is necessary to drive the LED with a guaranteed set current value.

  Therefore, in the semiconductor device 10 of the present embodiment, as shown in FIG. 32, the average current adjustment (PWM) is performed based on the ratio of the guaranteed set current value (20 [mA]) and off (0 [mA]) of the LED. Brightness adjustment). By adopting such a configuration, since the current region below the guaranteed current value is not used, it is not necessary to select the LEDs.

  Next, a problem in realizing luminance adjustment 1 [%] by the PWM method will be examined. In LED driver ICs for mobile phones, when PWM dimming of LED brightness by the power control dimming method is performed, as shown in FIG. Fast start-up that caused an increase in peak current each time the signal was turned on was suppressed (for example, corresponding to a start time of 300 [μs] and a luminance of 6 [%]). Further, the rise time of the LED current is the same every time the PWM signal is turned on, and corresponds to the reaction time of the DC / DC converter (for example, the reaction time is 150 [μs] and the luminance is 3 [%]). ) Was set to a condition that slows the startup time of the current driver.

  Therefore, in order to realize the LED current start-up time 50 [μs] (corresponding to luminance 1 [%]), the start-up time (300 [μs]) delayed by the soft start function and the reaction of the DC / DC converter Since time (150 [μs]) becomes a bottleneck, it is necessary to clear these two issues.

  First, a measure for realizing a reduction in the startup time of the LED current is examined.

  As described above, the problem in realizing the reduction in the LED current start-up time is that the start-up time by the soft start function is 300 [μs] (corresponding to a luminance of 6 [%]), which is 50 [μs. ] (Corresponding to luminance 1 [%]).

  As an approach to shortening the start-up time, it is conceivable to shorten the set value of the start-up time itself, but with this measure, the peak of the input current at the first start-up becomes large (see point A in FIG. 34). ). Although it is conceivable to reduce the input current by adjusting the overcurrent limit, with this measure, the LED current may not reach the target value under the condition that the battery voltage is low (in FIG. 34). (See point B).

  Therefore, in the semiconductor device 10 of the present embodiment, at the first startup, the soft start is performed with the conventional startup time of 300 [μs], and after the second time, the soft start is canceled and the startup time is set to zero. It is said that. By adopting such a configuration, it is possible to shorten the startup time for the second and subsequent times while appropriately suppressing the peak current at the first startup.

  However, as described above, another problem in reducing the LED current start-up time is that the reaction time of the DC / DC converter is 150 [μs] (see FIG. 35). (Corresponding to luminance 3 [%]) is slower than the target value 50 [μs] (corresponding to luminance 1 [%]). Unless this is eliminated, the target LED current rise time is achieved. I can't.

  As an approach for shortening the reaction time of the DC / DC converter, in order to shorten the rise time of the output voltage of the error amplifier constituting the DC / DC converter, a phase compensation circuit connected to the output terminal of the error amplifier is used. Although it is conceivable to reduce the CR time constant, in this measure, it is necessary to change the output capacitor from 2.2 [μF] to 20 [μF] in order to prevent system oscillation, and the 50 [V] breakdown voltage In addition, it is difficult to mount a 20 [μF] output capacitor on a thin panel from the viewpoint of installation area.

  Therefore, in the semiconductor device 10 according to the present embodiment, the previous value of the error output is increased until the LED current rises from the viewpoint of reducing the amount of change necessary for the error output rise instead of making the error output rise early. By maintaining (error output before the PWM signal is turned off), the LED current startup time is shortened.

  Specifically, as shown in FIG. 36, the semiconductor device 10 of the present embodiment includes a detection circuit 124 that detects the rise of the LED current, and the rise of the LED current after the PWM signal is set to the low level. The previous value holding circuit 125 for generating a timing signal for holding the previous value of the error output (the switch 126 is turned off) and the output terminal of the error amplifier 107 are connected, and according to the timing signal from the holding circuit 125 And a switch 126 that is on / off controlled.

  The detection circuit 124 includes a configuration for monitoring the rise of the LED current and a configuration for monitoring whether or not the LED terminal voltage has reached a predetermined threshold value. Either one of the configurations is adopted. Alternatively, both configurations may be adopted.

  In this way, if the phase compensation capacitor is also used to hold the previous value of the error output and the previous value of the error output is held until the LED current rises, as shown in FIG. The amount of change (drop amount) of the LED is small and the start-up is quick, so when combined with the on / off control of the soft start function described above, the LED current rise time 10 [μs] (luminance 0.2 [%] Equivalent). FIG. 38 shows the LED current behavior during power control dimming, and FIG. 39 shows the LED current behavior during current driver dimming.

  As a result of the above improvement, as shown in FIG. 40, the semiconductor device 10 of this embodiment has a lower luminance range than the luminance adjustment 1 [%], specifically 0.2 to 100 [%]. In this range, the luminance of the LED can be adjusted, and as shown in FIG. 41, high efficiency can be realized in the entire adjustment range without depending on the brightness. In particular, the efficiency at the time of low brightness adjustment can be greatly improved, and the battery life can be greatly extended (15 minutes or more). In addition, the mounting area is very small, and furthermore, as the previous value of the error output is held, as shown in FIG. 42, the fluctuation of the output voltage is reduced, so that the noise of the output capacitor is also eliminated. It becomes possible.

  Next, a measure for appropriately performing on / off control of the soft start function even when the high level period of the PWM signal (LED on period) is set short will be described.

  In the semiconductor device 10 of the present embodiment, when the predetermined time has elapsed after the PWM signal has been raised to a high level, control for invalidating the subsequent soft start function is performed. At this time, when the high level period of the PWM signal is sufficient, as shown in FIG. 43 (a), the count of the predetermined time is completed during the initial high level period of the PWM signal, and this is used as a trigger to perform the subsequent steps. Although it is possible to invalidate the soft start function, when the high level period of the PWM signal is set short, as shown in FIG. In some cases, it is not possible to complete the counting of the software, and it is not possible to generate a trigger for disabling the soft start function.

  Therefore, the semiconductor device 10 of the present embodiment is configured to count the number of pulses of the PWM signal (for example, the falling edge) and forcibly cancel the soft start when the third pulse is detected. By adopting such a configuration, even when the high level period of the PWM signal is set short, it is possible to appropriately perform on / off control of the soft start function.

  Next, countermeasures for maintaining the normal operation of the LED driver even when a regular PWM signal is not output from another IC that controls the LED driver will be described.

  As described above, the semiconductor device 10 according to the present embodiment includes the LED terminal detection unit 116, and the used LED terminal is connected to the cathode of the LED, while the unused LED terminal is the ground terminal. It is configured to be connected to.

  Here, when the LED terminal voltage is lower than a predetermined threshold (for example, 0.1 [V]), in the configuration in which it is determined that the LED terminal is an unused terminal, as shown in FIG. 44, Even if the LED terminal is determined to be a used terminal, if there is a section in which the PWM signal is erroneously stopped (low level section) due to some cause (for example, a soft bug of the graphic chip), the LED terminal There is a possibility that the voltage drops and is detected as an unused terminal, and the boosting operation of the DC / DC converter is stopped. When such an unintended boost stop occurs, a reset signal must be input, which is inconvenient for the user.

  Therefore, in the semiconductor device 10 of this embodiment, as shown in FIG. 45, when the LED terminal voltage exceeds 1.0 [V] even once, the LED terminal is detected as a use terminal. Even if it falls, it is set as the structure which is not detected as an unused terminal. That is, it is determined whether or not the terminal is a used terminal at power-on, and the LED terminal that is confirmed to be a used terminal even once is determined to be an unused terminal in the middle while holding the detection result. Therefore, even if the PWM signal is momentarily interrupted for some reason, it can be turned on again without any trouble as the PWM signal is restored.

  Next, countermeasures against noise in the LED terminal voltage will be described with reference to FIG.

  FIG. 46 is a block diagram illustrating a configuration example for realizing noise countermeasures for the LED terminal voltage.

  As the capacity of the constant current source Ix that generates the constant current ix is improved, the LED terminal voltage VFB falls sharply, and there is a risk of generating large noise. Therefore, the LED driving device of the present embodiment is configured to include a noise reduction capacitor Cx connected in parallel with the LED as a load. With such a configuration, when the constant current source Ix is started, first, the charging current iCx flows through the capacitor Cx, so that the LED current iLED can be gradually started up. That is, according to the capacitance value of the capacitor Cx, it is possible to adjust the slope when the LED terminal voltage VFB falls to reduce noise.

  FIG. 47 is a diagram for explaining countermeasures against noise of the LED terminal voltage, showing the behavior of the PWM signal, constant current ix, LED current iLED, charging current iCx, and LED terminal voltage VFB in order from the top. Yes.

  In FIG. 46, the configuration in which the capacitor Cx is provided on the panel side has been described as an example. However, the configuration of the present invention is not limited to this, and the capacitor Cx may be provided on the set side. Absent.

  In the above-described embodiment, as an application target of the present invention, a semiconductor device that performs backlight drive control of a medium-sized LCD panel mounted on a mobile notebook PC, a portable DVD player, a car navigation system, and the like has been described as an example. However, the application target of the present invention is not limited to this, and can be widely applied to other load driving apparatuses.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  The present invention is a technique suitable for a drive device that performs drive control of a load (such as an LED backlight of a medium-sized LCD panel).

These are block diagrams which show one Embodiment of the semiconductor device which concerns on this invention. These are correspondence tables showing pin numbers of external terminals, terminal names, input / output classifications, functions, and group classifications of terminal equivalent circuit diagrams. These are input / output equivalent circuit diagrams (groups A to G) of external terminals. These are figures which show the current driver PWM application at the time of 10 light * 6 parallel, LED current 20 [mA], and starting current 8.8 [microampere] setting. These are figures which show the current driver PWM application at the time of 10 light * 4 parallel, LED current 20 [mA], and starting current 6 [microampere] setting. These are figures which show the power control PWM application at the time of 10 light * 6 parallel and LED current 20 [mA] setting. These are figures which show an application at the time of driving at the time of internal REG non-use or 5 [V] or less. 4 is a table showing electrical characteristics of the semiconductor device 10. These are figures for demonstrating operation | movement of a FAILSEL terminal. These are figures for demonstrating light extinction control when a FAILSEL terminal is made into a high level. These are timing charts of control signals. FIG. 5 is a diagram for explaining current limitation of a control signal line. These are tables showing examples of current consumption when RSTV = 5 [V]. These are the logical value tables for demonstrating starting control and selection control of LED current. These are timing charts showing how the light-off control is performed by setting the PWMPOW terminal to low level during PWM control at the PWMPOW terminal. These are the timing charts which showed a mode that light extinction control was performed by making a RSTB terminal into a low level at the time of PWM control with a PWMPOW terminal. These are timing charts showing the start timing of the starting current. These are the timing charts which showed a mode that light extinction control was performed by making a PWMDRV terminal into a low level at the time of PWM control with a PWMDRV terminal. These are the timing charts which showed a mode that light extinction control was performed by making RSTB terminal low level at the time of PWM control with a PWMDRV terminal. These are figures which show the characteristics of current driver PWM dimming and power control PWM dimming. These are figures which show the application at the time of power supply isolation | separation. FIG. 2 is a diagram showing a layout of the semiconductor device 10. These are figures which show an example of an actual layout pattern (surface). These are figures which show an example of an actual layout pattern (back surface). These are the schematic diagrams for demonstrating the sound of the output capacitor C2. These are figures which show the example of 1 arrangement | positioning of the output capacitor C2. These are figures which show the example of 1 arrangement | positioning of the output capacitor C2. These are figures which show the example of 1 arrangement | positioning of the output capacitor C2. FIG. 3 is a block diagram showing an internal configuration of a REG unit 101. These are the figures for comparing the brightness | luminance adjustment characteristic of LED, and the brightness | luminance adjustment characteristic of a cold cathode fluorescent tube (CCFL). These are figures which show an example of the brightness | luminance characteristic of LED. These are figures which show an example of PWM brightness | luminance adjustment. These are the figures for demonstrating the subject of PWM brightness | luminance adjustment. These are the figures for demonstrating the 1st problem which should be solved when implement | achieving shortening of the starting time of LED current. These are the figures for demonstrating the 2nd problem which should be solved when implement | achieving shortening of the starting time of LED current. These are block diagrams which show the example of 1 structure for implement | achieving holding | maintenance of the previous value of an error output. These are timing charts for explaining the fast start-up of the LED current by holding the previous value of the error output. These are timing charts showing LED current behavior during power control dimming. These are timing charts showing LED current behavior during current driver dimming. These are figures which show the correlation of a luminance adjustment value and LED current. These are figures which show the correlation of a luminance adjustment value and efficiency. These are the figures for demonstrating the suppression effect of an output voltage fluctuation | variation. These are the figures for demonstrating on / off control of a soft start function. These are the figures for demonstrating the malfunctioning of LED terminal detection. These are the figures for demonstrating one operation example of the LED terminal detection part 116. FIG. These are block diagrams which show one structural example for implement | achieving the noise countermeasure of LED terminal voltage. These are the figures for demonstrating the noise countermeasure of LED terminal voltage.

Explanation of symbols

10 Semiconductor device (LED driver IC)
101 Internal voltage generator (REG unit)
102 Temperature protection part (TSD part)
103 Internal voltage detection unit 104 Low voltage protection unit (UVLO unit)
105 Schottky barrier diode disconnection protector (SBD disconnection protector)
106 Overvoltage protection part (OVP part)
107 error amplifier 108 PWM comparator 109 soft start unit 110 oscillator unit 111 slope voltage generation unit 112 current detection unit 113 control logic unit 114 SR flip-flop 115 driver 116 LED terminal detection unit 117 LED terminal overvoltage protection unit 118 first current (ISETH) Setting unit 119 Second current (ISETL) setting unit 120 switch 121 inverter 122 switch 123 current driver 124 detection circuit 125 previous value holding circuit 126 switch

Claims (8)

  1. A DC / DC converter that smoothes the input voltage using an input bypass capacitor connected between an application terminal of an input voltage and a ground terminal, converts the input voltage into a desired output voltage, and supplies the output voltage to a load;
    The DC / DC converter according to claim 1, wherein the input bypass capacitor is a plurality of capacitors connected in parallel.
  2.   2. The DC / DC converter according to claim 1, wherein the plurality of capacitors forming the input bypass capacitor are all of the same type.
  3.   3. The DC / DC converter according to claim 1, wherein the plurality of capacitors forming the input bypass capacitor are all arranged in the same direction. 4.
  4.   3. The DC / DC converter according to claim 1, wherein the plurality of capacitors forming the input bypass capacitor are arranged in different directions.
  5.   5. The DC / DC according to claim 1, wherein the plurality of capacitors forming the input bypass capacitor are distributed on the front surface side and the back surface side of the substrate. converter.
  6. A coil having one end connected to the input voltage application terminal, a transistor having one end connected to the other end of the coil, an anode connected to the other end of the coil, and a cathode connected to one end of the load A diode, an output capacitor connected between the cathode of the diode and a ground terminal, and a control unit that performs on / off control of the transistor based on a feedback voltage drawn from the other end of the load. A DC / DC converter comprising:
    6. The DC / DC converter according to claim 1, wherein a connection distance between the coil and the diode is shorter than a connection distance between the diode and the output capacitor.
  7.   A drive device comprising: a battery; and a DC / DC converter that converts an input voltage supplied from the battery into a desired output voltage and supplies the converted voltage to a load, wherein the DC / DC converter is a drive device. A drive device comprising the DC / DC converter according to any one of claims 1 to 6.
  8.   The drive apparatus according to claim 7, further comprising a noise reducing capacitor connected in parallel with the load.
JP2007336878A 2007-07-26 2007-12-27 DC / DC converter and driving apparatus using the same Active JP5097534B2 (en)

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JP2007336878A JP5097534B2 (en) 2007-07-26 2007-12-27 DC / DC converter and driving apparatus using the same
US12/178,793 US8405321B2 (en) 2007-07-26 2008-07-24 Drive unit, smoothing circuit, DC/DC converter
CN201310234917.3A CN103402284B (en) 2007-07-26 2008-07-28 Load drive device and electronic equipment
CN2008101343713A CN101355841B (en) 2007-07-26 2008-07-28 Drive unit, smoothing circuit, DC/DC converter
US13/781,005 US8723442B2 (en) 2007-07-26 2013-02-28 Drive unit, smoothing circuit, DC/DC converter

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JP2012125074A (en) * 2010-12-09 2012-06-28 Rohm Co Ltd Drive circuit and driving method of light-emitting element, and light-emitting device and electronic apparatus using the same
JP2012222322A (en) * 2011-04-14 2012-11-12 Mitsubishi Electric Corp Light source lighting apparatus and lighting device
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CN101355841A (en) 2009-01-28
CN103402284B (en) 2015-09-02
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JP5097534B2 (en) 2012-12-12
CN101355841B (en) 2013-06-26
CN103402284A (en) 2013-11-20

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