JP2009049370A5 - - Google Patents

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Publication number
JP2009049370A5
JP2009049370A5 JP2008137063A JP2008137063A JP2009049370A5 JP 2009049370 A5 JP2009049370 A5 JP 2009049370A5 JP 2008137063 A JP2008137063 A JP 2008137063A JP 2008137063 A JP2008137063 A JP 2008137063A JP 2009049370 A5 JP2009049370 A5 JP 2009049370A5
Authority
JP
Japan
Prior art keywords
layer wiring
wiring
semiconductor device
upper layer
lower layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2008137063A
Other languages
English (en)
Japanese (ja)
Other versions
JP5293939B2 (ja
JP2009049370A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from JP2008137063A external-priority patent/JP5293939B2/ja
Priority to JP2008137063A priority Critical patent/JP5293939B2/ja
Priority to TW097126596A priority patent/TWI437665B/zh
Priority to US12/178,204 priority patent/US8063415B2/en
Priority to KR1020080072364A priority patent/KR20090012136A/ko
Priority to CN2008101769097A priority patent/CN101388391B/zh
Publication of JP2009049370A publication Critical patent/JP2009049370A/ja
Publication of JP2009049370A5 publication Critical patent/JP2009049370A5/ja
Priority to US13/248,965 priority patent/US8264011B2/en
Publication of JP5293939B2 publication Critical patent/JP5293939B2/ja
Application granted granted Critical
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2008137063A 2007-07-25 2008-05-26 半導体装置 Expired - Fee Related JP5293939B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2008137063A JP5293939B2 (ja) 2007-07-25 2008-05-26 半導体装置
TW097126596A TWI437665B (zh) 2007-07-25 2008-07-14 半導體裝置
US12/178,204 US8063415B2 (en) 2007-07-25 2008-07-23 Semiconductor device
KR1020080072364A KR20090012136A (ko) 2007-07-25 2008-07-24 반도체 장치
CN2008101769097A CN101388391B (zh) 2007-07-25 2008-07-25 半导体装置
US13/248,965 US8264011B2 (en) 2007-07-25 2011-09-29 Semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2007193580 2007-07-25
JP2007193580 2007-07-25
JP2008137063A JP5293939B2 (ja) 2007-07-25 2008-05-26 半導体装置

Publications (3)

Publication Number Publication Date
JP2009049370A JP2009049370A (ja) 2009-03-05
JP2009049370A5 true JP2009049370A5 (enrdf_load_html_response) 2011-03-31
JP5293939B2 JP5293939B2 (ja) 2013-09-18

Family

ID=40477685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008137063A Expired - Fee Related JP5293939B2 (ja) 2007-07-25 2008-05-26 半導体装置

Country Status (4)

Country Link
JP (1) JP5293939B2 (enrdf_load_html_response)
KR (1) KR20090012136A (enrdf_load_html_response)
CN (1) CN101388391B (enrdf_load_html_response)
TW (1) TWI437665B (enrdf_load_html_response)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5552775B2 (ja) 2009-08-28 2014-07-16 ソニー株式会社 半導体集積回路
JP5685457B2 (ja) 2010-04-02 2015-03-18 ルネサスエレクトロニクス株式会社 半導体集積回路装置
WO2013018589A1 (ja) * 2011-08-01 2013-02-07 国立大学法人電気通信大学 半導体集積回路装置
US8813016B1 (en) * 2013-01-28 2014-08-19 Taiwan Semiconductor Manufacturing Company Limited Multiple via connections using connectivity rings
CN103546146B (zh) * 2013-09-24 2016-03-02 中国科学院微电子研究所 抗单粒子瞬态脉冲cmos电路
JP5776802B2 (ja) * 2014-02-14 2015-09-09 ソニー株式会社 半導体集積回路
US9653413B2 (en) * 2014-06-18 2017-05-16 Arm Limited Power grid conductor placement within an integrated circuit
US9454633B2 (en) * 2014-06-18 2016-09-27 Arm Limited Via placement within an integrated circuit
US11120190B2 (en) * 2017-11-21 2021-09-14 Advanced Micro Devices, Inc. Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level
WO2020044438A1 (ja) * 2018-08-28 2020-03-05 株式会社ソシオネクスト 半導体集積回路装置
WO2020066797A1 (ja) * 2018-09-28 2020-04-02 株式会社ソシオネクスト 半導体集積回路装置および半導体パッケージ構造
US11488947B2 (en) 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
WO2021192265A1 (ja) * 2020-03-27 2021-09-30 株式会社ソシオネクスト 半導体集積回路装置
CN114492283B (zh) * 2020-11-11 2025-08-01 Oppo广东移动通信有限公司 配置芯片的方法及装置、设备、存储介质

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5923060A (en) * 1996-09-27 1999-07-13 In-Chip Systems, Inc. Reduced area gate array cell design based on shifted placement of alternate rows of cells
JP3672788B2 (ja) * 2000-02-24 2005-07-20 松下電器産業株式会社 半導体装置のセルレイアウト構造およびレイアウト設計方法
JP3718687B2 (ja) * 2002-07-09 2005-11-24 独立行政法人 宇宙航空研究開発機構 インバータ、半導体論理回路、スタティックランダムアクセスメモリ、及びデータラッチ回路
JP4820542B2 (ja) * 2004-09-30 2011-11-24 パナソニック株式会社 半導体集積回路

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