JP2009021639A - Film for semiconductor carrier and semiconductor device using the same, and liquid crystal module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a film for a semiconductor carrier whose insulation resistance between terminals is harder to deteriorate than before even under a hot and humid environment so as to be applicable to fine pitch and high output, and to provide a semiconductor device using the same. <P>SOLUTION: A film 1 for a semiconductor carrier includes a base film 10 having an insulation property, a barrier layer 2 whose major component is a nickel-chrome alloy formed on the base film 10, and a wiring layer 3 composed of a copper-containing conductive matter formed on the barrier layer 2. The chromium content in the barrier layer 2 is 15-50 wt.%. A semiconductor device is formed by connecting a semiconductor element with the wiring layer 3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor carrier film for mounting, for example, a semiconductor chip or a passive component for driving a liquid crystal display device, and a semiconductor device using the same.

  In recent years, carrier tapes on which liquid crystal drivers are mounted are rapidly becoming fine pitches with the increase in the number of outputs of liquid crystal drivers whose functions and performance are increasing. Currently, COF (Chip On Film), which is a film for a semiconductor carrier that can be finer pitched than a TCP (Tape Carrier Package) on which a liquid crystal driver is mounted, is mainly used as a carrier tape.

  A general assembly method (manufacturing method) of a semiconductor device using this COF is as follows. A semiconductor chip on which a protruding electrode is formed is bonded by thermocompression bonding to a semiconductor carrier film formed by patterning a copper wiring on a polyimide base film by etching and applying tin plating on the wiring. . This bonding process is called inner lead bonding (ILB). After the ILB, an underfill resin as a protective material is filled between the semiconductor chip and the semiconductor carrier film, and then the underfill resin is cured. Thereafter, a final test is performed to complete the assembly of the semiconductor device using the COF.

  At this time, the film for semiconductor carriers used as a base film is mainly produced from the following film base material. One is a casting method in which a polyimide film varnish is applied on a copper foil having a thickness of 12 to 18 μm and then cured to create a base film substrate. The other is a metallizing method in which a metal barrier layer is formed on a polyimide substrate by a sputtering method, and a copper film (layer) to be a wiring is formed by copper plating. In order to achieve fine pitch, it is necessary to reduce the copper film thickness, and it is necessary to form a thin film only by controlling the plating thickness rather than the casting method in which it is difficult to control a thin copper foil. A metallizing method capable of achieving this is suitable. The metalizing method is disclosed in, for example, Patent Document 1.

FIG. 8 shows a cross-sectional structure diagram of a general semiconductor carrier film formed by the metalizing method. In the metallizing method, a barrier layer of nickel-chromium alloy having a composition ratio of 7% by weight of chromium and 93% by weight of nickel is formed on the base polyimide substrate 110 by sputtering to be about 50 to 100 mm (5 to 10 nm). It is formed with a thickness. After that, sputtered copper of 1000 to 2000 mm is applied, and then a copper wiring layer to be a wiring pattern is formed with a thickness of about 8 μm by performing electrolytic or electroless copper plating. Next, in order to form a desired wiring pattern on the film substrate, a photoresist is applied on the copper wiring layer and cured, masked with a predetermined pattern, and then exposed, developed, copper etched, and photoresist. Perform peeling. As a result, as shown in FIG. 8, a barrier layer 102 and a copper wiring layer 103 having a predetermined width are formed. After stripping the photoresist, tin plating (not shown) or tin plating and gold plating are formed. In addition, a film for a semiconductor film carrier is produced by coating the solder resist 111 on a necessary portion of the wiring.
JP 2002-252257 A (published September 6, 2002) Journal of Dental Materials and Mechanics Vol.4 No.5, p.455-480, 1985

  However, in the semiconductor carrier film formed by the conventional metalizing method as described above, when the distance between wirings (terminals) where a potential difference occurs is reduced, or when the potential difference generated between terminals is increased due to high output Furthermore, migration occurred between adjacent terminals where a potential difference occurred in a high temperature and high humidity environment, and the insulation resistance between the terminals was likely to deteriorate. In particular, when the wiring is gold-plated, since a cyan solvent is used as the plating solution, migration occurs more significantly due to the trace amount of the solvent remaining. As a result, there has been a problem that further fine pitch and higher output cannot be achieved.

  Here, when the mechanism (mechanism) of occurrence of migration was examined, the following knowledge was obtained, which will be described with reference to FIG.

  FIG. 9 is a cross-sectional view of a conventional film for semiconductor carrier. A barrier layer 102 and copper wiring layers 103a and 103b are formed on a base film 110 made of polyimide. A tin plating 104 is formed on the surfaces of the barrier layer 102 and the wiring layers 103a and 103b, and a gold plating 105 is formed thereon. Here, the barrier layer 102 is made of a nickel-chromium alloy having a chromium content of 7% by weight and a nickel content of 93% by weight, and has a thickness of 7 nm. Further, a potential difference is generated between the wiring layer 103a and the wiring layer 103b. The wiring layer 103a has a positive potential and the wiring layer 103b has a negative potential or a GND potential.

  When such a conventional semiconductor carrier film is placed in an environment of high temperature and high humidity, moisture 106 adheres to the semiconductor carrier film. The moisture 106 contains impurities such as chlorine, and the moisture 106 enters from a porous portion present in the barrier layer 102 on the wiring layer 103a side having a positive potential. As a result, part of the barrier layer 102 is eluted as ions in moisture and moves toward the wiring layer 103b having a negative potential or a GND potential. The copper that becomes the wiring corrodes through the barrier layer elution portion 107, and the corroded portion 109 is generated. Further, the copper forming the wiring layer 103a also elutes toward the wiring layer 103b having a negative potential or a GND potential. In particular, when the gold plating 105 is applied, a cyan solvent is usually used. However, the cyan solvent remaining without being cleaned can cause corrosion of copper, copper that is a component of the wiring layer 103a, and copper. Elution of the components of the barrier layer 102 is likely to occur. Thus, migration occurs due to the copper elution portion 108 and the barrier layer elution portion 107, and the insulation resistance between terminals deteriorates.

  The present invention has been made in view of the above-described problems, and the object of the present invention is to achieve a higher pitch and a higher output so that the terminals can be more connected to each other even in a high temperature and high humidity environment. An object of the present invention is to provide a film for a semiconductor carrier in which insulation resistance hardly deteriorates, a semiconductor device using the film, and a liquid crystal module.

  In order to solve the above problems, a film for a semiconductor carrier of the present invention was formed on a base film having an insulating property, a barrier layer made of a chromium alloy formed on the base film, and the barrier layer. A film for a semiconductor carrier having a wiring layer made of a conductive material containing copper, wherein the chromium content in the barrier layer is 15 to 50% by weight.

  According to said structure, since the surface resistivity and volume resistivity of a barrier layer improve, the electric current which flows through a barrier layer becomes small and it can suppress the corrosion of the copper which forms a wiring layer. In addition, since the surface potential of the barrier layer is close to the standard potential, elution of the components forming the barrier layer into moisture can be suppressed. This eliminates migration between terminals.

  As described above, it is possible to provide a film for a semiconductor carrier that can be applied to fine pitch and high output, and in which the insulation resistance between terminals is less deteriorated than in the past even in a high temperature and high humidity environment.

  In order to achieve the above object, a film for a semiconductor carrier according to the present invention is characterized in that the chromium content of the barrier layer is 15 to 30% by weight in addition to the above-described configuration.

  According to the above configuration, when the barrier layer and the wiring layer are formed in a predetermined wiring pattern, even if an etching process using a normal photosensitive resist is performed, the non-defective product rate in the wiring pattern formation is as high as 80% or more. The value can be maintained and productivity can be improved.

  In order to achieve the above object, a film for a semiconductor carrier according to the present invention is characterized in that, in addition to the above configuration, the barrier layer has a thickness of 10 to 35 n.

  According to said structure, since the thickness of a barrier layer is as thick as 10 nm or more, the void | hole part (porous part) in a barrier layer can be eliminated, and the penetration | invasion of a water | moisture content is prevented also in a high-temperature, high-humidity environment. Can do. Thereby, generation | occurrence | production of the migration between terminals can be suppressed further. In addition, since the thickness of the barrier layer is 35 nm or less, even when an etching process using a normal photosensitive resist is performed when the barrier layer and the wiring layer are formed in a predetermined wiring pattern, the yield rate in the wiring pattern formation is improved. Can be maintained at a high value of 80% or more, and productivity can be improved.

  In order to achieve the above object, a film for a semiconductor carrier according to the present invention is characterized in that, in addition to the above configuration, the thickness of the base film is 25 to 50 μm.

  According to said structure, it is convenient in handling and when it fixes to another member, bending etc. become easy.

  In order to solve the above problems, a semiconductor device according to the present invention is characterized in that a semiconductor element is bonded to a wiring layer included in the semiconductor carrier film.

  According to the above configuration, it is possible to provide a semiconductor device that can be applied to fine pitch and high output, and in which the insulation resistance between terminals is less deteriorated than in the past even in a high temperature and high humidity environment.

  In order to solve the above problems, a liquid crystal module according to the present invention includes the semiconductor device described above.

  According to the above configuration, it is possible to provide a liquid crystal module capable of stabilizing the operation and improving the reliability even in a high temperature and high humidity environment.

  As described above, the film for a semiconductor carrier of the present invention includes an insulating base film, a barrier layer made of a chromium alloy formed on the base film, and copper formed on the barrier layer. A film for a semiconductor carrier having a wiring layer made of a conductive material, wherein the barrier layer has a chromium content of 15 to 50% by weight.

Therefore, since the surface resistivity and volume resistivity of the barrier layer are improved, the current flowing through the barrier layer is reduced, and corrosion of copper forming the wiring layer can be suppressed. In addition, since the surface potential of the barrier layer is close to the standard potential, elution of the components forming the barrier layer into moisture can be suppressed. This eliminates migration between terminals.

  As described above, it is possible to provide a film for a semiconductor carrier which can be applied to fine pitch and high output, and can provide a semiconductor carrier film in which insulation resistance between terminals is less deteriorated than in the past even in a high temperature and high humidity environment. .

  An embodiment of the semiconductor device according to the present invention will be described below with reference to FIGS.

  FIG. 1 is a cross-sectional view of a film 1 for a semiconductor carrier according to the present embodiment. In the semiconductor carrier film 1, a barrier layer 2 made of a chromium alloy is formed on one surface of an insulating base film 10 with a predetermined thickness, and the wiring layer 3 is formed on the barrier layer 2 by, for example, about 8 μm. Is formed. The chromium alloy is an alloy containing chromium and other metal elements, for example, a nickel-chromium alloy containing chromium and nickel. In this embodiment, the nickel-chromium alloy is used. The wiring layer 3 is formed of a conductive material containing copper. The barrier layer 2 and the copper wiring layer 3 are formed in a line shape having a predetermined wiring pattern. FIG. 1 shows a cross-sectional view of a place where two adjacent lines are formed. Although not shown, the surfaces of the barrier layer 2 and the copper wiring layer 3 are tin (Sn) plated. Furthermore, in order to further improve the bondability with the semiconductor element (semiconductor chip), gold (Au) plating may be applied instead of tin plating. In addition, necessary portions of the wiring are covered with an insulating material such as a solder resist. This prevents a short circuit between the wirings.

  In addition, the base | substrate of the said base film 10 consists of a heat resistant resin material which has plasticity, for example, and a polyimide-type resin is preferable. Further, the thickness of the base film 10 is preferably 25 to 50 μm because it is inconvenient to handle if it is too thin, and on the other hand, if it is too thick, it becomes difficult to bend when fixing to other members.

  Further, in the semiconductor device 20 according to the present embodiment, a semiconductor chip or a passive component is bonded on a predetermined portion of the wiring pattern that is not covered with an insulating material such as a solder resist in the semiconductor carrier film 1. It has a structure.

  The manufacturing method of the semiconductor carrier film 1 and the semiconductor device 20 using the same is as follows.

  For example, on the base film 10 made of polyimide, a nickel-chromium alloy blended at a predetermined mixing ratio is adhered to a predetermined thickness by a sputtering method to form the metal barrier layer 2 and further to a predetermined thickness. Add copper by sputtering. Thereafter, copper is deposited by electrolytic plating to form a copper wiring layer 3. The copper deposition method may be partially electroless plating.

  Next, unnecessary portions of the barrier layer and the copper wiring layer are removed so that the barrier layer 2 and the copper wiring layer 3 have a predetermined wiring pattern. As a removal method (patterning method), for example, a method such as an etching process using a photosensitive resist is generally known. According to this method, a wiring pattern can be formed relatively easily. That is, a photoresist is applied on the deposited copper and dried and cured. Thereafter, a mask is formed with a predetermined pattern, and a copper wiring (inner lead) is formed through an exposure process, a development process, an etching process, and a photoresist peeling process.

  After a desired wiring pattern is formed, a tin plating layer is formed with a thickness of, for example, 0.1 to 0.5 μm on the surfaces of the barrier layer 2 and the wiring layer 3. Furthermore, when gold plating is applied to the upper layer of the tin plating layer, the thickness is, for example, 0.1 to 0.5 μm. When gold plating is performed, a cyan solvent is usually used. Thereafter, the semiconductor carrier film 1 is formed by coating an insulating material such as a solder resist on the necessary portion of the wiring.

  A semiconductor chip or a passive component is connected to the semiconductor carrier film 1. In this embodiment, for example, an inner lead bonding (ILB) method is employed as the connection method. In the ILB method, generally, a semiconductor chip has a protruding electrode (bump) made of gold, and the protruding electrode and a wiring layer on which a tin plating of a film for a semiconductor carrier is thermocompression bonded. In this method, the gold-tin alloy is eluted at the joint interface between the two, and the semiconductor chip and the film for film semiconductor carrier are electrically connected. FIG. 2 shows a cross-sectional view of the semiconductor device 20 according to the present embodiment. The semiconductor chip 21 includes a protruding electrode 22, and the protruding electrode 22 and the wiring layer 3 including a tin plating layer (not shown) are connected by thermocompression bonding. Further, a protective material 23 such as an underfill resin is filled between the semiconductor chip 21 and the base film 10 after the connection. Thereafter, a final test is performed to complete the manufacture of the semiconductor device 20.

  Furthermore, the liquid crystal module according to the present invention includes the semiconductor device 20 and a display panel in which a liquid crystal layer is disposed between, for example, two glass substrates, and an external connection terminal connected to the liquid crystal layer. Are connected to the wiring layer 3 of the semiconductor device 20. At this time, the semiconductor device 20 functions as a liquid crystal driver for driving the display panel. Thereby, the operation of the liquid crystal module can be stabilized even in a high temperature and high humidity environment, and the reliability of the liquid crystal module can be improved.

  Here, the characteristic part of the present embodiment is that the chromium content of the nickel-chromium alloy forming the barrier layer 2 is increased from 7% by weight to 15 to 50% by weight. This increases the surface resistivity and volume resistivity of the barrier layer 2 compared to the conventional barrier layer having a chromium content of 7% by weight, and migration between wirings (terminals) in the film 1 for semiconductor carriers. Generation is suppressed and insulation deterioration between terminals is prevented.

  FIG. 3 is a graph showing the surface resistivity and volume resistivity of a barrier layer formed of a nickel-chromium alloy at different chromium contents. The thickness of the barrier layer shown in FIG. 3 is 30 nm (300 mm). As shown in FIG. 3, the surface resistivity and volume resistivity of the barrier layer show maximum values when the chromium content is 30% by weight. Here, the chromium content is preferably 15 to 55% by weight. As a result, the surface resistivity is 30Ω or more, which is 1.3 times or more compared with the conventional 7% by weight. As described above, when the surface resistivity and the volume resistivity are increased, the current flowing through the barrier layer 2 is reduced, so that the chemical reaction between the copper in the wiring layer 3 and the impurities in the invading moisture is suppressed. Thereby, since corrosion of copper and elution of copper ions can be suppressed, the occurrence of migration can be suppressed.

  Furthermore, the chromium content is preferably 20 to 45% by weight. As a result, the surface resistivity becomes 35Ω or more, which can be 1.5 times or more compared to the conventional 7% by weight, and migration can be further prevented.

FIG. 4 is a graph showing the surface potential in an aqueous cyan solution in each barrier layer having different chromium contents. The vertical axis represents the potential when the electrode potential of the saturated calomel electrode (SCE) is 0V. As shown in FIG. 4, it is about −0.4 V vs. SCE when the chromium content is 7 wt% of the conventional case, but it approaches about −0.2 V vs. SCE by increasing the chromium content. . Since the electrode potential of the standard hydrogen electrode is about −0.2 V vs. SCE, the surface potential of the barrier layer can be made substantially the same as the potential of the standard hydrogen electrode by increasing the chromium content. Thereby, the elution amount of the metal ions of the barrier layer into moisture can be suppressed, that is, the occurrence of migration can be further suppressed. As shown in FIG. 4, a decrease in the absolute value of the surface potential due to an increase in the chromium content has been confirmed in an aqueous cyan solution, and the semiconductor carrier film having a barrier layer having a chromium content of 15 to 55% by weight, It can be seen that the present invention is also suitable when gold plating using an ordinary cyan solvent is applied to the wiring.

  The chromium content is preferably 30% by weight or less. Thereby, even when the etching process using a normal photosensitive resist is applied at the time of wiring pattern formation, the non-defective rate (etching property) at the time of wiring pattern formation can be maintained at 80% or more. That is, the productivity of the semiconductor carrier film can be improved.

  The thickness of the barrier layer is preferably 10 nm or more. Thereby, it becomes difficult to form a porous part in the barrier layer, and moisture can be prevented from entering. That is, the chemical reaction between copper forming the wiring layer and impurities in moisture can be prevented, and the occurrence of migration between terminals can be further suppressed.

  Furthermore, the thickness of the barrier layer is preferably 35 nm or less. Thereby, a normal etching process can be applied at the time of wiring pattern formation, and the non-defective rate at the time of wiring patterning can be maintained at 80% or more. That is, the productivity of the semiconductor carrier film can be improved.

  Moreover, it is preferable that 0.1-5 weight% zinc is contained in the barrier layer of chromium alloy with respect to the total weight of a barrier layer as a subcomponent. That is, the barrier layer is preferably a chromium-zinc alloy in which 15 to 50 wt% chromium, 0.1 to 5 wt% zinc, and the balance is another metal, such as nickel. Thereby, the occurrence of the migration can be prevented and the rust prevention effect of copper is improved.

  Moreover, it is preferable that 1-10 weight% of molybdenum is contained in the barrier layer of chromium alloy with respect to the total weight of a barrier layer as a subcomponent. That is, the barrier layer is preferably a chromium-molybdenum alloy in which 15 to 50% by weight of chromium, 1 to 10% by weight of molybdenum, and the balance is another metal such as nickel. Thereby, generation | occurrence | production of the said migration can be prevented and elution of the nickel component of a barrier layer can be prevented.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  Examples of the semiconductor device according to the present invention will be described below, but the present invention is not limited thereto.

[Examples 1-11 and Comparative Examples 1-2]
A barrier layer mainly composed of a nickel-chromium alloy having the chromium content and thickness shown in Table 1 below was formed on a 38 μm-thick polyimide base film (product name: Esperflex, manufactured by Sumitomo Metal Mining) by sputtering. . Table 1 also describes other examples and comparative examples described later.

  Next, a wiring layer made of copper was formed on the barrier layer by electrolytic copper plating so as to have a thickness of 8 μm. Next, it was applied onto the copper wiring layer using a photoresist so as to have a wiring pattern having a terminal pitch of 100 μm (wiring width 50 μm, wiring distance 50 μm), and dried and cured. Next, it developed after exposing with a glass photomask. Further, unnecessary portions of the copper wiring layer and the barrier layer were removed by etching. A semiconductor device for reliability evaluation in which tin plating 0.2 μm and gold plating 0.2 μm are applied to the surfaces of the barrier layer and the wiring layer, and a semiconductor chip is bonded on the wiring pattern of the film for semiconductor carrier by the ILB method Was made.

  This semiconductor device is placed in a constant temperature and humidity chamber (product name: FH13, manufactured by ETAC) set to environmental conditions of 85 ° C. and 85% RH, and a DC voltage of 15 V is applied between adjacent wires (terminals). It was confirmed whether or not migration occurred after a predetermined time. Note that the presence or absence of migration is evaluated by a microscope.

  Table 2 below shows the evaluation results of Examples 1 to 4 and Comparative Examples 1 and 2 after 100 hours and 500 hours, and Table 3 shows the evaluation results of Example 2 and Examples 5 to 11 after 100 hours and 500 hours. It was. In the figure, ○ indicates that no migration occurred, X indicates that migration occurred, and Δ indicates that the etching process was insufficient in wiring patterning, so that unnecessary portions of the barrier layer and wiring layer remained. Represents.

From Table 2, in Examples 1 to 4 having a chromium content of 15 to 50% by weight, no migration occurred even after 100 hours had passed, and Comparative Examples 1 and 2 having a chromium content of 7% by weight and 10% by weight were used. It can be seen that the reliability is improved. As described above, this is related to the fact that the surface resistivity of the barrier layer is 1.3 times or more that of Comparative Example 1. Furthermore, in Example 2 and Example 3 in which the chromium content is 20 to 30% by weight, it can be seen that migration does not occur even after 500 hours have elapsed, and the deterioration of the insulation resistance between the terminals can be further suppressed.

  Further, from Table 3, in Example 2 and Examples 5 to 10 having a chromium content of 20% by weight, no occurrence of migration was observed regardless of the thickness of the barrier layer. In Example 11 in which the thickness of the barrier layer was 50 nm, as described later, the thickness of the layer was too thick, and thus the barrier layer to be removed by etching and the wiring layer remained without being removed in wiring patterning. Migration evaluation could not be performed.

  Table 4 below shows the migration rate for each elapsed time in Example 2 and Comparative Example 1.

  Thus, in Comparative Example 1, the probability of occurrence of migration is already 20% after 240 hours have elapsed, but in Example 2, the probability of occurrence of migration is 0% even after 1000 hours have elapsed.

[Etching property evaluation results]
A barrier layer having a thickness of 10 nm was formed using a nickel-chromium alloy having a chromium content of 0 to 100% by weight in the same manner as in Examples 1 to 11, and wiring patterning was performed. Here, in order to confirm whether or not an unnecessary portion to be removed of the barrier layer and the wiring layer is surely removed by etching, an appearance inspection by AOI (automatic optical inspection) of the etched portion and open / short between the terminals are performed. An electrical inspection was conducted by testing. That is, a sample in which an unnecessary portion to be removed by etching is extracted by appearance inspection, and electrical inspection is performed on the sample, and it is confirmed that the terminals are short-circuited (resistance value between terminals is 10 ⁸ Ω or less). The non-defective product rate (etching property) was measured on the assumption that the sample was a defective sample.

  FIG. 5 shows the measurement results. In FIG. 5, the vertical axis represents the etching property. As shown in FIG. 5, it can be seen that when the chromium content is 30% by weight or less, the etching property is as high as 80% or more. If the etching property is 80% or more, the productivity can be further improved. Thus, in order to employ an etching process method using a photosensitive resist, which is a relatively simple method, in order to remove unnecessary portions of the barrier layer and the copper wiring layer, the chromium content is set to 30% by weight or less. It turns out that it is preferable to do.

Further, in the same manner as in Examples 1 to 11, a barrier layer is formed so that the chromium content is 7 wt% and 20 wt% so that the thickness is 7 to 50 nm (70 to 500 mm), Wiring patterning was performed. The evaluation result of the etching property at this time is as shown in FIG. As shown in FIG. 6, it can be seen that the etching property becomes 100% when the thickness of the barrier layer is 35 nm (350 mm) or less. Accordingly, in order to employ an etching method using a photosensitive resist, which is a relatively simple method, in order to remove unnecessary portions of the barrier layer and the copper wiring layer, the thickness of the barrier layer is set to 35 nm or less. It turns out that it is preferable.

  Next, although the Example of the film for semiconductor carriers which concerns on this invention is shown, this invention is not limited to this.

[Examples 12 and 13 and Comparative Examples 3 and 4]
In the same manner as in Examples 1 to 11, after forming a barrier layer made of a nickel-chromium alloy having the chromium content and thickness shown in Table 1 on the base film, copper is formed on the barrier layer. A wiring layer was formed. Next, an etching process is performed in the same manner as in Example 2 so as to form a comb-shaped wiring pattern having a terminal pitch of 40 μm (wiring width 20 μm, wiring distance 20 μm). Examples 12 and 13 and Comparative Examples 3 and 4 were prepared. Note that a solder resist was applied to the comb-shaped portion with only a part of the comb-shaped portion exposed.

First, a 40 V DC voltage was applied between the terminals of the semiconductor carrier film at room temperature and normal humidity (20 ° C., 25% RH), and a leak current value between the terminals was measured with an ammeter. Next, each sample was placed in a constant temperature bath of 85 ° C. (product name: KEYLESS) and held for about 1 h with a voltage of 40 V applied between adjacent terminals, and then the humidity was kept at normal humidity ( The leakage current value flowing between the terminals was measured stepwise from 25% RH).

  The measurement results are shown in FIG. In FIG. 7, the horizontal axis represents the environmental conditions of temperature and humidity at the time of measurement, and the vertical axis represents the leak current value flowing between the terminals. As shown in FIG. 7, in Comparative Example 3 with a chromium content of 7% by weight and Comparative Example 4 with 100% by weight, the leakage current value increases when the humidity exceeds 60% RH. On the other hand, in Examples 12 and 13 in which the chromium content was 20% by weight, the leakage current value did not change even when the humidity increased to 95% RH, and the deterioration of the insulation resistance between the terminals due to the increase in humidity was observed. I couldn't. This is because the surface resistivity of the barrier layer is higher than that of the comparative example as described above.

[Example 14 and Comparative Examples 5 and 6]
In the same manner as in Example 12, it has the chromium content and the barrier layer thickness shown in Table 1 above, and the inter-terminal pitch of the comb-shaped electrode wiring pattern is 30 μm (wiring width 15 μm, inter-wiring distance 15 μm). In this way, Example 14 and Comparative Examples 5 and 6 which are films for semiconductor carriers were produced in triplicate. Wiring after 100h, 240h, 500h, and 1000h have passed with the semiconductor carrier film placed in a constant temperature and humidity chamber set at 85 ° C. and 85% RH and a 40V DC voltage applied between the terminals. The presence or absence of copper corrosion was confirmed from the back side of the base film with a microscope. The measurement results are shown in Table 5 below. In Table 5, the denominator represents the total number of samples, and the numerator represents the number of samples in which the occurrence of corrosion was confirmed.

  As shown in Table 5 above, in Comparative Example 5 having a chromium content of 7% by weight and Comparative Example 6 having a chromium content of 7% by weight, corrosion was confirmed in all samples after 100 hours, but the chromium content was 20% by weight. % Of Example 14 showed no corrosion in all samples even after 1000 hours.

It is sectional drawing of the film for semiconductor carriers which concerns on this invention. 1 is a cross-sectional view of a semiconductor device according to the present invention. It is a graph which shows the chromium content rate dependency of the surface resistance value and volume resistance value of a barrier layer. It is a graph which shows the surface potential in the cyan solution in each barrier specification. It is a graph which shows the etching property with respect to the chromium content rate of a barrier layer. It is a graph which shows the etching property with respect to the thickness of a barrier layer. It is a graph which shows the humidity dependence of the leakage current value between terminals with respect to the specification of each barrier layer. It is sectional drawing of the film for semiconductor carriers formed by the conventional metalizing method. It is sectional drawing of the film for conventional semiconductor carriers explaining the generation | occurrence | production mechanism of migration.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor carrier film 2 Barrier layer 3 Wiring layer 10 Base film 20 Semiconductor device 21 Semiconductor chip (semiconductor element)

Claims (6)

An insulating base film;
A film for a semiconductor carrier having a barrier layer made of a chromium alloy formed on a base film and a wiring layer made of a conductive material containing copper formed on the barrier layer,
A film for a semiconductor carrier, wherein a chromium content in the barrier layer is 15 to 50% by weight.   The film for a semiconductor carrier according to claim 1, wherein the barrier layer has a chromium content of 15 to 30% by weight.   The film for a semiconductor carrier according to claim 1, wherein the barrier layer has a thickness of 10 to 35 nm.   The thickness of the said base film is 25-50 micrometers, The film for semiconductor carriers of Claim 1 characterized by the above-mentioned.   5. A semiconductor device, wherein a semiconductor element is bonded to a wiring layer of the semiconductor carrier film according to claim 1.   A liquid crystal module comprising the semiconductor device according to claim 5.

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