JP2009003874A - Information processor - Google Patents

Information processor Download PDF

Info

Publication number
JP2009003874A
JP2009003874A JP2007166536A JP2007166536A JP2009003874A JP 2009003874 A JP2009003874 A JP 2009003874A JP 2007166536 A JP2007166536 A JP 2007166536A JP 2007166536 A JP2007166536 A JP 2007166536A JP 2009003874 A JP2009003874 A JP 2009003874A
Authority
JP
Japan
Prior art keywords
voltage
dc
battery
arithmetic processing
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2007166536A
Other languages
Japanese (ja)
Other versions
JP5138284B2 (en
Inventor
Takeshi Ishizuka
Tomohiro Miki
Hajime Nagano
Takasuke Nakayama
智裕 三木
崇介 中山
肇 永野
雄志 石塚
Original Assignee
Kyocera Corp
京セラ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp, 京セラ株式会社 filed Critical Kyocera Corp
Priority to JP2007166536A priority Critical patent/JP5138284B2/en
Publication of JP2009003874A publication Critical patent/JP2009003874A/en
Application granted granted Critical
Publication of JP5138284B2 publication Critical patent/JP5138284B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor capable of efficiently reducing electric power consumption of the whole processor. <P>SOLUTION: This information processor is driven by output voltage of a DC-DC converter 11, and has an arithmetic processing part 14 for processing data synchronously with an operation clock, and has a storage means 4 for storing an output current value becoming highest in voltage conversion efficiency of the DC-DC converter 11, and a clock frequency control means 13 for controlling a frequency of the operation clock so that the output current value stored in the storage means 4 becomes substantially equal to a consumption current value of the arithmetic processing part 14 when data processed by the arithmetic processing part 14 is a predetermined classification. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an information processing apparatus having an arithmetic processing unit driven by a DC-DC converter.

  In general, an information processing apparatus includes a CPU including an arithmetic processing unit that processes data. The CPU processes data in synchronism with the operation clock under the supply of the driving voltage. When the driving voltage is constant, the current consumed by the CPU generally operates as shown in FIG. 9, for example. It increases in proportion to the clock frequency (operating frequency).

  As a conventional information processing apparatus utilizing such CPU characteristics, for example, there are a low-speed mode that operates with a low-frequency operation clock and a low voltage, and a high-speed mode that operates with a high-frequency operation clock and a high voltage. In normal processing, the device is operated in the low-speed mode. When a specific factor such as I / O access or interrupt occurs, the device is operated in the high-speed mode for a certain period of time, thereby reducing the current consumption of the entire device. Those are known (for example, see Patent Document 1).

  Also, as another information processing device, depending on the type of the connected power source, the battery is operated in the low speed mode when the battery is connected, and in the high speed mode when the commercial power source is connected. Also known is a device that saves power when the device is connected (see, for example, Patent Document 2).

Japanese Patent Laid-Open No. 5-11897 JP 2001-84054 A

  By the way, in recent information processing apparatuses, as in portable communication terminals, for example, a DC-DC converter is mounted, and a DC output voltage converted by the DC-DC converter is supplied to the CPU as a drive voltage. It is increasing.

  However, the DC-DC converter generally has a voltage conversion efficiency characteristic as shown in FIG. 10, for example, and the conversion efficiency peaks at a predetermined output current value (in the case of FIG. 10, 100 mA). For this reason, in a configuration in which power is supplied to the CPU using a DC-DC converter, if the CPU is operated in a low-speed mode as described in Patent Documents 1 and 2, conversion efficiency depends on the output current at that time. May decrease and the power consumption of the entire apparatus may increase.

  For example, when a battery having a rated voltage of 3.7 V is used as a power source and the battery voltage is converted to 1.8 V by a DC-DC converter, the DC-DC converter has the voltage conversion efficiency characteristics shown in FIG. If the output current of the DC-DC converter is 150 mA, the voltage conversion efficiency at that time is 80%, so the output current of the battery is about 91 mA. On the other hand, even if the output voltage of the DC-DC converter is the same 1.8V, when the output current is 60 mA, the voltage conversion efficiency at that time is 85%, so the output current of the battery is about 34 mA.

  For this reason, for example, when certain data is processed with the frequency of the operation clock of the CPU (hereinafter also referred to as a clock frequency as appropriate) as the first clock frequency (high-speed mode) with a current consumption of 150 mA, the processing is performed. If 6 s is required, the amount of power of the device is approximately 2200 mWs from (battery current) × (battery voltage) × (operation time). On the other hand, if the same data processing is executed at the second clock frequency (low speed mode) with a clock frequency lower than that of the high speed mode and a current consumption of 60 mA, the processing requires 20 s. If calculated in the same manner, it becomes about 2500 mWs, and on the contrary, it increases by 10% or more than in the case of the high-speed mode, and low power consumption cannot be achieved.

  Accordingly, an object of the present invention made in view of such a point is to provide an information processing apparatus capable of efficiently reducing the power consumption of the entire apparatus.

The invention according to claim 1 that achieves the above object is an information processing apparatus having an arithmetic processing unit that is driven by an output voltage of a DC-DC converter and processes data in synchronization with an operation clock.
Storage means for storing an output current value at which the voltage conversion efficiency of the DC-DC converter is highest;
When the data to be processed by the arithmetic processing unit is of a predetermined type, the frequency of the operation clock is set so that the output current value stored in the storage unit is substantially equal to the current consumption value of the arithmetic processing unit. Clock frequency control means for controlling
It is characterized by comprising.

The invention according to claim 2 is the information processing apparatus according to claim 1,
Battery monitoring means for monitoring the remaining battery voltage or voltage;
The clock frequency control means performs frequency control of the operation clock when the remaining amount or voltage of the battery monitored by the battery monitoring means is a predetermined value or less.
It is characterized by this.

The invention according to claim 3 is the information processing apparatus according to claim 1,
Wireless transmission means, and measurement means for measuring the transmission output of the wireless transmission means,
The clock frequency control means executes frequency control of the operation clock when the transmission output measured by the measurement means is a predetermined value or more.
It is characterized by this.

  According to the present invention, when the data to be processed by the arithmetic processing unit is of a predetermined type, the frequency of the operation clock of the arithmetic processing unit, the current consumed by the arithmetic processing unit, the DC− that drives the arithmetic processing unit Since the frequency is controlled to be approximately equal to the output current value at which the voltage conversion efficiency of the DC converter is highest, the power consumption of the entire apparatus can be efficiently reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a functional block diagram showing the configuration of the information processing apparatus according to the first embodiment of the present invention. The information processing apparatus shown in FIG. 1 is a portable communication terminal that uses a battery 1 as a power source. The voltage conversion unit 2, a CPU 3 that controls the entire operation including data processing, a memory 4 that exchanges information with the CPU 3, a liquid crystal screen, and the like. Data is transmitted wirelessly via a display unit 5 for displaying information, an image pickup unit 6 for photographing with a camera, an operation unit 7 for a user to operate keys, a clock generation unit 8 for supplying an operation clock to the CPU 3, and an antenna 9. It has the transmission / reception part 10 for transmitting / receiving.

  The voltage conversion unit 2 includes a plurality of DC-DC converters 11 and a plurality of regulators 12 that convert the voltage of the battery 1 into a required DC voltage and supply power to each unit. At least the transmission unit of the CPU 3 and the transmission / reception unit 9 includes The output voltage of the corresponding DC-DC converter 11 is supplied.

  The CPU 3 synchronizes data with the frequency converter 13 which is a clock frequency control means for converting the frequency of the operation clock from the clock generator 8 as necessary, and the operation clock output through the frequency converter 13. And an arithmetic processing unit 14 for processing. Further, although not shown, the CPU 3 also includes an external I / O unit, an audio processing unit, a video processing unit, and the like. In FIG. 1, the frequency conversion unit 13 is built in the CPU 3, but may be provided outside the CPU 3.

  In the present embodiment, the output current value at which the voltage conversion efficiency of the DC-DC converter 11 that drives the CPU 3 is the highest is measured in advance and stored in the memory 4 as storage means. Further, the relationship between the frequency of the operation clock of the CPU 3 and the current consumption as shown in FIG. 9 is also measured in advance and stored in the memory 4. In this way, the frequency conversion unit 13 controls the frequency of the operation clock supplied to each unit of the CPU 3 including the arithmetic processing unit 14 according to the type of data processed by the arithmetic processing unit 14.

  Hereinafter, the operation of the mobile communication terminal according to the present embodiment will be described with reference to the flowchart shown in FIG.

  First, when receiving a data processing request, the arithmetic processing unit 14 determines whether or not the data to be processed is of a predetermined type, that is, whether or not the clock frequency of the arithmetic processing unit 14 can be varied low. (Step S1).

  Here, the predetermined type of data is, for example, data with a light load such as a voice call or content download, or data that does not require real-time performance, such as data with a heavy load such as a TV phone, streaming playback, or video playback. The data for which real-time property is required is data other than a predetermined type. The type of data processed by the arithmetic processing unit 14 is determined by the data itself or an application to be activated.

  If it is determined in step S1 that the data to be processed is data other than the predetermined type and the clock frequency cannot be varied low, it is necessary to display data such as a moving image on the display unit 5 without delay. Therefore, while the clock frequency is kept high by the frequency converter 13, for example, the CPU 3 is kept at the maximum clock frequency at full speed (step S2), the processing is started (step S3), and the processing is completed (step S3). Step S4), the process proceeds to the next step, and transitions to the sleep mode as necessary.

  On the other hand, if it is determined in step S1 that the data to be processed is data of a predetermined type and the clock frequency can be varied low, the DC-DC converter 11 for driving the CPU 3 stored in the memory 4 is used. The frequency conversion unit 13 controls the clock frequency to be low so that the output current value that maximizes the voltage conversion efficiency and the current consumption value of the CPU 3 are substantially equal to each other, thereby setting the CPU 3 to a low speed (step S5). The process starts at. For example, when the DC-DC converter 11 has the voltage conversion efficiency characteristics shown in FIG. 10, the memory 4 stores an output current value of 100 mA at which the voltage conversion efficiency is 90% at the maximum. Therefore, the CPU 3 is controlled to a clock frequency at which the current consumption of the CPU 3 is 100 mA or a value closest to 100 mA, that is, approximately 100 mA.

  In this way, if the clock frequency of the CPU 3 is controlled, for example, as described above, the rated voltage of the battery 1 is 3.7V, and the battery voltage is converted to 1.8V by the DC-DC converter 11 and the CPU 3 When the same data as described above is processed at a clock frequency at which the current consumption of the CPU 3 is approximately 100 mA, and the processing requires 10 s, the output current of the battery 1 in this case is approximately 54 mA. Therefore, the amount of power of the terminal necessary for processing is approximately 2000 mWs when calculated in the same manner.

  Therefore, if the current consumption at the clock frequency for operating the CPU 3 at full speed is 150 mA, the processing speed is slower than that, but the power consumption of the entire terminal can be reduced by about 200 mWs. In addition, processing can be performed at a higher speed than when processing is performed with a clock frequency of 60 mA, and the power consumption of the entire terminal can be reduced by about 500 mWs.

  According to the present embodiment, when the data to be processed by the arithmetic processing unit 14 built in the CPU 3 is a predetermined type of data, for example, data with a light load such as a voice call or content download, Is the type of data that is not required, the frequency of the operation clock of the CPU 3 is controlled so that the current consumption value of the CPU 3 is substantially equal to the output current value at which the voltage conversion efficiency of the DC-DC converter 11 is maximized. Therefore, the power consumption of the entire terminal can be efficiently reduced, and the usage time of the battery 1 can be extended. In addition, the data processed by the arithmetic processing unit 14 is data other than a predetermined type that requires CPU performance, such as heavy load data such as videophone, streaming playback, and video playback, and data that requires real-time performance. In this case, since the CPU 3 is operated with a full-speed operation clock, the user operability is not affected.

(Second Embodiment)
FIG. 3 is a functional block diagram showing the configuration of the information processing apparatus according to the second embodiment of the present invention. In this embodiment, in the mobile communication terminal shown in the first embodiment, a battery monitoring unit 15 that monitors the remaining amount or voltage of the battery 1 is provided, and the monitoring result is supplied to the CPU 3 so that the remaining battery 1 remains. When the amount or voltage is equal to or less than a predetermined value, the frequency control of the operation clock by the frequency converter 13 is executed. Since other configurations and operations are the same as those of the first embodiment, the same configurations and processes as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate. To do.

  That is, in this embodiment, as shown in the flowchart in FIG. 4, when a data processing request is received, whether or not the data to be processed in step S1 is of a predetermined type, that is, the clock frequency of the arithmetic processing unit 14 is set. Prior to determining whether the data can fluctuate low, the CPU 3 determines whether the remaining amount or voltage of the battery 1 is equal to or less than a predetermined value based on the monitoring result by the battery monitoring unit 15 (step S11). ). In the following description, for convenience, the battery monitoring unit 15 monitors the voltage of the battery 1.

  As a result, if the battery voltage exceeds a predetermined value, it is assumed that the remaining battery level is sufficient, and in step S2, the frequency conversion unit 13 causes the CPU 3 to reach full speed regardless of the type of data to be processed. Processing is started in step S3 while maintaining the clock frequency.

  On the other hand, when the battery voltage is equal to or lower than the predetermined value, the frequency of the battery 1 is efficiently used according to the type of data processed by the arithmetic processing unit 14 as in the first embodiment. The conversion unit 13 controls the frequency of the operation clock supplied to each unit of the CPU 3 including the arithmetic processing unit 14.

  As described above, in the present embodiment, the battery monitoring unit 15 monitors the remaining amount or voltage of the battery 1, and when the remaining amount or voltage of the battery 1 is equal to or lower than a predetermined value, Since the frequency control is executed, when the remaining amount or voltage of the battery 1 becomes a predetermined value or less, the power of the battery 1 can be used efficiently and the usage time of the battery 1 can be extended. it can.

(Third embodiment)
FIG. 5 is a functional block diagram showing the configuration of the information processing apparatus according to the third embodiment of the present invention. In the present embodiment, in the mobile communication terminal shown in the first embodiment, the transmission / reception unit 10 is provided with a transmission output measurement unit 16 for measuring the transmission output, and the measurement result is supplied to the CPU 3 so that the transmission output is predetermined. When the value is greater than or equal to the value, the frequency control of the operation clock by the frequency converter 13 is executed. Since other configurations and operations are the same as those of the first embodiment, the same configurations and processes as those described in the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate. To do.

  That is, in this embodiment, as shown in the flowchart in FIG. 6, when a data processing request is received, whether or not the data to be processed in step S1 is of a predetermined type, that is, the clock frequency of the arithmetic processing unit 14 is set. Prior to determining whether or not the data can fluctuate low, the CPU 3 determines whether or not the transmission output is greater than or equal to a predetermined value based on the measurement result by the transmission output measurement unit 16 (step S21).

  As a result, when the transmission output does not exceed the predetermined value, the power consumption associated with the transmission output is small and the current consumption of the entire terminal is small. Therefore, in step S2, the frequency conversion unit is used regardless of the type of data to be processed. In step S3, the CPU 3 keeps the maximum clock frequency at which the CPU 3 is at full speed.

  On the other hand, when the transmission output is greater than or equal to the predetermined value, the current consumption of the entire terminal increases. Therefore, in order to efficiently use the necessary power other than the transmission output, as in the first embodiment, the arithmetic processing The frequency conversion unit 13 controls the frequency of the operation clock supplied to each unit of the CPU 3 including the arithmetic processing unit 14 according to the type of data processed by the unit 14, and the process starts in step S3.

  The above operation is repeated while returning to step S21 until the process is completed in step S4. When the process is completed, the process proceeds to the next step and transitions to the sleep mode as necessary.

  As described above, in the present embodiment, the transmission output measurement unit 16 measures the transmission output in the transmission / reception unit 10, and only when the transmission output is equal to or greater than a predetermined value, that is, when the current consumption of the entire terminal increases. Since the frequency control of the operation clock by the frequency conversion unit 13 is executed, the necessary power other than the transmission output can be used efficiently, and the operation time by battery driving with limited power can be extended.

  In addition, when the data to be processed is of a predetermined type, the peak of the battery current can be reduced by controlling the clock frequency to be low by the frequency conversion unit 13, so that the current consumption of the entire terminal is limited. The transmission output can be further increased. Therefore, the portable communication terminal of the present embodiment is, for example, a card type, and operates by receiving power supply from an external device instead of the battery 1, and the maximum power supply from the external device is limited by the interface standard. In some cases, the power on the CPU 3 side can be reduced, and accordingly, the power can be distributed to the transmitting unit side to increase the transmission output, thereby improving the receiving sensitivity on the communication partner side. .

(Fourth embodiment)
FIG. 7 is a functional block diagram showing the configuration of the information processing apparatus according to the fourth embodiment of the present invention. In this embodiment, the mobile communication terminal shown in the first embodiment includes the battery monitoring unit 15 shown in the second embodiment and the transmission output measuring unit 16 shown in the third embodiment. When the battery voltage monitored by the battery monitoring unit 15 is equal to or lower than a predetermined value or when the transmission output measured by the transmission output measuring unit 16 is equal to or higher than the predetermined value even when the battery voltage exceeds the predetermined value, As in the first embodiment, the frequency control of the operation clock by the frequency converter 13 is executed. Since other configurations and operations are the same as those in the above embodiment, the same configurations and processes as those described in the above embodiment are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  That is, in this embodiment, as shown in the flowchart of FIG. 8, when a data processing request is received, first, in step 11, whether the voltage of the battery 1 is lower than a predetermined value based on the monitoring result by the battery monitoring unit 15. Determine whether or not. As a result, when the battery voltage is equal to or lower than a predetermined value, the frequency conversion is performed according to the type of data processed by the arithmetic processing unit 14 as in the first embodiment in order to efficiently use the power of the battery 1. The unit 13 controls the frequency of the operation clock supplied to each unit of the CPU 3 including the arithmetic processing unit 14.

  On the other hand, when the battery voltage exceeds the predetermined value, next, in step S21, it is determined whether or not the transmission output is equal to or higher than the predetermined value based on the measurement result by the transmission output measuring unit 16. As a result, if the transmission output does not exceed the predetermined value, the maximum clock frequency at which the CPU 3 becomes full speed by the frequency conversion unit 13 in step S2, regardless of the type of data to be processed, as in the third embodiment. If the transmission output is greater than or equal to a predetermined value, the frequency conversion unit 13 depends on the type of data to be processed by the arithmetic processing unit 14 as in the first embodiment. Thus, the frequency of the operation clock supplied to each unit of the CPU 3 including the arithmetic processing unit 14 is controlled.

  As described above, in the present embodiment, even when the battery voltage exceeds a predetermined value, if the transmission output is equal to or higher than the predetermined value, the frequency control of the operation clock by the frequency conversion unit 13 is executed. It is possible to further extend the operation time due to the limited battery driving.

  In addition, this invention is not limited only to the said embodiment, Many deformation | transformation or a change is possible. For example, the present invention can be applied not only to a portable information processing apparatus but also to a fixed information processing apparatus and also to an information processing apparatus that does not have a communication function.

It is a functional block diagram which shows the structure of the information processing apparatus which concerns on 1st Embodiment of this invention. It is a flowchart explaining operation | movement of 1st Embodiment. It is a functional block diagram which shows the structure of the information processing apparatus which concerns on 2nd Embodiment of this invention. It is a flowchart explaining operation | movement of 2nd Embodiment. It is a functional block diagram which shows the structure of the information processing apparatus which concerns on 3rd Embodiment of this invention. It is a flowchart explaining operation | movement of 3rd Embodiment. It is a functional block diagram which shows the structure of the information processing apparatus which concerns on 4th Embodiment of this invention. It is a flowchart explaining the operation | movement of 4th Embodiment. It is a figure which shows an example of the relationship between the operating frequency of CPU, and current consumption. It is a figure which shows the general voltage conversion efficiency characteristic of a DC-DC converter.

Explanation of symbols

1 Battery 2 Voltage Converter 3 CPU
DESCRIPTION OF SYMBOLS 4 Memory 5 Display part 6 Imaging part 7 Operation part 8 Clock generation part 9 Antenna 10 Transmission / reception part 11 DC-DC converter 12 Regulator 13 Frequency conversion part 14 Arithmetic processing part 15 Battery monitoring part 16 Transmission output measurement part

Claims (3)

  1. In an information processing apparatus having an arithmetic processing unit that is driven by an output voltage of a DC-DC converter and processes data in synchronization with an operation clock,
    Storage means for storing an output current value at which the voltage conversion efficiency of the DC-DC converter is highest;
    When the data to be processed by the arithmetic processing unit is of a predetermined type, the frequency of the operation clock is set so that the output current value stored in the storage unit is substantially equal to the current consumption value of the arithmetic processing unit. Clock frequency control means for controlling
    An information processing apparatus comprising:
  2. Battery monitoring means for monitoring the remaining battery voltage or voltage;
    The clock frequency control means performs frequency control of the operation clock when the remaining amount or voltage of the battery monitored by the battery monitoring means is a predetermined value or less.
    The information processing apparatus according to claim 1.
  3. Wireless transmission means, and measurement means for measuring the transmission output of the wireless transmission means,
    The clock frequency control means executes frequency control of the operation clock when the transmission output measured by the measurement means is a predetermined value or more.
    The information processing apparatus according to claim 1.
JP2007166536A 2007-06-25 2007-06-25 Information processing device Active JP5138284B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007166536A JP5138284B2 (en) 2007-06-25 2007-06-25 Information processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007166536A JP5138284B2 (en) 2007-06-25 2007-06-25 Information processing device

Publications (2)

Publication Number Publication Date
JP2009003874A true JP2009003874A (en) 2009-01-08
JP5138284B2 JP5138284B2 (en) 2013-02-06

Family

ID=40320164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007166536A Active JP5138284B2 (en) 2007-06-25 2007-06-25 Information processing device

Country Status (1)

Country Link
JP (1) JP5138284B2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05313794A (en) * 1992-05-08 1993-11-26 Citizen Watch Co Ltd Power supply mechanism for computer
JPH10271062A (en) * 1997-03-27 1998-10-09 Nec Shizuoka Ltd Radio portable information terminal
JP2002237886A (en) * 2001-02-09 2002-08-23 Fujitsu Ltd Power saving apparatus and method in portable terminal equipped with display device
JP2003047242A (en) * 2001-07-27 2003-02-14 Sanken Electric Co Ltd Switching power supply apparatus
JP2004032875A (en) * 2002-06-25 2004-01-29 Sony Corp Electronic equipment
JP2004303206A (en) * 2003-03-18 2004-10-28 Matsushita Electric Ind Co Ltd Processor, its driving method, and electronic information processing apparatus
JP2006287345A (en) * 2005-03-31 2006-10-19 Canon Inc Communication device, and power control method

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05313794A (en) * 1992-05-08 1993-11-26 Citizen Watch Co Ltd Power supply mechanism for computer
JPH10271062A (en) * 1997-03-27 1998-10-09 Nec Shizuoka Ltd Radio portable information terminal
JP2002237886A (en) * 2001-02-09 2002-08-23 Fujitsu Ltd Power saving apparatus and method in portable terminal equipped with display device
JP2003047242A (en) * 2001-07-27 2003-02-14 Sanken Electric Co Ltd Switching power supply apparatus
JP2004032875A (en) * 2002-06-25 2004-01-29 Sony Corp Electronic equipment
JP2004303206A (en) * 2003-03-18 2004-10-28 Matsushita Electric Ind Co Ltd Processor, its driving method, and electronic information processing apparatus
JP2006287345A (en) * 2005-03-31 2006-10-19 Canon Inc Communication device, and power control method

Also Published As

Publication number Publication date
JP5138284B2 (en) 2013-02-06

Similar Documents

Publication Publication Date Title
US9413958B2 (en) Method and apparatus for driving camera
KR101796481B1 (en) Method of eliminating shutter-lags with low power consumption, camera module, and mobile device having the same
US9891681B2 (en) Adaptive graphics subsystem power and performance management
EP1460519B1 (en) Processor, driving method thereof, and information processing device
US6704584B2 (en) Mechanism for a wireless device to relinquish its network master status based on its power reserve
JP4834159B2 (en) Portable device with priority-based power saving control and method thereof
KR101193331B1 (en) Power Consumption Management System and Method in the Graphic Apparatus
US9905199B2 (en) Processor for use in dynamic refresh rate switching and related electronic device and method
US6710578B1 (en) Power resource management in a portable communication device
US9105212B2 (en) Method for gradually adjusting screen brightness when switching operating system
JP3776870B2 (en) Information processing apparatus and power saving control method
US8756615B2 (en) Method and electronic device for synchronizing information of dual operating systems and recording medium
JP3623967B2 (en) Portable multimedia communication terminal device
KR100621101B1 (en) Electronic device and control method thereof
CN104599642A (en) Backlight control method and backlight control device
US7411577B2 (en) Mobile display device, mobile display system and image signal reproducing method thereof
US6028631A (en) Portable terminal apparatus for multimedia communication
US9300898B2 (en) Electronic device and control method thereof
JP4444710B2 (en) Image processing apparatus, control method therefor, program, and storage medium
KR100471101B1 (en) Display device and method of controlling the same
US7696641B2 (en) Power supply control circuit and electronic circuit
CN103222254B (en) Portable terminal and communication control method
US7861206B2 (en) System-on-a-chip for processing multimedia data and applications thereof
JP2005032039A (en) Electronic equipment and power supply management/control method for electronic equipment, and power source device
TWI242130B (en) Color adaptation for multimedia devices

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100513

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120605

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120606

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120803

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121016

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121114

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20151122

Year of fee payment: 3