JP2008312140A - Communication apparatus, baseband signal processing device and reception processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication apparatus, baseband signal processing device and reception processing method, wherein a restriction of a duty ratio in an input signal is eliminated and a restriction in costs, substrate area or circuit design can be removed. <P>SOLUTION: A communication apparatus includes a VCTCXO 16, a clock frequency divider circuit 27 for dividing the frequency of a first clock signal (a) from the VCTCXO 16, a phase-locked loop (PLL) section 28 to which a frequency-divided clock signal (b) outputted from the clock frequency divider circuit 27 is inputted and which generates a second clock signal (c) by multiplying the inputted frequency divided clock signal (b) by a predetermined number, and a baseband signal processing section 22 which performs baseband signal processing according to the second clock signal (c) generated by the PLL section 28. The first clock signal (a) and the second clock signal (c) are generated so as to have the equal frequency. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a communication apparatus, a baseband signal processing apparatus, and a reception processing method including a baseband signal processing apparatus that is a device that inputs and outputs data in synchronization with a clock signal.

2. Description of the Related Art Conventionally, a device that inputs / outputs data in synchronization with a clock (CLK) signal, such as a baseband IC, is known. This device has a duty ratio constraint, and all controls are executed in synchronization with the clock signal based on the clock signal supplied from the external device. As described above, since all operate in synchronization with the supplied clock signal, it is inevitable that the duty ratio is restricted due to the logic configuration.
Up to now, by matching with the combination of external devices, it has been possible to connect somehow by design, but it is compatible with high-speed operation, while effectively utilizing the functional assets we have, Some measures were necessary to get the most out of the process.

By realizing the measures, it is possible to maximize the functions at the same cost on the system, which is a great benefit for the user. As an example of the countermeasure, a case of a clock configuration of a mobile phone is shown.
The baseband LSI performs an internal processing operation and outputs an external clock signal, a control signal, and the like in synchronization with a clock signal supplied from a radio frequency (RF) block due to its configuration. Processing such as receiving the data is performed.

As for such a clock signal, “clock control circuit and clock control method” (see Patent Document 1), “automatic meter reading system” (see Patent Document 2), and for duty ratio, “Duty Ratio Variable Circuit and A “duty ratio adjustment circuit” (see Patent Document 3) and “display device and display control software” (see Patent Document 4) are known.
JP 2001-273048 A Japanese Patent No. 00380362 Japanese Patent No. 003772344 JP 2003-066866 A

However, due to the internal configuration of the baseband LSI, there is a duty ratio of 45% to 55% as a restriction on the input signal. Due to this restriction, the selection range of the external device at the time of designing is narrow. In addition, it is necessary to add an additional circuit for shaping the waveform, which is difficult in terms of design.
An object of the present invention is to provide a communication device, a baseband signal processing device, and a reception processing method that can eliminate the restriction on the duty ratio in the input signal and remove the cost, board area, and circuit design restrictions.

In order to achieve the above object, a communication device according to the present invention includes a clock signal source, a clock frequency dividing circuit that divides a first clock from the clock signal source, and a frequency division output from the clock frequency dividing circuit. A transmission circuit that receives a clock and generates a second clock by multiplying the input divided clock by a predetermined number; a baseband signal processing circuit that performs baseband signal processing using the second clock generated by the transmission circuit; It is characterized by including.
In the present invention, it is preferable that the first clock and the second clock are generated so as to have the same frequency.
In the present invention, it is preferable that the first clock is divided by 1 / n (n is a natural number), and the divided clock is multiplied by n to generate the second clock.

In the present invention, it is preferable to execute a predetermined process using a predetermined third clock when the power is turned on.
The baseband signal processing apparatus according to the present invention is a baseband signal processing apparatus that processes a baseband signal using a clock signal output from a clock signal source, and that divides a first clock from the clock signal source. A frequency dividing circuit; a frequency dividing clock output from the clock frequency dividing circuit; a transmission circuit that generates a second clock by multiplying the input frequency divided clock by a predetermined frequency; and a first frequency generated by the transmission circuit. And a baseband signal processing circuit that performs baseband signal processing with two clocks.

  According to another aspect of the present invention, there is provided a reception processing method in which a baseband signal is processed by a clock signal output from a clock signal source, a step of dividing a first clock from the clock signal source, and the division The method includes a step of generating a second clock by multiplying the clock thus multiplied by a predetermined time, and a step of performing baseband signal processing using the second clock.

  According to the present invention, it is possible to remove the restriction on the duty ratio in the input signal, and to remove the restrictions on the cost, the board area, and the circuit design.

The best mode for carrying out the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram showing a system configuration of a communication apparatus according to an embodiment of the present invention. Here, a mobile phone will be described as an example of the communication device.
As shown in FIG. 1, a cellular phone (communication device) 10 is connected to an ASIC (Application Specific Integrated Circuit) unit 11 that processes an input signal, and the ASIC unit 11, and holds data processed by the ASIC unit 11. It has an SDRAM (Synchronous Dynamic Random Access Memory) 12 and a FLASH (Flash Memory) 13 in which program information is stored.

  Further, the mobile phone 10 includes an RF transmitter / receiver 15 that transmits / receives a signal to / from a base station (not shown) via an antenna 14, a voltage-controlled temperature-compensated crystal oscillator (VCTCXO) 16, a liquid crystal display Section (Liquid Crystal Display: LCD) 17, codec section 18 for performing A / D (Analog-Digital) / DA conversion of audio signals, speaker 19 and microphone 20 for telephone, and key input for user input of information Part 21.

  The ASIC unit 11 includes a baseband signal processing unit 22 that modulates and demodulates an input signal, a CPU (Central Processing Unit) 23 that controls signals in the ASIC unit 11, a system control unit 24 that controls the SDRAM 12 and the FLASH 13, And a clock control unit 25. Here, the baseband signal processing unit 22 and the clock control unit 25 constitute a baseband signal processing device. A program required for driving the ASIC unit 11 is expanded from the FLASH 13 to the SDRAM 12 and stored when the mobile phone 10 is powered on (at the initial time).

  FIG. 2 is a block diagram showing a configuration of the clock control unit of FIG. As shown in FIG. 2, the clock control unit 25 includes a multiplexer 26, a clock frequency dividing circuit 27, and a phase-locked loop (PLL) unit 28 that is a transmission circuit, and performs a clock setting process described below. Execute.

  The clock signal CLKIN (20 MHz or 24 MHz) output from the VCTCXO 16 as the clock signal source is dividedly input to the clock control unit 25, and the multiplexer 26 collects the divided input clock signals CLKIN into one, Output to the peripheral circuit 27. The clock frequency divider circuit 27 divides the first clock signal a input from the multiplexer 26 from the VCTCXO 16 into 1 / n (n is a natural number) and outputs the result.

  The PLL unit 28 receives the frequency-divided clock signal b that has been frequency-divided and output from the clock frequency-dividing circuit 27, and thereby multiplies the frequency-divided clock signal b that has been input by a predetermined multiple to generate a second clock signal (second signal). Clock) c is generated. At the time of generation, the first clock signal a and the second clock signal b are set to have the same frequency. That is, the first clock signal (for example, 24 MHz) from the VCTCXO 16 is divided by, for example, ½ by the clock frequency dividing circuit 27 to become the divided clock signal b (12 MHz), and the divided clock signal b is In the PLL unit 28, for example, it is multiplied by 2 to become the second clock signal c (24 MHz).

The second clock signal c is output from the PLL unit 28 and input to the baseband signal processing unit 22 and the CPU 23. The baseband signal processing unit 22 performs baseband signal processing using the second clock signal c generated by the PLL unit 28, and the CPU 23 controls the overall operation of the baseband signal processing unit 22 using the second clock signal c. .
FIG. 3 is a conceptual explanatory diagram illustrating the setting of the clock signal by the clock control unit of FIG. As shown in FIG. 3, the clock control unit 25 receives a second clock signal c that is an output signal from a register (REG) 30 that is a data holding circuit and is connected to an AHB (Advanced High-performance Bus) 29. Switching control is performed.

  The clock signal CLKIN (20 MHz or 24 MHz) input to the clock control unit 25 is frequency-divided by 1 / n (n is a natural number) by the clock frequency dividing circuit 27 and then output as the frequency-divided clock signal b. Here, for example, when CLKIN is 20 MHz, n = 5, and when CLKIN is 24 MHz, n = 6.

  The frequency-divided clock signal b output from the clock frequency dividing circuit 27 is input to the PLL unit 28, and is multiplied by a predetermined time by the PLL unit 28. For example, when CLKIN is 20 MHz, the divided clock signal b divided by 1/5 is multiplied by 5 times to 20 MHz, 6 times to 24 MHz, and 18 times to 72 MHz and 48 times. 192 MHz, and then output as the second clock signal c. For example, when CLKIN is 24 MHz, the divided clock signal b divided by 1/6 is multiplied by 5 times to 20 MHz, multiplied by 6 times to 24 MHz, and multiplied by 18 times to 72 MHz, 48 times. To 192 MHz and then output as the second clock signal c.

Note that the clock signal (including 32 KHz) employed by the CPU 23 is input to the register 30.
As described above, the clock control unit 25 receives the clock dividing circuit 27 that divides the first clock signal a from the VCTCXO 16 and the divided clock signal b that is output from the clock dividing circuit 27. And a PLL unit that generates the second clock signal c by multiplying the divided clock signal b by a predetermined number.

Next, a reception processing method in the mobile phone in FIG. 1 will be described.
First, the first clock signal a input from the VCTCXO 16 serving as the clock signal source is frequency-divided by the clock frequency dividing circuit 27 to obtain a frequency-divided clock signal b. Next, the divided clock signal b is multiplied by a predetermined factor by the PLL unit 28 to generate the second clock signal c. Next, the second clock signal c is input to the baseband signal processing unit 22, and baseband signal processing is performed using the second clock signal c. As a result, reception processing is performed in which the baseband signal is processed by the clock signal output from the clock signal source.

As described above, the clock frequency supplied from the VCTCXO 16 that is an external device is once divided, and then multiplied by using the PLL unit 28, so that the restriction due to the duty ratio so far can be removed.
Until now, since the supplied clock frequency was used for the logic of the baseband processing, there was a restriction due to the duty ratio. However, once the input clock frequency is divided, there is no restriction due to the duty ratio. After that, the divided clock frequency is multiplied to the original clock frequency by the PLL unit 28, thereby eliminating the restriction of the duty ratio. By further multiplying using the PLL unit 28, the synchronization frequency required for the internal circuit is obtained. Secure.

The simple configuration as in the above embodiment not only eliminates the restriction due to the duty ratio, but also supports the conventional configuration without changing it. Since it is not necessary, cost reduction can be effective.
As an example of the system configuration, i-BURST (registered trademark) is shown. In the case of i-BURST (registered trademark), a high frequency is required on the system, and a clock frequency of 24 MHz is required to supply a clock frequency that requires the baseband unit MODEM function processing, or to execute CPU and CPU peripheral processing. Supply was necessary.

The clock frequency of 24 MHz is multiplied to create a clock frequency of 72 MHz, and the generated clock frequency of 72 MHz is positioned as a system clock together with the input clock frequency of 24 MHz. It has been realized.
When executing baseband management and operation support, high-speed CPU processing is indispensable, and a CPU executing baseband management and operation support cannot be processed unless it is operated at least at a clock frequency of 72 MHz. This is one of the factors that require high performance.

On the other hand, a clock frequency of 24 MHz is supplied from the outside, and this is supplied from a voltage controlled temperature guaranteed crystal oscillator (VCTCXO). This signal is also used for exchanging with a base station (BS) in the system, and may be compatible with an operation with a clock frequency of 20 MHz by RF block (RF transceiver) processing. It was requested.
This VCTCXO originally has a duty ratio of 45% to 55%, and it is desirable to realize this with a duty ratio of 45% to 55% up to the baseband processing IC while maintaining this, and in addition, the adopted duty ratio of 45% It was necessary to maintain ~ 55%. There are VCTCXOs with better duty ratios, but they are expensive.

In such a situation, in order to realize a duty ratio of 45% to 55%, a simulation is performed with an external device to satisfy the specifications. However, there is no problem at room temperature, but when the temperature change is taken into consideration, the duty ratio is not satisfactory, and the design is difficult. Further, the voltages of the baseband processing IC and the RF control IC are also different, and the duty ratio is in the direction of further collapse.
In designing, when selecting a device that satisfies the specifications in the system, it was necessary to remove the constraint on the duty ratio of the VCTCXO without increasing the cost. In addition, it is desirable to perform baseband processing by directly connecting a VCTCXO in order to prevent an increase in cost in terms of design, but in this case as well, due to physical restrictions, it is naturally assumed that the duty ratio collapses, Depending on the temperature conditions, there is no guarantee that the constraints can be satisfied.

Therefore, for example, the clock frequency of 24 MHz is divided by half to generate the clock frequency of 12 MHz, and the clock frequency is multiplied by 2 to generate the clock frequency of 24 MHz. This clock frequency is used for the internal configuration of the system LSI. Use the clock source. Alternatively, the clock frequency 24 MHz is divided by 1/4 and then multiplied by 12 to generate the clock frequency 72 MHz, and further the clock frequency 72 MHz is divided by 1/3 to generate the clock frequency 24 MHz. In FIG. 2, it is described as 1 / n.
By generating the clock frequency in this way, design restrictions can be removed, and additional components can be costly increased, the board area can be increased, and waveform distortion due to temperature can be eliminated. There is also a method of multiplying the external clock frequency to 48 MHz and dividing it by half, but in this case, it is not desirable because of the large current consumption, and it is also considered that the development assets so far cannot be used. It is done.

As a result, the following effects can be obtained. It can be executed with a simple configuration by hardware. By forming a simple connection with such a mechanism and providing it on the hardware side, there is no problem even when the waveform collapses. In addition, it is possible to select and use inexpensive devices, and there is little risk. Until now, the external PLL has been divided after being multiplied due to the configuration, so that there is always a restriction due to the duty ratio in using the PLL circuit (PLL IC), but the restriction has been removed. There is no such configuration example even with an external PLL, and a PLL having such a configuration is also possible, so there is room for improvement in the device. In addition, when supporting source oscillation, the supply of a clock frequency of 32 KHz is supported and selectable by register setting, as is possible by CPU setting.
When the power is turned on, in order to create a source oscillation, for example, register setting (predetermined processing) and selection by the CPU 23 using a 32K clock (a predetermined third clock) are essential. Such processing at power-on is performed by the clock controller 25.

  In other words, it is possible to eliminate the duty constraint without changing the existing system with only a simple hardware configuration and connection configuration, and it is not necessary to search for another device, and the time, hardware and software development associated therewith is not required. The development time can be shortened because no effort is required. Further, the cost can be reduced, the substrate area required conventionally is not required, the range of device selection is widened, and further, no external circuit or device is required. In addition, when designing, it is not necessary to consider the peripheral related parts due to the duty ratio restriction, and it is not necessary to consider the influence of temperature.

  Although the present invention has been described with reference to the above-described embodiment, it is not limited to this embodiment. Therefore, what is implemented as a change aspect without deviating from the meaning of the present invention is also included. For example, the present invention is not limited to a mobile phone, and can be applied to a mobile terminal device other than a mobile phone.

It is a block diagram which shows the system configuration | structure of the communication apparatus which concerns on one embodiment of this invention. It is a block diagram which shows the structure of the clock control part of FIG. FIG. 3 is a conceptual explanatory diagram illustrating setting of a clock signal by a clock control unit in FIG. 2.

Explanation of symbols

10 cellular phone 11 ASIC unit 12 SDRAM
13 FLASH
14 Antenna 15 RF Transmitter / Receiver 16 VCTCXO
17 LCD
18 Codec part 19 Speaker 20 Microphone 21 Key input part 22 Baseband signal processing part 23 CPU
24 System Control Unit 25 Clock Control Unit 26 Multiplexer 27 Clock Divider 28 PLL Unit 29 AHB
30 Register a First clock signal b Divided clock signal c Second clock signal

Claims (6)

A clock signal source;
A clock divider circuit for dividing a first clock from the clock signal source;
A transmission circuit that receives the frequency-divided clock output from the clock frequency-dividing circuit and generates the second clock by multiplying the input frequency-divided clock by a predetermined amount;
A baseband signal processing circuit that performs baseband signal processing using the second clock generated by the transmission circuit;
A communication device comprising:   The communication apparatus according to claim 1, wherein the first clock and the second clock are generated so as to have the same frequency.   3. The communication apparatus according to claim 2, wherein the first clock is divided by 1 / n (n is a natural number), and the divided clock is multiplied by n to generate the second clock.   The communication apparatus according to any one of claims 1 to 3, wherein when the power is turned on, a predetermined process is executed using a predetermined third clock. In a baseband signal processing apparatus that processes a baseband signal using a clock signal output from a clock signal source,
A clock divider circuit for dividing a first clock from the clock signal source;
A transmission circuit that receives the frequency-divided clock output from the clock frequency-dividing circuit and generates the second clock by multiplying the input frequency-divided clock by a predetermined amount;
A baseband signal processing apparatus comprising: a baseband signal processing circuit that performs baseband signal processing using the second clock generated by the transmission circuit. In a reception processing method for processing a baseband signal using a clock signal output from a clock signal source,
Dividing the first clock from the clock signal source;
Generating a second clock by multiplying the divided clock by a predetermined number;
Performing baseband signal processing with the second clock;
A reception processing method comprising:

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