JP2008294008A - Thin film capacitor and method for manufacturing same - Google Patents

Thin film capacitor and method for manufacturing same Download PDF

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JP2008294008A
JP2008294008A JP2005206943A JP2005206943A JP2008294008A JP 2008294008 A JP2008294008 A JP 2008294008A JP 2005206943 A JP2005206943 A JP 2005206943A JP 2005206943 A JP2005206943 A JP 2005206943A JP 2008294008 A JP2008294008 A JP 2008294008A
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thin film
conductor
conductor layer
substrate
capacitor
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Yutaka Takeshima
裕 竹島
Masanobu Nomura
雅信 野村
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to PCT/JP2006/311306 priority patent/WO2007010681A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film capacitor having such a constitution that even when a stress occurs in a bump in the vertical direction, the stress does not concentrate on a conductor, the stress occurring owing to the difference in the coefficient of linear expansion between a substrate of the thin film capacitor and a mounted substrate. <P>SOLUTION: The thin film capacitor includes: a capacitor unit having the substrate 10, a first conductor layer 22 formed on the substrate, a dielectric thin film 23 formed on the first conductor layer, and a second conductor layer 24 formed on the dielectric thin film while electrically insulated from the first conductor layer; a first conductor pad 41 which is electrically connected with the first conductor layer and led out onto the top surface of the capacitor unit; a second conductor pad 42 which is electrically connected with the second conductor layer and also led out onto the top surface of the capacitor unit; and first and second bumps respectively formed on the first conductor pad and the second conductor pad, wherein the first and second conductor pads are joined to the substrate. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は薄膜キャパシタに関し、より詳しくは集積回路のデカップリング用などに使用される薄膜キャパシタに関する。   The present invention relates to a thin film capacitor, and more particularly to a thin film capacitor used for decoupling an integrated circuit.

近年、ＬＳＩ（大規模集積回路）の処理速度の高速化により、デカップリングキャパシタが用いられるようになっている。デカップリングキャパシタの高周波追随性能を向上させるためには、デカップリングキャパシタとＬＳＩとの間のインダクタンスが低いことが要求されるため、ＬＳＩの直下にデカップリングキャパシタを配し、バンプによってデカップリングキャパシタとＬＳＩを接続することが行われている。   In recent years, a decoupling capacitor has been used due to an increase in processing speed of an LSI (Large Scale Integrated Circuit). In order to improve the high frequency tracking performance of the decoupling capacitor, it is required that the inductance between the decoupling capacitor and the LSI is low. Therefore, a decoupling capacitor is arranged directly under the LSI, and the decoupling capacitor and the LSI are separated by bumps. An LSI is connected.

係る形態のデカップリング用に用いられる薄膜キャパシタとして、例えば特許文献１に記載された薄膜キャパシタがある。この薄膜キャパシタについて、図６を参照して説明する。   As a thin film capacitor used for decoupling in such a form, there is a thin film capacitor described in Patent Document 1, for example. This thin film capacitor will be described with reference to FIG.

薄膜キャパシタ１００は、基板１０１上に順に形成された下部導体１０２、誘電体薄膜１０３、上部導体１０４を有している。そして、下部導体１０２および上部導体１０４にはそれぞれ導体パッド１０７ａ，１０７ｂが接続されていて、その上にはＬＳＩや実装基板などとの電気的接続のためのバンプ１０８ａ，１０８ｂが形成されている。さらに、バンプ１０８ａ，１０８ｂからの機械的応力を緩和するためにポリイミド等の樹脂材からなる保護絶縁層１０６が設けられるとともに、キャパシタ部（下部導体１０２、誘電体薄膜１０３および上部導体１０４）と保護絶縁層１０６との間に非導電性無機質材料からなるバリア層１０５を設けることによって、ポリイミドの硬化時に起こる脱水縮合反応によって放出されるＨ2Ｏが分解されて生じる水素イオンが誘電体薄膜１０３に悪影響を及ぼすことを防止している。
特開２００４−２１４５８９号公報 The thin film capacitor 100 includes a lower conductor 102, a dielectric thin film 103, and an upper conductor 104 that are sequentially formed on a substrate 101. Conductor pads 107a and 107b are connected to the lower conductor 102 and the upper conductor 104, respectively, and bumps 108a and 108b for electrical connection with an LSI, a mounting substrate, and the like are formed thereon. Further, a protective insulating layer 106 made of a resin material such as polyimide is provided to relieve mechanical stress from the bumps 108a and 108b, and the capacitor portion (the lower conductor 102, the dielectric thin film 103 and the upper conductor 104) is protected. By providing a barrier layer 105 made of a non-conductive inorganic material between the insulating layer 106, hydrogen ions generated by decomposition of H 2 O released by a dehydration condensation reaction that occurs at the time of curing of the polyimide are generated in the dielectric thin film 103. Preventing adverse effects.
JP 2004-214589 A

特許文献１に記載された発明では、バンプからの機械的応力を緩和するために保護絶縁層を設けている。この保護絶縁層は、バンプに対する水平方向（基板の主面に平行な方向、図の横方向）の応力に対しては緩衝材として一定の有効性があるものの、鉛直方向（基板の主面に垂直な方向、図の縦方向）の成分を有する応力に対しての緩衝効果は必ずしも十分ではない。   In the invention described in Patent Document 1, a protective insulating layer is provided to relieve mechanical stress from the bumps. This protective insulating layer has a certain effectiveness as a cushioning material against the stress in the horizontal direction (the direction parallel to the main surface of the substrate, the horizontal direction in the figure) with respect to the bump, but the vertical direction (on the main surface of the substrate). The buffering effect against stress having a component in the vertical direction (vertical direction in the figure) is not always sufficient.

ここで、バンプに対して鉛直方向の成分を有する応力が働くメカニズムについて説明すると、薄膜キャパシタに通常用いられるＳｉ基板の線膨張係数は２〜３ｐｐｍ／℃であるが、樹脂多層基板の線膨張係数は数十ｐｐｍ／℃程度とＳｉ基板の線膨張係数と比較してかなり大きいため、樹脂多層基板に薄膜キャパシタを実装して温度変化が起こると、基板の線膨張係数の違いによってどちらかの基板に反りが発生する。   Here, the mechanism by which a stress having a component in the vertical direction acts on the bump will be described. The linear expansion coefficient of a Si substrate usually used for a thin film capacitor is 2 to 3 ppm / ° C. Is about several tens of ppm / ° C, which is considerably larger than the linear expansion coefficient of the Si substrate. When a thin film capacitor is mounted on a resin multilayer substrate and temperature changes, one of the substrates will differ depending on the difference in the linear expansion coefficient of the substrate. Warping occurs.

Ｓｉ基板と樹脂基板のいずれが反るかは基板の厚みやヤング率によって決定されるが、例えばＳｉ基板のほうが相対的に変形しやすい場合において、はんだバンプを用いて実装を行ったあとに冷却すると、樹脂基板のほうが相対的に大きく収縮するため薄膜キャパシタはバンプが形成されていない側の面を凸にして変形する。このような変形が生じると、中央付近に形成されているバンプには大きな引っ張り応力が生じる。一方、樹脂基板のほうが相対的に変形しやすい場合には、冷却時に樹脂基板は薄膜キャパシタが実装されていない側の面を凹として変形するので、外側のバンプに大きな引っ張り応力が生じる。   Whether the Si substrate or the resin substrate is warped is determined by the thickness and Young's modulus of the substrate. For example, when the Si substrate is more easily deformed, cooling is performed after mounting using solder bumps. Then, since the resin substrate contracts relatively larger, the thin film capacitor is deformed with the surface on which the bump is not formed being convex. When such deformation occurs, a large tensile stress is generated in the bump formed near the center. On the other hand, when the resin substrate is relatively easily deformed, the resin substrate is deformed with a concave surface on the side where the thin film capacitor is not mounted during cooling, so that a large tensile stress is generated on the outer bump.

ここで図６においてバンプ１０８ｂに図の上方向の引っ張り応力が発生すると、バンプ１０８ｂと導体パッド１０７ｂとの界面および導体パッドと上部導体１０４ｂとの界面の接合強度は相対的に強いため、上部導体が上方向に引っ張られる。そして上部導体と誘電体薄膜とは材質の違いにより（上部導体は金属であるのに対して、誘電体薄膜は酸化物であるため）界面の接合強度が相対的に弱く、引っ張り応力は誘電体薄膜には伝わりにくい。その結果、上部導体に引っ張り応力が集中して上部導体の破断が発生したり、上部導体と誘電体薄膜との界面に剥離が生じてキャパシタとしての機能が著しく損なわれることがあった。また、界面に剥離が生じないまでも、界面に引っ張り応力が集中した状態ではキャパシタとしての信頼性に悪影響を及ぼす。   Here, when an upward tensile stress is generated in the bump 108b in FIG. 6, the bonding strength at the interface between the bump 108b and the conductor pad 107b and the interface between the conductor pad and the upper conductor 104b is relatively strong. Is pulled upward. Due to the difference in material between the upper conductor and the dielectric thin film (because the upper conductor is a metal whereas the dielectric thin film is an oxide), the bonding strength at the interface is relatively weak, and the tensile stress is the dielectric Hard to be transmitted to thin film. As a result, tensile stress concentrates on the upper conductor and the upper conductor breaks, or peeling occurs at the interface between the upper conductor and the dielectric thin film, which may significantly impair the function as a capacitor. In addition, even if no peeling occurs at the interface, the reliability as a capacitor is adversely affected in the state where tensile stress is concentrated on the interface.

引っ張り応力の原因となる基板の反りはバンプの材料としてリフロー温度が高い無鉛はんだを用いた場合に特に顕著であり、近年は環境への影響性に配慮して無鉛はんだの使用が増加していることから、係る問題点への対応は喫緊の課題である。   The warpage of the board that causes tensile stress is particularly noticeable when lead-free solder with a high reflow temperature is used as the bump material. In recent years, the use of lead-free solder has increased in consideration of environmental impact. Therefore, dealing with such problems is an urgent issue.

なお、上記では樹脂基板上に薄膜キャパシタを実装した場合を例にとって説明したが、セラミック基板上に実装した場合でも同様の問題が生じる。セラミック基板は線膨張係数が樹脂基板よりも小さいがヤング率は高いため、結局バンプに大きな引っ張り応力が発生することに変わりはない。   In the above description, the case where the thin film capacitor is mounted on the resin substrate has been described as an example, but the same problem occurs even when the thin film capacitor is mounted on the ceramic substrate. The ceramic substrate has a smaller coefficient of linear expansion than the resin substrate, but has a higher Young's modulus, so that a large tensile stress is generated in the bumps.

また、薄膜キャパシタの基板としてサファイア基板（線膨張係数およそ８ｐｐｍ／℃）や石英ガラス基板（線膨張係数およそ０．５ｐｐｍ／℃）などを使用した場合にも、実装基板との線膨張係数の差があるので上記の問題が発生する。   Even when a sapphire substrate (linear expansion coefficient of about 8 ppm / ° C.) or a quartz glass substrate (linear expansion coefficient of about 0.5 ppm / ° C.) is used as a thin film capacitor substrate, the difference in linear expansion coefficient from the mounting substrate This causes the above problem.

本発明は上記の問題に鑑みてなされたものであり、バンプに働く鉛直方向の応力が導体に集中しない構造を有する薄膜キャパシタを提供するとともに、その製造方法を提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a thin film capacitor having a structure in which a vertical stress acting on a bump does not concentrate on a conductor, and a manufacturing method thereof.

上記問題点を解決するために本発明の薄膜キャパシタは、基板と、該基板上に形成された第１の導体層と、該第１の導体層上に形成された誘電体薄膜と、該誘電体薄膜上に前記第１の導体層と電気的に絶縁されて形成された第２の導体層と、を有するキャパシタ部と、前記第１の導体層に電気的に接続するとともに前記キャパシタ部の上面に引き出さるように形成された第１の導体パッドと、前記第２の導体層に電気的に接続するとともに前記キャパシタ部の上面に引き出されるように形成された第２の導体パッドと、前記第１および第２の導体パッド上それぞれに形成された第１および第２のバンプと、を備え、前記第１および前記第２の導体パッドは前記基板に接合されていることを特徴とする。   In order to solve the above problems, a thin film capacitor of the present invention includes a substrate, a first conductor layer formed on the substrate, a dielectric thin film formed on the first conductor layer, and the dielectric A capacitor portion having a second conductor layer formed on the body thin film so as to be electrically insulated from the first conductor layer, and electrically connected to the first conductor layer and of the capacitor portion A first conductor pad formed so as to be drawn to the upper surface; a second conductor pad electrically connected to the second conductor layer and drawn to the upper surface of the capacitor unit; and First and second bumps formed on the first and second conductor pads, respectively, wherein the first and second conductor pads are bonded to the substrate.

第１および第２の導体パッドが基板に接合されていることにより、バンプに鉛直方向に引っ張り応力が生じた場合でも、この応力が第１あるいは第２の導体層に集中することはなく、第１あるいは第２の導体層の破断や界面の剥離が生じない。   Since the first and second conductor pads are bonded to the substrate, even if a tensile stress is generated in the vertical direction on the bump, this stress is not concentrated on the first or second conductor layer. No breakage of the first or second conductor layer or peeling of the interface occurs.

前記誘電体薄膜は、平坦な面上に形成されていることが好ましい。誘電体薄膜が段差上に形成されていると、段差部分で欠陥が生じやすく、信頼性の低下を生じるからである。   The dielectric thin film is preferably formed on a flat surface. This is because if the dielectric thin film is formed on the step, defects are likely to occur at the step portion, resulting in a decrease in reliability.

また、本発明に係る薄膜キャパシタの製造方法は、基板上に第１の導体層を形成する工程と、前記第１の導体層上に、金属の有機化合物を含有する誘電体原料溶液を塗布して熱処理を行い、誘電体薄膜を形成する工程と、前記誘電体薄膜上に第２の導体層を形成する工程と、前記第１および第２の導体層と前記誘電体薄膜を貫通し、前記基板を底面とする複数の貫通孔を形成する工程と、前記貫通孔のうちいずれかの内部に、前記第１の導体層と電気的に接続し前記第２の導体層と電気的に絶縁され、前記基板に接合された第１の導体パッドを形成する工程と、前記貫通孔のうちいずれかの内部に、前記第２の導体層と電気的に接続し前記第１の導体層と電気的に絶縁され、前記基板に接合された第２の導体パッドを形成する工程と、前記第１および第２の導体パッド上に、それぞれ第１および第２のバンプを形成する工程と、を有することを特徴とする。   The method of manufacturing a thin film capacitor according to the present invention includes a step of forming a first conductor layer on a substrate, and applying a dielectric material solution containing a metal organic compound on the first conductor layer. Performing a heat treatment to form a dielectric thin film; forming a second conductor layer on the dielectric thin film; penetrating the first and second conductor layers and the dielectric thin film; Forming a plurality of through holes having a substrate as a bottom surface, and electrically connecting to the first conductor layer and being electrically insulated from the second conductor layer in any one of the through holes; Forming a first conductor pad bonded to the substrate; and electrically connecting to the second conductor layer and electrically connecting to the first conductor layer in any one of the through holes. Forming a second conductor pad that is insulated by and bonded to the substrate; and And on the second conductor pad, forming first and second bumps respectively, and having a.

このように製造することにより、第１および第２の導体パッドが基板に接合されることとなり、バンプに鉛直方向に引っ張り応力が生じた場合でも、この応力が第１あるいは第２の導体層に集中することはなく、第１あるいは第２の導体層の破断や界面の剥離が生じない。   By manufacturing in this way, the first and second conductor pads are bonded to the substrate, and even if a tensile stress is generated in the vertical direction on the bump, this stress is applied to the first or second conductor layer. There is no concentration, and no breakage of the first or second conductor layer or peeling of the interface occurs.

以上において説明したように、本発明によれば、第１および第２の導体パッドが基板に接合されて形成されているので、バンプに鉛直方向に引っ張り応力が生じた場合でも、この応力が第１あるいは第２の導体層に集中することはなく、第１あるいは第２の導体層の破断や界面の剥離が生じない。   As described above, according to the present invention, the first and second conductor pads are formed by being bonded to the substrate. Therefore, even if a tensile stress is generated in the vertical direction on the bump, the stress is It does not concentrate on the first or second conductor layer, and the first or second conductor layer does not break or peel off at the interface.

以下において添付図面を参照しつつ本発明を実施するための最良の形態について説明する。   The best mode for carrying out the present invention will be described below with reference to the accompanying drawings.

図１（ａ）は本発明に係る薄膜キャパシタを示す平面図であり、図１（ｂ）は図１（ａ）におけるＡ−Ａ線断面の一部を示す断面図である。   FIG. 1A is a plan view showing a thin film capacitor according to the present invention, and FIG. 1B is a cross-sectional view showing a part of a cross section taken along line AA in FIG.

本発明の薄膜キャパシタは、Ｓｉからなる基板１０と、基板１０上に順に形成された密着層２１、第１の導体層２２、誘電体薄膜２３、第２の導体層２４を備えるとともに、基板１０に直接接合するように形成された第１および第２の導体パッド４１，４２を備えている。第１および第２の導体パッド４１，４２上には外部の回路と接続するためにバンプ５１，５２が形成されている。また、樹脂材料からなる第１および第２の保護層３３，３４が形成されている。第１および第２の保護層３３，３４とキャパシタ部（第１および第２の導体層２２，２４と誘電体薄膜２３）との間には、結晶質の金属酸化物からなる第１のバリア層３１と、非導電性の無機質材料からなる第２のバリア層３２とが形成されている。第１および第２のバリア層３１，３２は、第１および第２の保護層３３，３４とキャパシタ部との間でバリア機能を果たすとともに、キャパシタ部内部での絶縁層の機能を兼ねている。   The thin film capacitor of the present invention includes a substrate 10 made of Si, an adhesion layer 21, a first conductor layer 22, a dielectric thin film 23, and a second conductor layer 24 formed in order on the substrate 10. The first and second conductor pads 41 and 42 are formed so as to be directly bonded to each other. Bumps 51 and 52 are formed on the first and second conductor pads 41 and 42 to connect to external circuits. Further, first and second protective layers 33 and 34 made of a resin material are formed. A first barrier made of a crystalline metal oxide is provided between the first and second protective layers 33 and 34 and the capacitor portion (the first and second conductor layers 22 and 24 and the dielectric thin film 23). A layer 31 and a second barrier layer 32 made of a nonconductive inorganic material are formed. The first and second barrier layers 31 and 32 serve as a barrier function between the first and second protective layers 33 and 34 and the capacitor portion, and also serve as an insulating layer inside the capacitor portion. .

第１の導体パッド４１は側面が第１の導体層２２と接続しており、第２の導体層３４とは第１および第２のバリア層３１，３２によって電気的に絶縁されている。第２の導体パッド４２は第２の導体層２４に接続するとともに、第１の導体層２２とは第１および第２のバリア層３１，３２によって電気的に絶縁されている。ここで、第２の導体パッド４２と第２の導体層２４の接続状態についてより詳しく説明すると、第２の導体層２４上に形成されている第１および第２のバリア層３１，３２は第２の導体層２４の表面を底面とする孔を有しており、この孔を覆うように第２の導体パッド４２が形成されることにより、孔の底部において第２の導体層２４と第２の導体パッド４２とが接続されている。このとき、孔はバンプ５２の直下を避けて形成されているので、バンプ５２に鉛直方向の引っ張り応力が加わっても、引っ張り応力が直接的に第２の導体層２４に加わることがない。   The side surface of the first conductor pad 41 is connected to the first conductor layer 22, and the first conductor pad 41 is electrically insulated from the second conductor layer 34 by the first and second barrier layers 31 and 32. The second conductor pad 42 is connected to the second conductor layer 24 and is electrically insulated from the first conductor layer 22 by the first and second barrier layers 31 and 32. Here, the connection state between the second conductor pad 42 and the second conductor layer 24 will be described in more detail. The first and second barrier layers 31 and 32 formed on the second conductor layer 24 are the first and second barrier layers 31 and 32. 2 has a hole whose bottom surface is the surface of the second conductor layer 24, and the second conductor pad 42 is formed so as to cover the hole, whereby the second conductor layer 24 and the second conductor layer 24 are formed at the bottom of the hole. The conductive pads 42 are connected. At this time, since the hole is formed so as to avoid a position directly below the bump 52, even if a tensile stress in the vertical direction is applied to the bump 52, the tensile stress is not directly applied to the second conductor layer 24.

本発明はこのように第１および第２の導体パッド４１，４２が基板１０に接合されて形成されているので、バンプ５１，５２に鉛直方向に引っ張り応力が生じた場合でも、この応力が第１あるいは第２の導体層２２，２４に集中することはなく、第１あるいは第２の導体層２２，２４の破断や界面の剥離が生じない。   In the present invention, since the first and second conductor pads 41 and 42 are bonded to the substrate 10 as described above, even when a tensile stress is generated in the vertical direction on the bumps 51 and 52, the stress is not reduced. There is no concentration on the first or second conductor layers 22, 24, and the first or second conductor layers 22, 24 do not break or peel off at the interface.

ここで、図２ないし図４を参照して、この薄膜キャパシタの製造方法について説明する。まず、図２（ａ）に示すように、表面に厚さ０．７μｍの熱酸化膜（ＳｉＯ2膜、図示を省略）が形成されたＳｉ単結晶からなる基板１０を用意し、Ｂａ，Ｓｒ，Ｔｉの有機化合物を含有する（Ｂａ，Ｓｒ）ＴｉＯ3（ＢＳＴ）のＭＯＤ原料溶液を基板１０上に塗布して乾燥させ、酸素中で６２５℃の熱処理を行って膜厚５０ｎｍの密着層２１を形成した。次に密着層２１上にスパッタ法によって膜厚２００ｎｍのＰｔからなる第１の導体層２２を形成した。さらに第１の導体層２２上に前記のＭＯＤ原料溶液を塗布、乾燥させて酸素中６２５℃で３０分間の熱処理を行って誘電体薄膜２３を形成した。誘電体薄膜２３の膜厚は１００ｎｍとなるように形成した。誘電体薄膜２３上にスパッタ法で膜厚２００ｎｍのＰｔからなる第２の導体層２４を形成した。 Here, with reference to FIG. 2 thru | or FIG. 4, the manufacturing method of this thin film capacitor is demonstrated. First, as shown in FIG. 2A, a substrate 10 made of Si single crystal having a surface formed with a thermal oxide film (SiO 2 film, not shown) having a thickness of 0.7 μm is prepared, and Ba, Sr A MOD raw material solution of (Ba, Sr) TiO 3 (BST) containing an organic compound of Ti, Ti is applied onto the substrate 10 and dried, and then heat-treated at 625 ° C. in oxygen to form an adhesion layer 21 having a thickness of 50 nm. Formed. Next, a first conductor layer 22 made of Pt having a thickness of 200 nm was formed on the adhesion layer 21 by sputtering. Further, the MOD raw material solution was applied onto the first conductor layer 22 and dried, followed by heat treatment in oxygen at 625 ° C. for 30 minutes to form a dielectric thin film 23. The film thickness of the dielectric thin film 23 was formed to be 100 nm. A second conductor layer 24 made of Pt having a thickness of 200 nm was formed on the dielectric thin film 23 by sputtering.

このとき、誘電体薄膜２３は基板１０上の略全面に形成された第１の導体層２２上に形成されているので、実質的に段差のない平坦面上に形成されていることになる。ＭＯＤ法によって誘電体薄膜２３を形成する場合、段差部分の被覆性が必ずしも良好ではなく、段差部分でショートやリーク電流の発生を招きやすい。よって、誘電体薄膜２３は平坦面上に形成することがプロセス上好ましい。   At this time, since the dielectric thin film 23 is formed on the first conductor layer 22 formed on substantially the entire surface of the substrate 10, it is formed on a flat surface having substantially no step. When the dielectric thin film 23 is formed by the MOD method, the coverage of the step portion is not necessarily good, and a short circuit or a leak current is likely to occur at the step portion. Therefore, it is preferable in the process that the dielectric thin film 23 is formed on a flat surface.

次に第２の導体層２４上にレジストを塗布し、露光・現像を行ってレジストを所定のパターンに形成し、ドライエッチングによって第２の導体層２４の一部を除去した（図２（ｂ））。   Next, a resist is applied on the second conductor layer 24, exposed and developed to form a resist in a predetermined pattern, and a part of the second conductor layer 24 is removed by dry etching (FIG. 2B). )).

次に前記のＭＯＤ原料溶液を塗布、乾燥させて酸素中６２５℃で３０分間の熱処理を行って、図２（ｃ）に示すように、膜厚２００ｎｍのＢＳＴからなる第１のバリア層３１を形成した。その後、８２５℃で３０分間の熱処理を行って誘電体薄膜２３の結晶性を向上させた。   Next, the MOD raw material solution is applied and dried, and heat treatment is performed in oxygen at 625 ° C. for 30 minutes. As shown in FIG. 2C, the first barrier layer 31 made of BST having a thickness of 200 nm is formed. Formed. Thereafter, heat treatment was performed at 825 ° C. for 30 minutes to improve the crystallinity of the dielectric thin film 23.

次に第１のバリア層３１上にレジストを塗布し、露光・現像を行ってレジストを所定のパターンに形成し、ウェットエッチングを行って第１のバリア層３１と誘電体薄膜２３とを、図２（ｄ）に示すように所定形状にパターニングした。このとき、第２の導体層２４上の第１のバリア層３１に孔６３が形成されて第２の導体層２４の一部が露出するようにされている。   Next, a resist is applied onto the first barrier layer 31, exposure and development are performed to form the resist in a predetermined pattern, and wet etching is performed to form the first barrier layer 31 and the dielectric thin film 23. Patterned into a predetermined shape as shown in 2 (d). At this time, a hole 63 is formed in the first barrier layer 31 on the second conductor layer 24 so that a part of the second conductor layer 24 is exposed.

次に第１の導体層２２および第１のバリア層３１上にレジストを塗布し、露光・現像を行ってレジストを所定のパターンに形成し、ドライエッチングを行うことによって基板１０外周部の密着層２１および第１の導体層２２を除去するとともに、第１および第２の貫通孔６１，６２を形成して基板１０表面を露出させた。   Next, a resist is applied on the first conductor layer 22 and the first barrier layer 31, exposure / development is performed to form a resist in a predetermined pattern, and dry etching is performed, whereby an adhesion layer on the outer periphery of the substrate 10 is formed. 21 and the first conductor layer 22 were removed, and the first and second through holes 61 and 62 were formed to expose the surface of the substrate 10.

次にスパッタ法によって膜厚１μｍの窒化ケイ素を成膜し、レジストを塗布し、露光・現像を行ってレジストを所定のパターンに形成し、ドライエッチングによって窒化ケイ素膜の一部を除去して、図３（ｆ）に示すように第２のバリア層３２を形成した。第２のバリア層３２は、第１の貫通孔６１の内部においては第１の導体層２２を完全に覆うことがないように内壁の一部を覆っており、第２の貫通孔６２の内部においては第１の導体層２２を完全に覆うように内壁の略全面を覆っている。   Next, a silicon nitride film having a thickness of 1 μm is formed by sputtering, a resist is applied, exposure / development is performed to form a resist in a predetermined pattern, and a part of the silicon nitride film is removed by dry etching, A second barrier layer 32 was formed as shown in FIG. The second barrier layer 32 covers a part of the inner wall so as not to completely cover the first conductor layer 22 inside the first through hole 61, and the inside of the second through hole 62. In FIG. 3, substantially the entire inner wall is covered so as to completely cover the first conductor layer 22.

次に感光性のベンゾシクロブテン（ＢＣＢ）ワニスを塗布し、露光・現像した後にキュアを行って、図３（ｇ）に示すようにＢＣＢ樹脂からなる第１の保護層３３を形成した。   Next, photosensitive benzocyclobutene (BCB) varnish was applied, exposed and developed, and then cured to form a first protective layer 33 made of BCB resin, as shown in FIG.

次に順にＴｉ，Ｃｕ，Ｎｉを成膜することによって図３（ｈ）に示すように第１および第２の導体パッド４１，４２を形成した。Ｔｉ，Ｃｕ，Ｎｉの膜厚はそれぞれ１００ｎｍ、５００ｎｍ、２μｍとした。   Next, Ti, Cu, and Ni were formed in this order to form first and second conductor pads 41 and 42 as shown in FIG. The film thicknesses of Ti, Cu, and Ni were 100 nm, 500 nm, and 2 μm, respectively.

次に第１の保護層３３と同様の方法で図４（ｉ）に示すようにＢＣＢ樹脂からなる第２の保護層３４を形成した。第１の保護層３３を形成せずに第２の保護層３４のみを形成するようにしてもよい。   Next, a second protective layer 34 made of BCB resin was formed by the same method as that for the first protective layer 33 as shown in FIG. Only the second protective layer 34 may be formed without forming the first protective layer 33.

次に第１および第２の導体パッド４１，４２の露出部分に、はんだとの接合性を高めるために、無電解めっきによって順にＮｉ，Ａｕを形成し（Ｎｉ，Ａｕ被膜は図示しない）、Ｓｎ−Ａｇ−Ｃｕ系の無鉛はんだによって図４（ｊ）に示すようにバンプ５１，５２を形成して本発明の薄膜キャパシタが完成した。なおＮｉ，Ａｕの膜厚はともに５００ｎｍとした。   Next, Ni and Au are sequentially formed on the exposed portions of the first and second conductor pads 41 and 42 by electroless plating in order to improve the bondability with the solder (Ni and Au coatings are not shown). As shown in FIG. 4 (j), bumps 51 and 52 were formed with -Ag-Cu lead-free solder, thereby completing the thin film capacitor of the present invention. The film thicknesses of Ni and Au were both 500 nm.

ここで、比較例として上記実施例と同様の方法で図５に示す構造を有する薄膜キャパシタを作製した。比較例の薄膜キャパシタは、第１の導体層２２と第１の導体パッド４１とが第１の導体層２２の上面で接続しており、第２の導体層２４と第２の導体パッド４２とが第２の導体層２４の上面で接続している。第１および第２の導体パッド４１，４２はいずれも基板１０に接合していない。その他の構成は実施例の薄膜キャパシタと同じである。図５においては、図１ないし図４と共通あるいは対応する部分に同一の符号を付しているので、構成の説明は省略する。   Here, as a comparative example, a thin film capacitor having the structure shown in FIG. In the thin film capacitor of the comparative example, the first conductor layer 22 and the first conductor pad 41 are connected on the upper surface of the first conductor layer 22, and the second conductor layer 24 and the second conductor pad 42 are connected to each other. Are connected on the upper surface of the second conductor layer 24. None of the first and second conductor pads 41 and 42 are bonded to the substrate 10. Other configurations are the same as those of the thin film capacitor of the embodiment. In FIG. 5, the same or corresponding parts as in FIGS. 1 to 4 are denoted by the same reference numerals, and the description of the configuration is omitted.

実施例の薄膜キャパシタと比較例の薄膜キャパシタを各々１０個ずつ作製し、表面にＣｕからなる配線が形成された厚さ１．２７ｍｍのガラス−エポキシ基板（線膨張係数およそ４０ｐｐｍ／℃）上に実装した。   Ten thin film capacitors of the example and the comparative thin film capacitor were manufactured, respectively, on a glass-epoxy substrate (linear expansion coefficient of about 40 ppm / ° C.) having a thickness of 1.27 mm on which Cu wiring was formed. Implemented.

実装後、各試料について導通不良のバンプがみられるか実験したところ、実施例の薄膜キャパシタはすべての試料で導通不良はみられなかったが、比較例の薄膜キャパシタでは１０個中１個の試料で導通不良が見つかった。   After mounting, an experiment was conducted to determine whether or not bumps with poor continuity were observed for each sample. In all of the thin film capacitors of the example, no continuity failure was observed, but one sample out of 10 was found in the thin film capacitor of the comparative example. In continuity failure was found.

次にこれらの試料を−５５℃〜＋１２５℃で５００サイクルの熱サイクル試験に供した後に導通テストおよび静電容量の測定を行った。実施例に係る試料では導通不良はみられず、静電容量変化率ΔＣ／Ｃ0（熱サイクル試験前の静電容量をＣ0、熱サイクル試験前後の静電容量の変化量をΔＣとする）は±２％以内だった。これに対して比較例に係る試料では、１０個中８個の試料で導通不良が見つかった。また、導通不良がみられた８個の試料で、導通不良のないバンプを用いて静電容量を測定したところ、８個中６個でショート状態であることがわかった。なお、静電容量はＬＣＲメータを用いて０．５Ｖ、１ｋＨｚの条件で測定した。 Next, these samples were subjected to a thermal cycle test of 500 cycles at −55 ° C. to + 125 ° C., and then a continuity test and a capacitance measurement were performed. In the sample according to the example, no conduction failure was observed, and the capacitance change rate ΔC / C 0 (capacitance before the thermal cycle test was C 0 , and the change in capacitance before and after the thermal cycle test was ΔC. ) Was within ± 2%. On the other hand, in the sample according to the comparative example, conduction failure was found in 8 out of 10 samples. Moreover, when the electrostatic capacity was measured using the bumps having no continuity failure in 8 samples in which the continuity failure was observed, it was found that 6 out of 8 samples were in a short-circuit state. The capacitance was measured using an LCR meter under conditions of 0.5 V and 1 kHz.

なお、本発明は上記実施例に限定されるものではないことはいうまでもなく、本発明の趣旨の範囲内で種々の変更を加えることが可能である。   Needless to say, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the gist of the present invention.

例えば基板としてはＳｉ基板の他にサファイア基板や石英ガラス基板などを用いることができる。密着層として上記実施例ではＢＳＴを用いたが、必ずしも誘電体薄膜と同一の材料を用いる必要はなく、例えばＴｉやＣｒ、ＴｉＯ2などを用いることもできる。誘電体薄膜としてはＢＳＴの他にＢａＴｉＯ3、ＳｒＴｉＯ3、Ｐｂ（Ｚｒ，Ｔｉ）Ｏ3などの高誘電率の複合酸化物を好適に用いることができる。 For example, a sapphire substrate or a quartz glass substrate can be used as the substrate in addition to the Si substrate. In the above embodiment, BST is used as the adhesion layer, but it is not always necessary to use the same material as that of the dielectric thin film. For example, Ti, Cr, TiO 2 or the like can be used. As the dielectric thin film, a complex oxide having a high dielectric constant such as BaTiO 3 , SrTiO 3 , Pb (Zr, Ti) O 3 can be preferably used in addition to BST.

また、上記実施例では一つの基板上に一つの薄膜キャパシタを作製するかのように説明したが、一つの基板上に複数の薄膜キャパシタを作製してダイシングソーで個々の薄膜キャパシタに切り分けるようにしてもよい。   In the above embodiment, the description is made as if one thin film capacitor is formed on one substrate. However, a plurality of thin film capacitors are manufactured on one substrate and separated into individual thin film capacitors using a dicing saw. May be.

本発明の薄膜キャパシタを示す平面図および断面図である。It is the top view and sectional drawing which show the thin film capacitor of this invention. 本発明の薄膜キャパシタの製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the thin film capacitor of this invention. 本発明の薄膜キャパシタの製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the thin film capacitor of this invention. 本発明の薄膜キャパシタの製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the thin film capacitor of this invention. 比較例の薄膜キャパシタを示す断面図である。It is sectional drawing which shows the thin film capacitor of a comparative example. 従来の薄膜キャパシタを示す断面図である。It is sectional drawing which shows the conventional thin film capacitor.

符号の説明Explanation of symbols

１０ 基板
２１ 密着層
２２ 第１の導体層
２３ 誘電体薄膜
２４ 第２の導体層
３１ 第１のバリア層
３２ 第２のバリア層
３３ 第１の保護層
３４ 第２の保護層
４１ 第１の導体パッド
４２ 第２の導体パッド
５１，５２ バンプ

DESCRIPTION OF SYMBOLS 10 Board | substrate 21 Adhesion layer 22 1st conductor layer 23 Dielectric thin film 24 2nd conductor layer 31 1st barrier layer 32 2nd barrier layer 33 1st protective layer 34 2nd protective layer 41 1st conductor Pad 42 Second conductor pad 51, 52 Bump

Claims (3)

基板と、
該基板上に形成された第１の導体層と、該第１の導体層上に形成された誘電体薄膜と、該誘電体薄膜上に前記第１の導体層と電気的に絶縁されて形成された第２の導体層と、を有するキャパシタ部と、
前記第１の導体層に電気的に接続するとともに前記キャパシタ部の上面に引き出さるように形成された第１の導体パッドと、
前記第２の導体層に電気的に接続するとともに前記キャパシタ部の上面に引き出されるように形成された第２の導体パッドと、
前記第１および第２の導体パッド上それぞれに形成された第１および第２のバンプと、を備え、
前記第１および前記第２の導体パッドは前記基板に接合されていることを特徴とする薄膜キャパシタ。 A substrate,
A first conductor layer formed on the substrate; a dielectric thin film formed on the first conductor layer; and the first conductor layer electrically insulated from the first conductor layer on the dielectric thin film. A capacitor portion having a second conductor layer formed;
A first conductor pad formed so as to be electrically connected to the first conductor layer and to be drawn to the upper surface of the capacitor unit;
A second conductor pad formed so as to be electrically connected to the second conductor layer and to be drawn to the upper surface of the capacitor unit;
First and second bumps formed on the first and second conductor pads, respectively,
The thin film capacitor, wherein the first and second conductive pads are bonded to the substrate. 前記誘電体薄膜は、平坦な面上に形成されていることを特徴とする請求項１に記載の薄膜キャパシタ。   The thin film capacitor according to claim 1, wherein the dielectric thin film is formed on a flat surface. 基板上に第１の導体層を形成する工程と、
前記第１の導体層上に、金属の有機化合物を含有する誘電体原料溶液を塗布して熱処理を行い、誘電体薄膜を形成する工程と、
前記誘電体薄膜上に第２の導体層を形成する工程と、
前記第１および第２の導体層と前記誘電体薄膜を貫通し、前記基板を底面とする複数の貫通孔を形成する工程と、
前記貫通孔のうちいずれかの内部に、前記第１の導体層と電気的に接続し前記第２の導体層と電気的に絶縁され、前記基板に接合された第１の導体パッドを形成する工程と、
前記貫通孔のうちいずれかの内部に、前記第２の導体層と電気的に接続し前記第１の導体層と電気的に絶縁され、前記基板に接合された第２の導体パッドを形成する工程と、
前記第１および第２の導体パッド上に、それぞれ第１および第２のバンプを形成する工程と、を有することを特徴とする薄膜キャパシタの製造方法。

Forming a first conductor layer on a substrate;
Applying a dielectric material solution containing a metal organic compound on the first conductor layer and performing a heat treatment to form a dielectric thin film;
Forming a second conductor layer on the dielectric thin film;
Forming a plurality of through holes penetrating the first and second conductor layers and the dielectric thin film and having the substrate as a bottom surface;
A first conductor pad electrically connected to the first conductor layer, electrically insulated from the second conductor layer, and joined to the substrate is formed inside any of the through holes. Process,
A second conductor pad that is electrically connected to the second conductor layer, electrically insulated from the first conductor layer, and joined to the substrate is formed inside any of the through holes. Process,
Forming a first bump and a second bump on the first and second conductor pads, respectively.

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