JP2008270250A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a copper wiring in which the resistance rate of a wiring does not remarkably increases even if a trench forming the wiring has a width of not more than 70 nm and a value disclosed in the international semiconductor road map is met. <P>SOLUTION: The copper wiring has a width of not more than 70 nm and a ratio D/W of an average crystal particle diameter D to a wiring width W is ≥1.3 in a surface parallel to the side surface of a trench. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a wiring width of 70 nm and less than that shown in a wiring road map, and a manufacturing method thereof.

  Semiconductor integrated circuit devices are being highly integrated at a high speed, in which integration is quadrupled in three years, which is said by Moore's Law. An example of the wiring of the MPU (Micro Processing Unit) of 2005 (ITRS 2005 Edition) is the International Semiconductor Technology Roadmap for Semiconductor, which is a standard for improving the degree of integration. In order to improve the degree of integration, the target value of the wiring width is 90 nm in 2005, 68 nm in 2007, 45 nm in 2010, and 32 nm in 2013. The target value of resistivity is as follows to ensure high-speed operation. They are 3.07 μΩ · cm, 3.43 μΩ · cm, 4.08 μΩ · cm, and 4.83 μΩ · cm, respectively.

As a wiring material of a semiconductor integrated circuit device, aluminum or an aluminum alloy that has been inexpensive and has a relatively low resistivity has been widely used so far. However, as the degree of integration increases (the wiring width becomes narrower), the resistivity of aluminum is reduced. Copper or a copper alloy, which is about half and whose allowable current is two orders of magnitude greater than aluminum, tends to be used instead of aluminum. However, it is known that when the wiring width is reduced to a certain value or less, the resistivity of the copper wiring becomes larger than that of aluminum based on the difference in mean free path between copper and aluminum (Patent Document 1). In patent document 1, it is based on the difference of an average free path | route by providing both aluminum wiring and copper wiring, and selectively using the direction where a resistivity becomes small among aluminum wiring and copper wiring according to the shape of wiring. The problem is solved.
JP 2003-133212 A

  The present inventors have confirmed through experiments that the resistivity disclosed in the international semiconductor technology roadmap cannot be achieved by the method proposed in Patent Document 1 when the wiring width is 70 nm or less. The inventors of the present invention are that the width of the trench for forming the wiring becomes narrower when the integration degree of the semiconductor integrated circuit device is improved, and the crystal grain size of the copper wiring formed in the trench when the width of the trench is 100 nm or less. It has been estimated that there is a large number of crystal grains in the direction of current flow, the chance of electrons being scattered at the crystal grain interface increases, and the resistivity increases abnormally.

  An object of the present invention is to provide a copper wiring that satisfies the target value disclosed in the international semiconductor technology roadmap with a margin without increasing the resistivity of the wiring even when the width of the trench forming the wiring is 70 nm or less. An object of the present invention is to provide a semiconductor integrated circuit device using the same and a manufacturing method thereof.

  The semiconductor integrated circuit device of the present invention that achieves the above object is characterized by utilizing a semiconductor substrate on which circuit elements are formed, an insulating layer formed on the main surface of the semiconductor substrate, and at least the insulating layer. And a copper wiring having a wiring width of 70 nm or less formed in the trench, and the copper wiring has a grain boundary structure with less electron scattering. The grain boundary structure with less electron scattering will be clear from the following explanation.

  The semiconductor integrated circuit device of the present invention that achieves the above object is characterized in that a semiconductor substrate on which circuit elements are formed, an insulating layer formed on the main surface of the semiconductor substrate, and at least using the insulating layer And a copper wiring formed in the trench, the wiring width of the copper wiring is 70 nm or less, and the average crystal grain size in the plane parallel to the side surface of the trench of the copper wiring is 1.3 times or more of the wiring width It is in the point made to become. The resistivity of the copper wiring increases rapidly when the ratio D / W of the average crystal grain size D and the wiring width W in the plane parallel to the side surface of the trench is 1.3 or less, but is stable when the ratio is higher than that. It is confirmed that the low value is maintained, and by setting the ratio D / W to 1.3 or more, it becomes possible to realize a wiring satisfying the resistivity disclosed in the international semiconductor technology roadmap. The copper wiring here means wiring made of high-purity copper that does not contain impurities other than impurities inevitably mixed in the manufacturing process. Examples of the semiconductor substrate include a substrate made of a semiconductor single crystal or semiconductor polycrystal composed of a group IV element, a group III-V compound, and a combination thereof, an insulating substrate, and a semiconductor single crystal layer or a semiconductor polycrystal layer formed thereon. A substrate. The term “copper wiring” as used herein includes not only those in which all the wiring layers of the semiconductor integrated circuit device are formed of copper wiring, but also those in which copper wiring is used in part.

  Another feature of the semiconductor integrated circuit device of the present invention that achieves the above object with good reproducibility is that the standard deviation of the crystal grain size of the copper wiring is set in the semiconductor integrated circuit device having the above ratio D / W of 1.3 or more. 40 nm or less.

  Another feature of the semiconductor integrated circuit device of the present invention that achieves the above object is that the oxygen concentration in the copper wiring is 5 wt% or less at a wiring width of 70 nm or less, 4 wt% or less at 50 nm or less, and 3 wt% at 30 nm or less. It is in the following. By reducing the oxygen concentration in the wiring to a predetermined value or less according to the wiring width, the resistivity of the copper wiring is the resistivity of the wiring widths 68 nm, 45 nm, and 32 nm disclosed in the International Semiconductor Technology Roadmap 2005 edition. It is possible to realize a resistivity significantly lower than the target value of 3.43 μΩ · cm, 4.08 μΩ · cm, and 4.83 μΩ · cm. Further, the change in the resistivity of the wiring with respect to the change in the oxygen concentration in the wiring is remarkably reduced, and a desired resistivity can be realized with good reproducibility.

  The manufacturing method of the semiconductor integrated circuit device of the present invention that achieves the above object is characterized by a copper sulfate plating bath having a purity of 99.99 to 99.99999999 wt% (hereinafter referred to as 4N to 8N), and a purity of 99.9999 for the anode. A copper plating layer is formed in the trench by electrolytic plating using a copper electrode of ˜99.9999999 wt% (hereinafter referred to as 6N to 9N), and then the copper plating layer is heat-treated in a hydrogen atmosphere. By this manufacturing method, it is possible to easily realize the ratio D / W of 1.3 or more and the oxygen concentration of 5 wt% or less.

  Another feature of the method of manufacturing a semiconductor integrated circuit device according to the present invention that achieves the above object is that a copper plating layer is formed in the trench by electrolytic plating using a copper sulfate plating bath, a copper electrode at the anode, and accordingly. Later, the copper plating layer is heated by infrared rays in an atmosphere selected from hydrogen, argon, and nitrogen. This manufacturing method can easily realize the ratio D / W of 1.3 or more and the oxygen concentration of 5 wt% or less.

  According to the present invention, the resistivity increases abnormally as the trench width becomes narrower by defining the ratio D / W of the average crystal grain size D and the wiring width W or by defining the oxygen concentration in the wiring. This makes it possible to realize a semiconductor integrated circuit device having wiring that satisfies the values disclosed in the international semiconductor technology roadmap.

As a semiconductor integrated circuit device to which the present invention is applied, MPUs and ASICs (Applications) in which a single crystal semiconductor substrate is integrated with a large number of circuit elements selected from MOS transistors, bipolar transistors, etc., and the degree of integration is being promoted every day. A logic LSI such as a specific integrated circuit (generic name of an integrated circuit for a specific application), a memory LSI such as a DRAM (Dynamic Random Access Memory), and a flash memory are preferable applications. As another application, there is a liquid crystal display device that requires a high-speed operation due to an increase in size of a display screen.
Hereinafter, preferred embodiments of a semiconductor integrated circuit device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view of a semiconductor integrated circuit device to which the present invention is applied. An actual semiconductor integrated circuit device has eight, nine, or more wiring layers. However, in order to simplify the description, FIG. A layer wiring structure is illustrated. In the figure, 1 is a semiconductor substrate on which a large number of circuit elements (not shown) are formed adjacent to one main surface 1a, and 2 is, for example, a silicon oxide formed on one main surface 1a of the semiconductor substrate 1. A first insulating layer made of a material layer, 2a is a through hole formed in the first insulating layer 2, 3 is a plug made of, for example, tungsten formed in the through hole 2a, and 3a is between the through hole 2a and the plug 3. A barrier layer made of, for example, TiN (titanium nitride) is formed on the first insulating layer 2 and the plug 3, and a second insulating layer made of, for example, a silicon oxide layer 42 is formed through, for example, a silicon nitride layer 41. 4a is a first trench formed in the second insulating layer 4, 5 is a first copper wiring formed in the first trench 4a, and 5a is formed between the first trench 4a and the first copper wiring 5. For example, TaN A barrier layer 6 made of tantalum nitride) / Ta (tantalum), for example, a silicon oxide layer 62, a silicon nitride layer 63, and a silicon oxide layer on the second insulating layer 4 and the first copper wiring 5 through a silicon nitride layer 61, for example. A third insulating layer formed by sequentially stacking the physical layers 64; 6a, a second trench having a T-shaped cross section formed in the second insulating layer 6; and 7, a second copper wiring formed in the second trench 6a. , 7a are barrier layers made of, for example, Ta / TaN / Ta formed between the second trench 6a and the second copper wiring 7. The wiring width of the first copper wiring 5 and / or the second copper wiring 7 is a value of 70 nm or less including the width of the barrier layer 5a or 7a, and the average crystal grain size D and the wiring width in a plane parallel to the side surface of the trench The ratio D / W of W is 1.3 or more. The wiring width is a width determined by the width of the trench, and is a value obtained by adding the width of the barrier layer 5 a or 7 a to the line width of the first copper wiring 5 or the second copper wiring 7.

  FIG. 2 is a diagram showing the relationship between the average crystal grain size D and the ratio D / W of the wiring width W and the resistivity in the plane parallel to the side surface of the trench in the copper wiring. From this figure, the ratio D / W is 1.3. It can be seen that when the boundary is 1.3 or less, the resistivity increases rapidly, and when it is 1.3 or more, the resistivity is stable between 2.8 and 3.0 μΩ · cm. This resistivity is significantly higher than the target value of 3.43 μΩ · cm, 4.08 μΩ · cm, and 4.83 μΩ · cm when the wiring width is 68 nm, 45 nm, and 32 nm, which is disclosed in the 2005 edition of the International Semiconductor Technology Roadmap. It is possible to realize a value lower than. The present invention is characterized in that the copper wiring is used in the range of the ratio D / W of the average crystal grain diameter D and the wiring width W where the resistivity is stable. The data in FIG. 2 was the same regardless of whether the wiring width was 70 nm, 50 nm, or 30 nm.

  The average crystal grain size in a plane parallel to the side surface of the trench of the copper wiring was measured using a FIB / TEM technique widely known as a fine structure analysis technique. As shown in FIG. 3, the FIB / TEM technique is a sample piece formed by focusing ion beam (FIB) processing on a region extending from a copper wiring 5 (7) as a sample to a surface parallel to the side surface of the trench 4a (6a). And a surface parallel to the side surface of the trench 4a (6a) of the sample piece is observed with a transmission electron microscope (TEM). In the organization chart shown in FIG. 4 observed by TEM, a line is drawn along the grain boundary of each crystal grain, the area of the grain size is obtained assuming that the crystal grain is circular, and finally the individual grain size is calculated. The average value of them was obtained. This is the average crystal grain size.

  The present invention has found that the ratio D / W of the average crystal grain diameter D and the wiring width W in a plane parallel to the side surface of the trench of the copper wiring has a preferable range for reducing the resistivity of the wiring. It is a thing. The ratio D / W between the average crystal grain size D of the wiring and the width W of the wiring has been studied in order to improve the electromigration resistance. In this case, the average crystal grain size of the wiring formed in the trench is from the surface side. The calculated value is used. The present inventors have found that in copper wiring having a wiring width of 100 nm or less, crystal grains are distributed so that the crystal grain size decreases from the surface side toward the bottom side. Therefore, the average crystal grain size seen from the surface side of the wiring does not change greatly depending on the wiring width, but the average crystal grain size in the plane parallel to the side surface of the trench of the wiring changes greatly. Since the resistivity of the wiring depends on the number of crystal grain boundaries in the direction of current flow, the average crystal grain size in the plane parallel to the side surface of the trench is important for reducing the wiring resistivity. It becomes a factor. The present invention has been made based on this new finding.

  The reason why the resistivity can be reduced when the ratio D / W of the average crystal grain size D to the wiring width W in the plane parallel to the side surface of the trench of the copper wiring is 1.3 or more is that the average crystal grain size increases. It means that the crystal grain becomes larger, and as a result, the main factor is that the grain boundary existing in the direction of current flow decreases and the electron scattering decreases.

FIG. 5 is a diagram showing the relationship between the standard deviation of the crystal grain size and the resistivity in the copper wiring, and it can be seen that the resistivity rapidly increases when the standard deviation of the crystal grain size is around 35 to 40 nm. Therefore, when the standard deviation is 40 nm or less, preferably 35 nm or less, the change in resistivity is almost eliminated, and a copper wiring having a desired resistivity can be obtained with good reproducibility.

  Reducing the standard deviation of the crystal grain size while maintaining the ratio D / W of the average crystal grain size D and the wiring width W to 1.3 or more means that crystal grains having a crystal grain size larger than the line width are aligned. This means that the grain boundaries existing in the direction of current flow are reduced and the resistivity is reduced. Therefore, it is preferable that the standard deviation is small. However, 0 nm is not included in the standard deviation. The data in FIG. 5 was the same regardless of whether the wiring width was 70 nm, 50 nm, or 30 nm.

  As a method of measuring the standard deviation of the crystal grain size from the copper wiring, for example, the organization chart shown in FIG. 4 is created using the FIB / TEM technique, and the grain size of all crystal grains is calculated from the formula (1). It is possible to calculate by

  FIG. 6 is a diagram showing the relationship between the oxygen concentration contained in the copper wiring and the resistivity. When the wiring width is 70 nm, the resistivity rapidly increases when the oxygen concentration exceeds 5 wt%, and when the wiring width is 50 nm, the oxygen concentration is 4 wt%. It can be seen that the resistivity rapidly increases when the oxygen concentration exceeds 30 nm, and the resistivity increases rapidly when the oxygen concentration exceeds 3 wt% in the case of 30 nm. Therefore, if the oxygen concentration in the copper wiring is 5 wt% or less when the wiring width is 70 nm, a copper wiring having a resistivity of 3 μΩ · cm or less can be obtained with good reproducibility, and if the wiring width is 50 nm, the oxygen concentration is 4 wt%. Copper wiring with a resistivity of 3.5 μΩ · cm or less can be obtained with good reproducibility when it is less than%, and when the wiring width is 30 nm, copper wiring with a resistivity of 3.8 μΩ · cm or less is obtained with an oxygen concentration of 3 wt% or less. Is obtained with good reproducibility and is disclosed in the International Semiconductor Technology Roadmap 2005 edition as a target value of resistivity 3.43 μΩ · cm, 4.08 μΩ · cm, 4.83 μΩ · when the wiring width is 68 nm, 45 nm, and 32 nm. It can be seen that a resistivity significantly lower than cm can be realized. The lower the oxygen concentration, the lower the resistivity, so there is no preferred lower limit for the oxygen concentration.

  The oxygen concentration in the copper wiring was measured by TEM / EDS (energy dispersive X-ray analyzer compatible with a transmission electron microscope). Specifically, by irradiating the copper wiring with an electron beam having a beam diameter of 1 to 2 nm and detecting the energy of the X-rays excited from the copper wiring, the type of element contained in the copper wiring (qualitative analysis) and its This is a method for analyzing the concentration (quantitative analysis).

  The reason why the resistivity decreases when the concentration of oxygen contained in the copper wiring is reduced is as follows. (1) Since oxygen collects near the grain boundary and causes electron scattering, lowering the oxygen concentration can reduce the oxygen collected near the grain boundary. It can be considered that the electron scattering can be suppressed, and (2) the adhesion between the copper wiring and the barrier layer is improved when the oxygen concentration is lowered, and the electron scattering on the side surface and the bottom surface of the copper wiring can be suppressed. Infer.

  When referring to the copper wiring of the semiconductor integrated circuit device of the present invention from the grain boundary structure, it is considered that the grain boundary of adjacent crystal grains is a coincidence boundary. As described in the paper “5. Special High Angle Grain Boundaries” published in Grain Boundary Structure and Properties Academic Press (1976), the corresponding grain boundary is defined as two grain boundaries adjacent to each other in the grain boundary. The state where there is an atom to do. When atoms are shared between adjacent crystal grains, there is no grain boundary in that portion, and electron scattering does not occur, so that the effect of decreasing the resistivity is obtained.

  FIG. 7 is a schematic process diagram for explaining a method for manufacturing a semiconductor integrated circuit device of the present invention. The same members in FIG. In addition, a step of forming a copper wiring using a dual damascene process directly related to the present invention in the method of manufacturing a semiconductor integrated circuit device is shown.

  First, a semiconductor substrate 1 having a large number of circuit elements (not shown) formed adjacent to one main surface 11 is prepared, and a silicon nitride layer 41 and a silicon oxide layer are formed above one main surface 1a of the semiconductor substrate 1. The first insulating layer 4 made of the material layer 42 is deposited by a CVD (Chemical Vapor Deposition) method. Next, the silicon oxide layer 42 in a region where wiring is to be formed is removed by etching, and the exposed silicon nitride layer 41 is further etched to form the first trench 4a. This trench has a depth selected by a current carrying capacity from a range of 70 nm or less in width and 50 to 300 nm. The silicon nitride layer 41 is used as a stopper when the silicon oxide layer 42 is etched (FIG. 7a).

  Next, a barrier layer 5a made of, for example, a TaN / Ta laminated body is deposited on the silicon oxide layer 42 including the inside of the first trench 4a to a thickness of about several nm to 10 nm by sputtering or CVD. Copper wiring 5 is formed on this barrier layer 5a. In this method, first, an ultrathin copper seed layer (not shown) is formed on the barrier layer 5a by sputtering, a copper sulfate plating bath having a purity of 6N is formed on the copper seed layer, and a copper electrode having a purity of 9N is used for the anode. A copper plating layer having a thickness exceeding the depth of the first trench 4a was formed by electrolytic plating, and then formed by a process of heat treatment at 200 to 400 ° C. for 10 minutes to 1 hour in a hydrogen atmosphere (FIG. 7b). The high-purity plating bath and copper electrode used in this electrolytic plating process are not currently available on the market, so they were specially ordered from material manufacturers.

  As another method for forming the copper wiring 5, an electrolytic plating method is performed by using a commercially available copper sulfate plating bath having a normal purity of 3N on the copper seed layer and a copper electrode having a purity of 4N commercially available on the anode. A copper plating layer having a thickness exceeding the depth of the first trench 4a is formed by heat treatment at 200 to 600 ° C. for 10 minutes to 1 hour with an infrared lamp in an atmosphere selected from hydrogen, argon and nitrogen. is there. The feature of this method is that a low-purity plating bath and a copper electrode can be used, and processing can be performed in a short time.

  Next, the portion of the first trench 4a that exceeds the depth of the first trench 4a, and the copper layer and the barrier layer 5a on the silicon oxide layer 42 are removed by CMP (Chemical Mechanical Polishing), and the first trench 4a is removed. Only the copper layer to be the first copper wiring 5 and the barrier layer 5a are left (FIG. 7c).

  Next, a silicon nitride layer 61, a silicon oxide layer 62, a silicon nitride layer 63, and a silicon oxide layer 64 are sequentially deposited on the silicon oxide layer 42 and the first copper wiring 5 by a CVD method. Here, the silicon nitride layer 63 serves as an etching stopper when forming the upper side portion of the second trench 6 a having a T-shaped cross section, and the silicon nitride layer 61 serves as a contact hole for connection to the first copper wiring 5. It functions as an etching stopper when forming the (T-shaped leg) (FIG. 7d). The width of the upper side portion of the trench has a depth selected by the current carrying capacity from a range of 70 nm or less and 50 to 300 nm.

  Next, the silicon oxide layer 64, the silicon nitride layer 63, and the silicon oxide layer 62 on the contact region of the first copper wiring 5 are removed by etching, and the silicon nitride layer 61 exposed by the etching is further etched to thereby contact holes. (T-shaped leg portion of the second trench 6a) is formed.

  Next, an antireflection film or a resist film (not shown) is formed on the silicon oxide layer 64 including the inside of the contact hole. Further, the antireflection film or the resist film and the silicon oxide layer 64 are etched using the resist film having an opening in a region where the second copper wiring 7 is to be formed as a mask. Subsequently, the silicon nitride layer 63 exposed by this etching is etched and the antireflection film or the resist film in the contact hole is removed to form the second trench 6a (FIG. 7e).

  Next, a barrier layer 7a made of, for example, a Ta / TaN / Ta laminate is deposited on the silicon oxide layer 64 including the inside of the second trench 6a to a thickness of about several nm to 10 nm by sputtering or CVD.

  Next, a thin copper film is formed on the barrier layer 7a by sputtering, and this copper film is used as a seed layer on the entire surface of the barrier layer 7a including the second trench 6a by the same method as that for the first copper wiring. A copper layer having a thickness exceeding the depth of the two trenches 6a is formed, and the same heat treatment is performed (FIG. 7f).

  Thereafter, the portion of the second trench 6a that exceeds the depth of the second trench 6a and the copper layer and the barrier layer 7a on the silicon oxide layer 64 are removed by CMP, so that the second trench 6a is only in the second trench 6a. A copper layer having a two-layer structure is completed, leaving the copper layer and the barrier layer 7a to be the copper wiring 7. (Figure 7g).

  In this embodiment, the method for manufacturing a copper wiring having a two-layer structure has been described. However, when a wiring structure having three or more layers is used, it can be realized by repeating the process of forming the second copper wiring.

  The copper wiring of the semiconductor integrated circuit device obtained in this example has a wiring width of 70 nm, a ratio D / W of the average crystal grain size D to the wiring width W of 1.4, a resistivity of 2.9 μΩ · cm, and an oxygen concentration of 1 wt. %Met.

  In the embodiment of the present invention, a combination of a Ta film and a TaN film is used as the barrier layers 5a and 7a. However, the present invention is not limited to this, and a combination of another metal and a nitride of the metal can be used. Examples of the metal include Ti (titanium), W (tungsten), Nb (niobium), Cr (chromium), and Mo (molybdenum).

It is a schematic sectional drawing of the semiconductor integrated circuit device shown as one Example of this invention. It is a figure which shows the relationship between the ratio D / W of the average crystal grain diameter D in the surface parallel to the side surface of the trench in copper wiring, and wiring width W, and resistivity. It is explanatory drawing of the measuring method of the average crystal grain diameter in a surface parallel to the side surface of the trench of copper wiring using FIB / TEM technique. It is the organization chart which observed the field parallel to the side of the trench of copper wiring with TEM. It is a figure which shows the relationship between the standard deviation of the crystal grain diameter in copper wiring, and resistivity. It is a figure which shows the relationship between the oxygen concentration contained in a copper wiring, and a resistivity. It is a schematic process drawing for demonstrating one process of one Example of the manufacturing method of the semiconductor integrated circuit device of this invention. It is a schematic process drawing for demonstrating one process of one Example of the manufacturing method of the semiconductor integrated circuit device of this invention. It is a schematic process drawing for demonstrating one process of one Example of the manufacturing method of the semiconductor integrated circuit device of this invention. It is a schematic process drawing for demonstrating one process of one Example of the manufacturing method of the semiconductor integrated circuit device of this invention. It is a schematic process drawing for demonstrating one process of one Example of the manufacturing method of the semiconductor integrated circuit device of this invention. It is a schematic process drawing for demonstrating one process of one Example of the manufacturing method of the semiconductor integrated circuit device of this invention. It is a schematic process drawing for demonstrating one process of one Example of the manufacturing method of the semiconductor integrated circuit device of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... 1st insulating layer, 3 ... Plug, 4 ... 2nd insulating layer, 4a ... 1st trench, 41 ... Silicon nitride layer, 42 ... Silicon oxide layer, 5 ... 1st copper wiring, 5a ... Barrier layer, 6 ... third insulating layer, 6a ... trench layer, 61 ... silicon nitride layer, 62 ... silicon oxide layer, 63 ... silicon nitride layer, 64 ... silicon oxide layer, 7 ... second copper wiring, 7a ... barrier layer.

Claims (8)

  A semiconductor substrate on which circuit elements are formed, an insulating layer formed on the main surface of the semiconductor substrate, a trench formed using at least the insulating layer, and a copper wiring formed in the trench A semiconductor integrated circuit device, wherein a line width of the copper wiring is 70 nm or less, and an average crystal grain size in a plane parallel to the side surface of the trench of the copper wiring is 1.3 times or more of the wiring width.   2. The semiconductor integrated circuit device according to claim 1, wherein a standard deviation of an average crystal grain size in a plane parallel to the side surface of the trench of the copper wiring is 40 nm or less.   A semiconductor substrate on which circuit elements are formed, an insulating layer formed on the main surface of the semiconductor substrate, a trench formed using at least the insulating layer, and a copper wiring formed in the trench A semiconductor integrated circuit device, wherein the copper wiring has a line width of 70 nm or less and an oxygen concentration of 5 wt% or less.   4. The semiconductor integrated circuit device according to claim 3, wherein the copper wiring has a line width of 50 nm or less and an oxygen concentration of 4 wt% or less.   4. The semiconductor integrated circuit device according to claim 3, wherein the copper wiring has a line width of 30 nm or less and an oxygen concentration of 3 wt% or less.   A semiconductor substrate on which circuit elements are formed, an insulating layer formed on the main surface of the semiconductor substrate, a trench formed using at least the insulating layer, and a wiring width formed in the trench is 70 nm. A semiconductor integrated circuit device comprising the following copper wiring, wherein the copper wiring has a grain boundary structure with less electron scattering.   A semiconductor substrate on which circuit elements are formed, an insulating layer formed on the main surface of the semiconductor substrate, a trench formed using at least the insulating layer, and a copper wiring formed in the trench A method of manufacturing a semiconductor integrated circuit device comprising: a copper sulfate plating bath having a purity of 99.99 to 99.99999999 wt%; and electroplating using a copper electrode having a purity of 99.9999 to 99.99999 wt% at the anode. A method for manufacturing a semiconductor integrated circuit device, comprising: a first step of forming a copper plating layer in a trench; and a second step of heat-treating the copper plating layer in a hydrogen atmosphere after electrolytic plating.   A semiconductor substrate on which circuit elements are formed, an insulating layer formed on the main surface of the semiconductor substrate, a trench formed using at least the insulating layer, and a copper wiring formed in the trench A semiconductor integrated circuit device manufacturing method comprising: a copper sulfate plating bath; a first step of forming a copper plating layer in the trench by electrolytic plating using a copper electrode as an anode; from argon, hydrogen, nitrogen after electrolytic plating; A method for manufacturing a semiconductor integrated circuit device, comprising a second step of performing infrared heating in a selected atmosphere.

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