JP2008245134A - Cdr circuit - Google Patents

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JP2008245134A
JP2008245134A JP2007085776A JP2007085776A JP2008245134A JP 2008245134 A JP2008245134 A JP 2008245134A JP 2007085776 A JP2007085776 A JP 2007085776A JP 2007085776 A JP2007085776 A JP 2007085776A JP 2008245134 A JP2008245134 A JP 2008245134A
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signal
output
phase
early
value
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Yasushi Shizuki
康 志津木
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Toshiba Corp
株式会社東芝
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Abstract

The cutoff frequency is adaptively controlled.
A CDR circuit includes a phase detector, a serial-parallel converter, a digital filter, a phase controller, a phase interpolator, an integrator, a multiplexer, and a multiplexer. The integrator 6 receives an output signal SF that is an information signal of the sign of the Early signal [0: n] -Rate signal [0: n] calculated by the digital filter 3, and inputs this signal. Monitor at a fixed period M, and integrate as frequency jitter using a delay element and an adder. The CDR circuit 40 adaptively controls the cutoff frequency by changing the threshold value of the digital filter and the phase step of the phase interpolator to optimum values.
[Selection] Figure 1

Description

  The present invention relates to a CDR circuit.

  A receiver that receives high-speed data, for example, transmission data of GHz class or higher, inputs the transmission data, generates a recovery clock signal having a frequency equal to the data rate of the transmission data, and performs CDR (Clock Data Recovery) circuit is provided. In the CDR circuit, the phase detector compares the edge of the data signal with the phase of the recovered clock signal, outputs an early signal when the phase detector is advanced from the ideal position, and outputs a rate when the phase detector is delayed from the ideal position. (Late) signal is output. The information on the number of pulses of the Early signal and the Rate signal is fed back to optimize the phase of the recovered clock signal (see, for example, Patent Document 1).

In the CDR circuit described in Patent Document 1 and the like, the threshold value of the digital filter and the phase step of the phase interpolator are fixed to a constant value. However, there is a problem that it is very difficult to find a parameter (the threshold value of the digital filter and the phase step of the phase interpolator) that satisfies both the tolerance against low frequency jitter and the tolerance against high frequency jitter. In addition, the bit width of received data is reduced due to the influence of inter-symbol interference (ISI Inter-Symbol Interference), which is caused by reflection on the transmission line and attenuation of high-frequency components, and data destruction caused by signals before interfering with current data. Since the output result of Early / Late from the phase detector may not be correct due to being smaller than 1U.I. (Unit Interval), the integrator installed in the digital filter etc. There is a problem that it is difficult to determine the threshold value. In addition, when the optimum compatible parameters (digital filter threshold and phase interpolator phase step) cannot be used, the dip amount of jitter tolerance at high frequencies increases due to the influence of the latency of the digital filter. To do.
Japanese Patent Laying-Open No. 2003-257872 (page 10, FIG. 3)

  The present invention provides a CDR circuit that can adaptively control the cutoff frequency.

  In the CDR circuit of one embodiment of the present invention, an input data signal and a recovered clock signal are input, a transition edge of the input data signal is detected, and a binary positional relationship between the data of the recovered clock signal and an early / rate is determined. , A phase detector that generates a restored data signal, a first early signal, and a first rate signal, and the first early signal and the first rate signal are input and the first detector is input at a predetermined time interval. The difference between the number of pulses of the early rate signal and the first rate signal is compared, and if the total value of the differences becomes a certain value or more, the second early signal or the second rate signal is output, and for a predetermined time A digital filter for outputting a sign signal having a value obtained by subtracting the number of pulses of the first rate signal from the first early signal at intervals, and the first filter output from the digital filter. And a second phase signal that is input to the early rate signal and the second rate signal, and a phase controller that generates a phase step signal to determine a phase step, and the code signal is input and the code signal is monitored for a certain period and integrated as frequency jitter. And an integrator that outputs as an output signal and two or more threshold values having different values of the digital filter are input, the threshold value of the digital filter is selected based on the output signal of the integrator, and the selected First selection means for outputting a digital filter threshold value to the digital filter, two or more values having different phase steps are input, and the value of the phase step is selected based on the output signal of the integrator, Second selection means for outputting the value of the selected phase step to the phase control circuit, and outputting from the phase controller Wherein based on the phase step signal, the recovered clock signal is generated and wherein the input to the phase detector.

  Furthermore, the CDR circuit according to another aspect of the present invention receives an input data signal and a recovered clock signal, detects a transition edge of the input data signal, and determines the positional relationship of the recovered clock signal with respect to the data of the early / rate binary. And a phase detector for generating a restored data signal, a first early signal, and a first rate signal, and the first early signal and the first rate signal are input at predetermined time intervals. The pulse number difference between the first early signal and the first rate signal is compared, and if the total difference value becomes a certain value or more, the second early signal or the second rate signal is output, and a predetermined value is output. A digital filter that outputs a sign signal having a value obtained by subtracting the number of pulses of the first rate signal from the first early signal at a time interval of, and output from the digital filter The second early signal and the second rate signal are input, a phase controller that generates a phase step signal for determining a phase step, the code signal is input, and the code signal is monitored for a first fixed period. Then, it is integrated as frequency jitter to generate a first signal, the code signal is monitored for a second fixed period that is different from the first fixed period, and integrated as frequency jitter to be integrated into the second signal. And an integrator that takes the AND of the first and second signals and outputs it as an output signal, and two or more threshold values having different values of the digital filter are input, and based on the output signal of the integrator A first selection means for selecting the threshold value of the digital filter and outputting the selected threshold value of the digital filter to the digital filter; And a second selection means for selecting the value of the phase step based on the output signal of the integrator and outputting the selected value of the phase step to the phase control circuit. The restored clock signal is generated and input to the phase detector based on the phase step signal output from the phase controller.

  ADVANTAGE OF THE INVENTION According to this invention, the CDR circuit which can control a cutoff frequency adaptively can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, a CDR circuit according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a CDR circuit, and FIG. 2 is a block diagram showing an integrator. In this embodiment, an integrator for integrating frequency jitter is provided in the CDR circuit.

  As shown in FIG. 1, the CDR circuit 40 includes a phase detector 1, a serial-parallel converter 2, a digital filter 3, a phase controller 4, a phase interpolator 5, an integrator 6, a multiplexer 7, and a multiplexer 8. Provided. The CDR circuit 40 adaptively controls the cutoff frequency.

  A phase detector 1 receives an input data signal and a recovered clock signal output from the phase interpolator 5, detects a transition edge of the input data, and determines the positional relationship of the clock signal with respect to the data. ) / Rate (Late) is determined, and a restored data signal, an early signal, and a rate signal are output. Here, the phase detector is also called a phase comparator, the early signal is also called an up signal, and the rate signal is also called a down signal.

  Here, as the phase detector 1, for example, a non-linear type phase detector including a register, a latch circuit, an Ex-OR circuit, and an adder is used. This phase detector receives an input data signal, a recovered clock signal, and a clock signal that is 180 ° out of phase with the recovered clock signal, and uses these two clock signals to determine the positional relationship of the clock signal with respect to data. ) / Rate (Late).

  The serial-parallel converter (Deserializer) 2 is provided between the phase detector 1 and the digital filter 3 and outputs a restored data signal, an early signal, and a rate signal output from the phase detector 1. The restored data signal, early signal, and rate signal are serial-parallel converted and output.

  The digital filter 3 is provided between the serial-parallel converter 2, the phase controller 4 and the integrator 6. The digital filter 3 is a parallel-converted early signal, a parallel-converted rate signal, And a threshold signal ST of the digital filter is input. The digital filter 3 is provided with a frequency offset integrator, a phase integrator, and the like, and a gain element, a cutoff frequency, and the like are controlled.

  The digital filter 3 inputs the parallelized Early signal and the rate signal, averages the parallelized Early signal and the rate signal, and sets the early ( The difference between the number of pulses of the Early signal and the Rate signal is compared, and if the total value of the difference becomes a certain value or more, an Early signal or a Rate signal is output. The digital filter 3 outputs an output signal SF that is a sign signal of an Early signal [0: n] -Late signal [0: n] (n: natural number). Then, the threshold value of the digital filter 3 is changed by the threshold signal ST of the digital filter output from the multiplexer 7.

  The phase controller 4 is provided between the digital filter 3 and the phase interpolator 5 and inputs an early signal or rate signal output from the digital filter 3 and a phase step signal SS of the phase interpolator. To do. The phase controller 4 generates a control signal for determining a ratio for mixing clocks having different phases. This control signal is changed by the phase step signal SS of the phase interpolator output from the multiplexer 8 and is output as the output signal SPC.

  The phase interpolator 5 is provided between the phase controller 4 and the phase detector 1 and receives an output signal SPC output from the phase controller 4 and a reference clock signal output from a PLL (Phase Locked Loop) circuit. To do. The phase interpolator 5 generates a recovered clock signal having a phase determined by the output signal SPC, which is a phase control signal, and outputs the recovered clock signal to the phase detector 1.

  Here, the phase interpolator 5 is provided with, for example, a phase controller, a binary up / down counter, a mixer, a comparator, and the like, and performs phase control with mbit resolution.

  As shown in FIG. 2, the integrator 6 includes a delay element 11a, a delay element 11b, a delay element 11c, a delay element 11k, an adder 12a, an adder 12b, an adder 12k-1, an adder for one clock cycle. 12k, a comparator 13a, a comparator 13b, and a two-input OR circuit 14 are provided.

  The delay element 11a receives the output signal SF and outputs the previous signal. The delay element 11b receives the signal output from the delay element 11a and outputs the previous signal. The delay element 11c receives the signal output from the delay element 11b and outputs the previous signal. The delay element 11k receives the signal output from the delay element 11k-1 (not shown) and outputs the previous signal.

  The adder 12a receives the signals output from the delay element 11a and the delay element 11b, and outputs the added signal. The adder 12b receives the signals output from the adder 12a and the delay element 11c, and outputs an added signal. The adder 12k-1 receives the signals output from the adder 12k-2 and the delay element 11k (not shown), and outputs the added signal. In the adder 12k-1, the output signal SF is cumulatively added (integrated) in a certain period M. The adder 12k receives the signal (threshold P) output from the adder 12k-1 and the value of M for a certain period, and outputs a signal obtained by subtracting the value of P from M.

  The comparator 13a receives the threshold value P and the threshold value N, and outputs a signal obtained by the comparison operation as an output signal SC1. The comparator 13b receives (MP) and (MN) output from the adder 12k, and outputs a signal obtained by comparison operation as an output signal SC2. The 2-input OR circuit 14 receives the output signal SC1 output from the comparator 13a and the output signal SC2 output from the comparator 13b, and outputs a logically operated signal as the output signal SX.

  Here, the integrator 6 inputs an output signal SF that is an information signal of a sign of an Early signal [0: n] -Late signal [0: n] calculated by the digital filter 3; This signal is monitored for a certain period M and integrated as frequency jitter using a delay element and an adder. Specifically, for example, assuming that an Early signal ≧ rate signal is “High” level and an Early signal <Late signal is “Low” level, a certain period M * When the threshold value P exceeds the threshold value N or (MP) exceeds (MN) during the clock speed time, it is determined as low frequency jitter. If not, it is determined as high frequency jitter. Compared with the case where the difference between the Early signal and the Rate signal itself is counted for a certain period of M * clock cycles, the amount of information in the sign is reduced, so that the Early / Rate of the digital filter 3 (Late) The output result is less affected by the number of data transitions included in the received data within a certain period, ISI caused by reflection and attenuation of the transmission line, and as a result, the transmission line length from the transmitter to the receiver Compared to the case where the difference between the Early signal and the Late signal itself is counted between M * clock cycles for a certain period because the influence is reduced, it is not necessary to consider the dependency of the transmission bit, and the sign information is 1 bit. Thus, the circuit scale of the digital counter can be reduced.

  The multiplexer (first selection means) 7 receives the digital filter threshold T1 and the digital filter threshold T2 having a value different from the digital filter threshold T1, and based on the output signal SX output from the integrator 6, the digital filter threshold T1 or the threshold T2 of the digital filter is selected and output to the digital filter 3 as the threshold signal ST of the digital filter. That is, the threshold value of the digital filter 3 is changed by the threshold signal ST of the digital filter.

  The multiplexer (second selection means) 8 inputs the phase step S1 of the phase interpolator and the phase step S2 of the phase interpolator having a value different from the phase step S1, and based on the output signal SX output from the integrator 6, The phase step S1 of the phase interpolator or the phase step S2 of the phase interpolator is selected and output to the phase interpolator 5 as the phase step signal SS of the phase interpolator. That is, the phase step of the phase interpolator 5 is changed by the phase step signal SS of the phase interpolator.

  Here, the threshold value of the digital filter is set to two and the phase step of the phase interpolator is set to two. However, the number is not necessarily limited to two and may be set to three or more.

  Next, the characteristics of the CDR circuit will be described with reference to FIG. FIG. 3 is a diagram showing the relationship between the jitter frequency and the jitter tolerance, the solid line (a) in the diagram shows the characteristics of this embodiment, and the broken line (b) shows the characteristics when the conventional cutoff frequency is low. The broken line (c) is a diagram showing the characteristics when the conventional cutoff frequency is high. Here, the conventional circuit is a CDR circuit in which the integrator for integrating the jitter frequency is not provided, and the threshold value of the digital filter and the phase step of the phase interpolator are set to constant values.

  As shown in FIG. 3B, conventionally, when the cut-off frequency is set low for the purpose of improving the resistance to high frequency noise, the low frequency noise resistance on the low jitter frequency side deteriorates (jitter tolerance). Reduction). Also, as shown in FIG. 3C, conventionally, when the cutoff frequency is set high for the purpose of improving the resistance to low frequency noise, the resistance of high frequency noise on the higher jitter frequency side is degraded (10 MHz). Jitter tolerance decreases due to the occurrence of a dip centered around the area.

  On the other hand, as shown in FIG. 3A, in the present embodiment, the threshold value of the digital filter and the value of the phase step of the phase interpolator can be changed based on the output signal SX output from the integrator 6. In addition, since the optimum value can be set, the allowable jitter value is improved over the entire jitter frequency.

  As described above, in the CDR circuit of this embodiment, the phase detector 1, the serial-parallel converter 2, the digital filter 3, the phase controller 4, the phase interpolator 5, the integrator 6, the multiplexer 7, and the multiplexer 8 are provided. Provided. The integrator 6 receives an output signal SF that is an information signal of the sign of the Early signal [0: n] -Rate signal [0: n] calculated by the digital filter 3, and inputs this signal. Monitoring is performed for a certain period M, and a signal integrated as frequency jitter using a delay element and an adder is output as an output signal SX. The multiplexer 7 receives the threshold T1 of the digital filter and the threshold T2 of the digital filter having a value different from the threshold, and based on the output signal SX output from the integrator 6, the threshold T1 of the digital filter or the threshold T2 of the digital filter Is output to the digital filter 3 as the threshold signal ST of the digital filter. The multiplexer 8 receives the phase step S1 of the phase interpolator and the phase step S2 of the phase interpolator having a value different from that of the phase interpolator, and based on the output signal SX output from the integrator 6, the phase step S1 of the phase interpolator. Alternatively, the phase step S2 of the phase interpolator is selected and output to the phase interpolator 5 as the phase step signal SS of the phase interpolator.

  For this reason, the threshold value of the digital filter and the phase step of the phase interpolator can be set to optimum values, and the cutoff frequency can be controlled adaptively. Therefore, even when the latency of the digital filter increases, an increase in the dip amount of the frequency jitter tolerance can be suppressed, and the jitter tolerance can be improved over the entire jitter frequency than before. it can.

  In this embodiment, the serial-parallel converter 2 is provided between the phase detector 1 and the digital filter 3. However, an Early signal and a Rate signal output from the phase detector 1 are used. You may make it input into the digital filter 3 directly.

  Next, a CDR circuit according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 4 is a diagram showing a case where frequency jitter near 1.5 / (M * clock cycle) is inputted, and FIG. 5 is a block diagram showing an integrator. In this embodiment, the configuration of the integrator is changed.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 4, when a frequency jitter in the vicinity of 1.5 / (M * clock cycle) is input, if the value of threshold N / predetermined period M is set to approximately 2/3 or more, the embodiment In the case of 1, the possibility of misrecognizing from “Low” determination of the cutoff frequency as “High” determination occurs. Therefore, in this embodiment, the integrator is changed in order to prevent erroneous recognition. The CDR circuit of this embodiment has the same configuration as that of the first embodiment except for the integrator.

  As shown in FIG. 5, the integrator 6a includes a delay element 11a, a delay element 11b, a delay element 11c, a delay element 11k, a delay element 11aa, a delay element 11ka, an adder 12a, an adder 12b, and an adder 12k-1. , Adder 12k, adder 12aa, adder 12 (k-1) a, adder 12ka, comparator 13a, comparator 13b, comparator 13c, comparator 13d, 2-input OR circuit 14, 2-input OR circuit 14a , And a two-input AND circuit 15 are provided.

  The integrator 6a has a sign of an early signal [0: n] -rate signal [0: n] calculated by the digital filter 3 for two periods, a certain period M and another certain period Ma. The output signal SF that is an information signal is monitored.

  Here, the delay element 11a, delay element 11b, delay element 11c, delay element 11k, adder 12a, adder 12b, adder 12k-1, adder 12k, comparator 13b, comparator 13c, and 2-input OR circuit Reference numeral 14 denotes the same configuration and operation as in the first embodiment, and a description thereof will be omitted.

  The monitoring of the fixed period Ma of the output signal SF, which is the information signal of the sign of the Early signal [0: n] -Late signal [0: n] calculated by the digital filter 3, is performed by delay elements 11aa, This is performed using a delay element 11ka, an adder 12aa, an adder 12 (k-1) a, an adder 12ka, a comparator 13c, a comparator 13d, and a two-input OR circuit 14a.

  The delay element 11aa receives the signal output from the delay element 11k and outputs the previous signal. The delay element 11ka receives the signal output from the delay element 11 (k-1) (not shown) and outputs the previous signal.

  The adder 12aa receives the signals output from the adder 12k-1 and the delay element 11aa and outputs the added signal. The adder 12 (k-1) a receives signals output from the adder 12 (k-2) a (not shown) and the delay element 11ka, and outputs an added signal (threshold Pa). In the adder 12 (k−1) a, the output signal SF is cumulatively added (integrated) for a predetermined period Ma. The adder 12ka receives the threshold value Ma and the threshold value Pa, and outputs a signal obtained by subtracting the value of Pa from Ma.

  The comparator 13c receives the threshold value Pa and the threshold value Na, and outputs a signal obtained by the comparison operation as the output signal SC1a. The comparator 13d receives (Ma-Pa) and (Ma-Na) output from the adder 12ka, and outputs a signal obtained by the comparison operation as an output signal SC3. The 2-input OR circuit 14a receives the output signal SC1a output from the comparator 13c and the output signal SC2a output from the comparator 13d, and outputs a logically operated signal as the output signal SX2.

  The 2-input OR circuit 14 receives the output signal SC1 output from the comparator 13a and the output signal SC2 output from the comparator 13b, and outputs a logically operated signal as the output signal SX1. The 2-input AND circuit 15 receives the output signal SX1 output from the 2-input OR circuit 14 and the output signal SX2 output from the 2-input OR circuit 14a, and outputs a logically operated signal as the output signal SX.

  The integrator 6a receives an output signal SF, which is an information signal of the sign of the Early signal [0: n] -Rate signal [0: n] calculated by the digital filter 3, and inputs this signal. Monitoring is performed in a certain period M and another certain period Ma, and the frequency jitter is integrated using a delay element and an adder, and AND of both is performed. For this reason, when a frequency jitter in the vicinity of 1.5 / (M * clock cycle) is input, even if the value of threshold N / predetermined period M is set to approximately 2/3 or more, the cutoff is performed in this embodiment. It is possible to avoid erroneous recognition from “Low” determination of the frequency as “High” determination.

  Next, the characteristics of the CDR circuit will be described with reference to FIG. FIG. 6 is a diagram showing the relationship between the jitter frequency and the jitter tolerance, the solid line (a) in the diagram shows the characteristics of the present embodiment, and the broken line (b) shows the characteristics of the first embodiment.

  As shown in FIG. 6B, in the first embodiment, when frequency jitter near 1.5 / (M * clock cycle) is input, the value of threshold N / predetermined period M is approximately 2/3 or more. When the parameters are set, the tolerance of high frequency noise on the higher jitter frequency side deteriorates (the allowable jitter value decreases due to the occurrence of a dip centered around 24 MHz). This dip level is smaller than the conventional level.

  On the other hand, as shown in FIG. 6 (a), in this embodiment, monitoring is performed for a certain period M and another certain period Ma, and based on an output signal SX output from an integrator 6a obtained by ANDing them. Thus, the threshold value of the digital filter and the value of the phase step of the phase interpolator can be changed as appropriate, and the jitter tolerance is improved over the entire jitter frequency.

  As described above, in the CDR circuit of the present embodiment, the phase detector 1, the serial-parallel converter 2, the digital filter 3, the phase controller 4, the phase interpolator 5, the integrator 6a, the multiplexer 7, and the multiplexer 8 are provided. Provided. The integrator 6a receives an output signal SF, which is an information signal of the sign of the Early signal [0: n] -Rate signal [0: n] calculated by the digital filter 3, and inputs this signal. Monitoring is performed in a certain period M and another certain period Ma, and the frequency jitter is integrated using a delay element and an adder, and AND of both is performed.

  For this reason, when a frequency jitter near 1.5 / (M * clock cycle) is input, even if the value of threshold N / predetermined period M is set to approximately 2/3 or more, the cutoff frequency “Low” is set. It is possible to avoid erroneous recognition from “determination” to “High” determination. The cutoff frequency can be controlled adaptively. Therefore, even when the latency of the digital filter increases, an increase in the dip amount of the frequency jitter tolerance can be suppressed, and the jitter tolerance can be improved over the entire jitter frequency than before. it can. Further, even when the threshold value N / the constant period M value is set to approximately 2/3 or more, an increase in the dip amount of the allowable value of frequency jitter on the high frequency side can be suppressed. Furthermore, by reducing the amount of information in the code, it is not necessary to consider the dependency of the transmission bit.

  Next, a CDR circuit according to Embodiment 3 of the present invention will be described with reference to the drawings. 7 is a block diagram showing the configuration of the CDR circuit, FIG. 8 is a block diagram showing the integrator, FIG. 9 is a block diagram showing the offset pattern generator, and FIG. 10 is a diagram showing the operation of the FSM circuit. In this embodiment, an offset pattern generator is provided in the CDR circuit.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 7, the CDR circuit 40a includes a phase detector 1, a serial-parallel converter 2, a digital filter 3, a phase controller 4, a phase interpolator 5, a multiplexer 7, a multiplexer 8, an integrator 21, and An offset pattern generator 22 is provided.

  The CDR circuit 40a adaptively controls the cutoff frequency. For example, it can support SSC (Speed Spectrum Clock) system that tracks low frequency jitter, monitors the ratio of setting the cut-off frequency high over a certain period, and if the set threshold is exceeded, the offset pattern is one step The integrator 21 passes an increment / decrement signal and a signal indicating the direction thereof to the offset pattern generator 22, and the optimum offset value is searched adaptively to optimize the offset pattern.

  In the conventional CDR circuit in the SSC system that tracks to low frequency jitter, the Early (0: n) and the rate (Late) are used over a relatively long period so as to correspond to the SSC (for example, 30 to 33 KHz). ) Integrate [0: n], detect the difference between the frequency of the recovered clock signal and the data rate based on the integrated edge information, and input the information to the offset pattern generator. For this reason, in order to integrate edge data over a long period, the configuration of the CDR circuit becomes large. Further, it is necessary to track the SSC until the integrator generates an offset pattern, and since the cutoff frequency is always set high, it is vulnerable to sine wave jitter caused by cross-coupling of various signals.

  As shown in FIG. 8, the integrator 21 is provided with integrators 6 and 9. The integrator 21 outputs an output signal SX, an output signal SC1, an output signal SC2, and an output signal SC3. The integrator 9 includes a delay element 11ab, a delay element 11bb, a delay element 11kb, an adder 12ab, an adder 12 (k-1) b, and a comparator 13e.

  The integrator 9 integrates the output signal SF, which is an information signal of the sign of the Early signal [0: n] -rate signal [0: n], by the integrator 6 over a certain period M (an output signal ( The low frequency noise detected signal) SX is input, this signal is monitored for a certain period S, and integrated as a frequency offset using a delay element and an adder.

  The delay element 11ab receives the output signal SX and outputs the previous signal. The delay element 11bb receives the signal output from the delay element 11ab and outputs the previous signal. The delay element 11 kb receives the signal output from the delay element 11 (k−1) b (not shown) and outputs the previous signal.

  The adder 12ab receives the signals output from the delay element 11ab and the delay element 11bb, and outputs the added signal. The adder 12 (k-1) b receives signals output from the adder 12 (k-2) b and the delay element 11kb (not shown), and outputs a signal subjected to addition processing. In the adder 12 (k−1) b, the output signal SX is cumulatively added (integrated) in a certain period S.

  The comparator 13e receives the threshold value L and the threshold value R, and outputs a signal obtained by the comparison operation as an output signal SC3. The output signal SC3 is fed back to the adder 12 (k−1) b, and when the output signal SC3 changes to “High” level, the value accumulated and added by the adder 12 (k−1) b is reset.

  As shown in FIG. 9, the offset pattern generator 22 is provided with an FSM (Finite State Machine) circuit 10 and a delay element 11c. The offset pattern generator 22 receives the output signals SC1 to SC3, and when the signal SX in which the low frequency noise is detected is “High” equal to or higher than R / S which is a specific ratio in a certain period S, the output signal SC3 is output. Assert, receive the output signals SC1 and SC3 indicating the frequency offset direction, and output an output signal SQ that is an optimal frequency offset value.

  The FSM circuit 10 is also called a finite state machine, and includes, for example, a programmable logic controller, a combinational logic circuit, and a flip-flop.

  For example, as shown in FIG. 10, the FSM circuit 10 receives the output signals SC1 to SC3, and for example, when the value Q of the output signal SQ is set as (-3 <Q <3), the FSM circuit 10 increments by one step (increment). ) / Decrement and search (serial addition) for the optimum value.

  Next, the operation of the CDR circuit will be described with reference to FIG. FIG. 11 is a flowchart showing the operation of the CDR circuit.

  As shown in FIG. 11, in the CDR circuit 40a, the frequency offset value Q is first updated using the offset pattern generator 22 (step S1).

  Next, it is determined whether or not the offset correction value that is the offset value Q of the updated frequency is an optimal value. If it is determined that this correction value is an optimum value, the CDR circuit 40a is locked (step S2).

  If it is determined that the correction value is not an optimum value, the offset value of the frequency is increased or decreased by the offset pattern generator 22 (step S3).

  The operation is advanced until the offset value Q of the increased or decreased frequency is updated and this offset correction value is determined to be the optimum value.

  As described above, in the CDR circuit of this embodiment, the phase detector 1, the serial-parallel converter 2, the digital filter 3, the phase controller 4, the phase interpolator 5, the multiplexer 7, the multiplexer 8, the integrator 21, and An offset pattern generator 22 is provided. The integrator 21 is provided with integrators 6 and 9. The integrator 9 integrates the output signal SF, which is the information signal of the sign of the Early signal [0: n] −Late signal [0: n], by the integrator 6 over a certain period M. , And this signal is monitored for a certain period S and integrated as a frequency offset using a delay element and an adder. The offset pattern generator 22 includes an FSM circuit 10 and a delay element 11c, and receives the output signals SC1 to SC3 and outputs an output signal SQ that is an optimal frequency offset value.

  For this reason, in addition to the effects of the first embodiment, it is not necessary to integrate edge data over a long period, so that the circuit configuration can be simplified as compared with the conventional case. Further, since it is not necessary to track the SSC until the integrator generates an offset pattern, it is not always necessary to set the cutoff frequency high, and it is robust against sine wave jitter caused by cross-coupling of various signals. Can be.

  Next, a CDR circuit according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 12 is a block diagram showing the configuration of the CDR circuit. In this embodiment, the CDR circuit is provided with a voltage controlled oscillator instead of the phase interpolator.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 12, the CDR circuit 40b includes a phase detector 1, a serial-parallel converter 2, a digital filter 3, a multiplexer 7, a multiplexer 8, a voltage controlled oscillator 23, a voltage controller 24, and an integrator 31. Provided. The CDR circuit 40b dynamically controls the cutoff frequency by dynamically controlling the threshold of the digital filter and the voltage step of the voltage controlled oscillator.

  The voltage controller 24 is provided between the digital filter 3 and the voltage controlled oscillator 23, and receives an early signal or a rate signal output from the digital filter 3 and a voltage step signal SV of the voltage controlled oscillator. To do. The voltage controller 24 generates a control signal for determining a ratio for mixing the clocks. This control signal is changed by the voltage step signal SV of the voltage controlled oscillator output from the multiplexer 8 and is output as the output signal SVC.

  The voltage controlled oscillator 23 is provided between the voltage controller 24 and the phase detector 1 and receives the output signal SVC output from the voltage controller 24. The voltage controlled oscillator 23 generates a recovered clock signal determined by the output signal SVC that is a voltage step signal and outputs the recovered clock signal to the phase detector 1.

  The integrator 31 receives a parallel Early signal and a Rate signal, monitors the signal for a predetermined period M, and outputs a signal integrated as a frequency jitter as an output signal SX.

  The multiplexer (second selection means) 8 inputs the voltage step V1 of the voltage controlled oscillator and the voltage step V2 of the voltage controlled oscillator having a value different from that of the voltage controlled oscillator, and based on the output signal SX output from the integrator 31. The voltage step V1 of the voltage controlled oscillator or the voltage step V2 of the voltage controlled oscillator is selected and output to the voltage controller 24 as the voltage step signal SV of the voltage controlled oscillator. That is, the voltage step of the voltage controlled oscillator 23 is changed by the voltage step signal SV of the voltage controlled oscillator.

  As described above, in the CDR circuit of this embodiment, the phase detector 1, the serial-parallel converter 2, the digital filter 3, the multiplexer 7, the multiplexer 8, the voltage controlled oscillator 23, the voltage controller 24, and the integrator 31 are included. Provided. The integrator 31 receives a parallel Early signal and a Rate signal, monitors the signal for a predetermined period M, and outputs a signal integrated as a frequency jitter as an output signal SX. The voltage controller 24 is provided between the digital filter 3 and the voltage controlled oscillator 23, and receives an early signal or a rate signal output from the digital filter 3 and a voltage step signal SV of the voltage controlled oscillator. To do. The voltage controller 24 generates a control signal for determining a ratio for mixing the clocks. This control signal is changed by the voltage step signal SV of the voltage controlled oscillator output from the multiplexer 8 and is output as the output signal SVC. The voltage controlled oscillator 23 receives the output signal SVC output from the voltage controller 24, generates a recovered clock signal determined by the output signal SVC that is a voltage step signal, and outputs the recovered clock signal to the phase detector 1.

  For this reason, the threshold value of the digital filter and the voltage step of the voltage controlled oscillator can be set to optimum values, and the cutoff frequency can be controlled adaptively. Therefore, even when the latency of the digital filter increases, an increase in the dip amount of the frequency jitter tolerance can be suppressed, and the jitter tolerance can be improved over the entire jitter frequency than before. it can. Further, by reducing the amount of information in the code, it is not necessary to consider the dependency of the transmission bit. Further, it is not necessary to input a reference clock signal output from a PLL circuit or the like from the outside.

  Next, a CDR circuit according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 13 is a circuit diagram showing the configuration of the CDR circuit. In this embodiment, a DLL circuit is provided in the CDR circuit instead of the phase interpolator.

  In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

  As shown in FIG. 13, the CDR circuit 40c includes a phase detector 1, a serial-parallel converter 2, a digital filter 3, a phase controller 4, a multiplexer 7, a multiplexer 8, a DLL circuit 25, and an integrator 31. It is done. The CDR circuit 40 dynamically controls the cutoff frequency by dynamically controlling the threshold value of the digital filter and the phase step of the output of the DLL circuit.

  A DLL (Delay Locked Loop) circuit 25 is provided between the phase controller 4 and the phase detector 1 and receives an output signal SPC output from the phase controller 4. The PLL circuit 25 generates a recovered clock signal having a phase determined by the output signal SPC that is a phase control signal, and outputs the recovered clock signal to the phase detector 1.

  The integrator 31 receives a parallel Early signal and a Rate signal, monitors the signal for a predetermined period M, and outputs a signal integrated as a frequency jitter as an output signal SX.

  As described above, the CDR circuit of this embodiment includes the phase detector 1, the serial-parallel converter 2, the digital filter 3, the phase controller 4, the multiplexer 7, the multiplexer 8, the DLL circuit 25, and the integrator 31. It is done. The integrator 31 receives a parallel Early signal and a Rate signal, monitors the signal for a predetermined period M, and outputs a signal integrated as a frequency jitter as an output signal SX. The DLL circuit 25 receives the output signal SPC output from the phase controller 4, generates a recovered clock signal having a phase determined by the output signal SPC that is a phase control signal, and outputs the recovered clock signal to the phase detector 1.

  For this reason, the threshold value of the digital filter and the phase step of the phase interpolator can be set to optimum values, and the cutoff frequency can be controlled adaptively. Therefore, even when the latency of the digital filter increases, an increase in the dip amount of the frequency jitter tolerance can be suppressed, and the jitter tolerance can be improved over the entire jitter frequency than before. it can. Further, by reducing the amount of information in the code, it is not necessary to consider the dependency of the transmission bit. Further, it is not necessary to input a reference clock signal output from a PLL circuit or the like from the outside.

  The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

  For example, in the embodiment, the multiplexer is used as selection means for selecting the threshold value of the digital filter, the phase interpolator phase step, and the like, but a switch or the like may be used instead of the multiplexer. In the embodiment, a non-linear type (for example, Alexander Detector) phase detector is used as a phase detector, but a linear type (for example, Hogge Detector) phase detector that inputs a recovered clock signal and an input data signal may be used. Good.

The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) An input data signal and a restored clock signal are input, a transition edge of the input data signal is detected, a binary relation of the early / rate is determined for a positional relationship with respect to the data of the restored clock signal, a restored data signal, A phase detector that generates one early signal and a first rate signal, and the restored data signal, the first early signal, and the first rate signal are input, the restored data signal, the first rate signal And a serial-parallel converter that performs serial / parallel conversion on the first rate signal, a second early signal and a second rate signal that have been serial / parallel converted, and a predetermined time interval. Then, the pulse number difference between the second early signal and the second rate signal is compared, and if the total difference value exceeds a certain value, the third A digital filter that outputs a first signal or a third rate signal and outputs a sign signal having a value obtained by subtracting the number of pulses of the second rate signal from the second early signal at a predetermined time interval; The third early signal and the third rate signal output from the filter are input, a phase controller that generates a phase step signal that determines a phase step, the phase step signal and the reference clock signal are input, Based on the phase step signal, a phase interpolator that generates the recovered clock signal and the code signal are input, the code signal is monitored for a first fixed period and integrated as a frequency jitter to obtain a first signal. And generating a frequency jitter by monitoring the code signal for a second fixed period that is different from the first fixed period. And an integrator that takes the AND of the first and second signals and outputs as an output signal, and two or more threshold values having different values of the digital filter are input, and the output signal of the integrator A threshold value of the digital filter is selected based on the first selection means for outputting the selected threshold value of the digital filter to the digital filter, and two or more values having different phase steps are input, and the integrator A CDR circuit comprising: second selection means for selecting the value of the phase step based on the output signal of the output signal and outputting the selected value of the phase step to the phase control circuit.

(Supplementary Note 2) An input data signal and a recovered clock signal are input, a transition edge of the input data signal is detected, a binary relation of the early / rate is determined for a positional relationship with respect to the data of the recovered clock signal, a recovered data signal, A phase detector that generates one early signal and a first rate signal, and the restored data signal, the first early signal, and the first rate signal are input, the restored data signal, the first rate signal And a serial-parallel converter that performs serial / parallel conversion on the first rate signal, a second early signal and a second rate signal that have been serial / parallel converted, and a predetermined time interval. And comparing the difference in the number of pulses between the second early signal and the second rate signal, and if the total value of the differences is greater than a certain value, A digital filter that outputs a first signal or a third rate signal and outputs a sign signal having a value obtained by subtracting the number of pulses of the second rate signal from the second early signal at a predetermined time interval; The third early signal and the third rate signal output from the filter are input, a phase controller that generates a phase step signal that determines a phase step, the phase step signal and the reference clock signal are input, Based on the phase step signal, a phase interpolator that generates the recovered clock signal and the code signal are input, the code signal is monitored for a first fixed period and integrated as a frequency jitter to obtain a first signal. An integrator for generating and monitoring the first signal for a second period of time and integrating as a frequency offset to generate a second signal; Two or more threshold values having different digital filter values are input, the threshold value of the digital filter is selected based on the first signal of the integrator, and the selected threshold value of the digital filter is output to the digital filter. Two or more values having different phase steps are input, and the value of the phase step is selected based on the first signal of the integrator, and the value of the selected phase step is selected. A CDR circuit comprising: a second selection unit that outputs a signal to the phase control circuit; and an offset pattern generator that selects an optimal frequency offset value based on a signal output from the integrator.

(Supplementary Note 3) The CDR circuit according to Supplementary Note 2, wherein the offset pattern generator is provided with the FSM circuit that calculates an optimal frequency offset value from a plurality of signals output from the integrator.

(Supplementary Note 4) An input data signal and a recovered clock signal are input, a transition edge of the input data signal is detected, a binary relation of the early / rate is determined for a positional relationship with respect to the data of the recovered clock signal, a recovered data signal, A phase detector that generates one early signal and a first rate signal, and the restored data signal, the first early signal, and the first rate signal are input, the restored data signal, the first rate signal And a serial-parallel converter that performs serial / parallel conversion on the first rate signal, a second early signal and a second rate signal that have been serial / parallel converted, and a predetermined time interval. And comparing the difference in the number of pulses between the second early signal and the second rate signal, and if the total value of the differences is greater than a certain value, A digital filter that outputs a first signal or a third rate signal and outputs a sign signal having a value obtained by subtracting the number of pulses of the second rate signal from the second early signal at a predetermined time interval; The third early signal and the third rate signal output from the filter are input, a voltage controller that generates a voltage step signal that determines a voltage step, the voltage step signal is input, and the voltage step signal A voltage controlled oscillator for generating the recovered clock signal, the second early signal, and the second rate signal are input, and the second early signal and the second rate signal are received for a certain period of time. An integrator that monitors and integrates as frequency jitter and outputs it as an output signal, and two or more threshold values having different values of the digital filter The first selection means for selecting the threshold value of the digital filter based on the input signal and the output signal of the integrator, and outputting the selected threshold value of the digital filter to the digital filter. Second selection means for inputting the above values, selecting the value of the voltage step based on the output signal of the integrator, and outputting the selected value of the voltage step to the voltage control circuit. CDR circuit to perform.

(Supplementary Note 5) An input data signal and a restored clock signal are input, a transition edge of the input data signal is detected, a binary relation of the early / rate is determined for a positional relationship with respect to the data of the restored clock signal, a restored data signal, A phase detector that generates one early signal and a first rate signal, and the restored data signal, the first early signal, and the first rate signal are input, the restored data signal, the first rate signal And a serial-parallel converter that performs serial / parallel conversion on the first rate signal, a second early signal and a second rate signal that have been serial / parallel converted, and a predetermined time interval. And comparing the difference in the number of pulses between the second early signal and the second rate signal, and if the total value of the differences is greater than a certain value, A digital filter that outputs a first signal or a third rate signal and outputs a sign signal having a value obtained by subtracting the number of pulses of the second rate signal from the second early signal at a predetermined time interval; A phase controller that generates a phase step signal for determining a phase step by inputting the third early signal and the third rate signal output from a filter; and the phase step signal is input to the phase step signal. Based on this, the DLL circuit for generating the recovered clock signal, the second early signal and the second rate signal are input, and the second early signal and the second rate signal are monitored for a certain period of time. The integrator that integrates as frequency jitter and outputs as an output signal, and two or more threshold values with different values of the digital filter are input. A first selection means for selecting a threshold value of the digital filter based on the output signal of the integrator, and outputting the selected threshold value of the digital filter to the digital filter; And a second selection means for selecting the value of the phase step based on the output signal of the integrator and outputting the selected value of the phase step to the phase control circuit. CDR circuit.

(Supplementary Note 6) The CDR circuit according to any one of Supplementary notes 1 to 5, wherein the selection unit is a multiplexer.

1 is a block diagram showing a configuration of a CDR circuit according to Embodiment 1 of the present invention. 1 is a block diagram showing a configuration of an integrator according to Embodiment 1 of the present invention. The figure which shows the relationship of the jitter frequency and jitter tolerance which concern on Example 1 of this invention, the solid line (a) in a figure is a figure which shows the characteristic of a present Example, and a broken line (b) is a case where the conventional cutoff frequency is low The figure which shows the characteristic of this, and the broken line (c) is a figure which shows the characteristic in case the conventional cutoff frequency is high. The figure which shows the case where the frequency jitter of 1.5 / (M * clock cycle) vicinity which concerns on Example 2 of this invention is input. The block diagram which shows the integrator which concerns on Example 2 of this invention. The figure which shows the relationship of the jitter frequency and jitter tolerance which concern on Example 2 of this invention, the solid line (a) in a figure shows the characteristic of a present Example, and the broken line (b) shows the characteristic of Example 1 . FIG. 6 is a block diagram illustrating a configuration of a CDR circuit according to a third embodiment of the invention. FIG. 6 is a block diagram illustrating an integrator according to a third embodiment of the invention. The block diagram which shows the offset pattern generator which concerns on Example 3 of this invention. FIG. 10 is a diagram illustrating an operation of the FSM circuit according to the third embodiment of the present invention. 10 is a flowchart showing the operation of the CDR circuit according to the third embodiment of the present invention. FIG. 9 is a block diagram illustrating a configuration of a CDR circuit according to a fourth embodiment of the invention. FIG. 9 is a block diagram illustrating a configuration of a CDR circuit according to a fifth embodiment of the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Phase detector 2 Serial-parallel converter 3 Digital filter 4 Phase control circuit 5 Phase interpolator 6, 6a, 9, 21, 31 Integrator 7, 8 Multiplexer 10 FSM circuit 11a, 11b, 11c, 11k, 11aa, 11ka 11ab, 11bb, 11kb, 11c Delay elements 12a, 12b, 12k-1, 12k, 12aa, 12 (k-1) a, 12ka, 12ab, 12 (k-1) b Adders 13a, 13b, 13c, 13d , 13e Comparator 14, 14a 2-input OR circuit 15 2-input AND circuit 22 Offset pattern generator 23 Voltage-controlled oscillator 24 Voltage controller 25 DLL circuit 40, 40a, 40b, 40c CDR circuit M, Ma, S Fixed period N, P, Na, Pa, L Threshold values SC1, SC2, SF, SPC, SX, Sc1a, SC2a, X1, SX2, SC3, SQ, CVC Output signals S1, S2 Phase interpolator phase step SS Phase interpolator phase step signal ST Digital filter threshold signal SV Voltage controlled oscillator voltage step signal T1, T2 Digital filter threshold V1 , V2 Voltage step of voltage controlled oscillator

Claims (5)

  1. An input data signal and a recovered clock signal are input, a transition edge of the input data signal is detected, a binary relation of the early / rate is determined for the positional relationship of the recovered clock signal with respect to the data, and the recovered data signal, the first early signal And a phase detector for generating a first rate signal;
    The first early signal and the first rate signal are input, the pulse number difference between the first early signal and the first rate signal is compared at a predetermined time interval, and the total value of the differences is not less than a certain value. The second early signal or the second rate signal is output when the value becomes the value, and the sign signal has a value obtained by subtracting the number of pulses of the first rate signal from the first early signal at a predetermined time interval. A digital filter that outputs
    A phase controller that receives the second early signal and the second rate signal output from the digital filter and generates a phase step signal that determines a phase step;
    An integrator that inputs the code signal, monitors the code signal for a certain period, integrates it as frequency jitter, and outputs it as an output signal;
    Two or more threshold values having different values of the digital filter are input, the threshold value of the digital filter is selected based on the output signal of the integrator, and the selected threshold value of the digital filter is output to the digital filter. First selection means;
    Two or more values having different phase steps are input, a value of the phase step is selected based on the output signal of the integrator, and a second value of the selected phase step is output to the phase control circuit. And means for selecting
    A CDR circuit, wherein the recovered clock signal is generated and input to the phase detector based on the phase step signal output from the phase controller.
  2. An input data signal and a recovered clock signal are input, a transition edge of the input data signal is detected, a binary relation of the early / rate is determined for the positional relationship of the recovered clock signal with respect to the data, and the recovered data signal, the first early signal And a phase detector for generating a first rate signal;
    The first early signal and the first rate signal are input, the pulse number difference between the first early signal and the first rate signal is compared at a predetermined time interval, and the total value of the differences is not less than a certain value. The second early signal or the second rate signal is output when the value becomes the value, and the sign signal has a value obtained by subtracting the number of pulses of the first rate signal from the first early signal at a predetermined time interval. A digital filter that outputs
    A phase controller that receives the second early signal and the second rate signal output from the digital filter and generates a phase step signal that determines a phase step;
    The code signal is input, the code signal is monitored for a first fixed period and integrated as frequency jitter to generate a first signal, and the code signal is in a period different from the first fixed period. An integrator that monitors a certain period of time 2 and integrates it as frequency jitter to generate a second signal, takes the AND of the first and second signals, and outputs the result as an output signal;
    Two or more threshold values having different values of the digital filter are input, the threshold value of the digital filter is selected based on the output signal of the integrator, and the selected threshold value of the digital filter is output to the digital filter. First selection means;
    Two or more values having different phase steps are input, a value of the phase step is selected based on the output signal of the integrator, and a second value of the selected phase step is output to the phase control circuit. And means for selecting
    A CDR circuit, wherein the recovered clock signal is generated and input to the phase detector based on the phase step signal output from the phase controller.
  3. An input data signal and a recovered clock signal are input, a transition edge of the input data signal is detected, a binary relation of the early / rate is determined for the positional relationship of the recovered clock signal with respect to the data, and the recovered data signal, the first early signal And a phase detector for generating a first rate signal;
    The first early signal and the first rate signal are input, the pulse number difference between the first early signal and the first rate signal is compared at a predetermined time interval, and the total value of the differences is not less than a certain value. The second early signal or the second rate signal is output when the value becomes the value, and the sign signal has a value obtained by subtracting the number of pulses of the first rate signal from the first early signal at a predetermined time interval. A digital filter that outputs
    A phase controller that receives the second early signal and the second rate signal output from the digital filter and generates a phase step signal that determines a phase step;
    The code signal is input, the code signal is monitored for a first fixed period and integrated as frequency jitter to generate a first signal, and the first signal is monitored for a second fixed period to obtain a frequency offset. An integrator that integrates to generate a second signal;
    Two or more threshold values having different values of the digital filter are input, the threshold value of the digital filter is selected based on the first signal of the integrator, and the threshold value of the selected digital filter is input to the digital filter. First selection means for outputting;
    Two or more values having different phase steps are input, the value of the phase step is selected based on the first signal of the integrator, and the selected value of the phase step is output to the phase control circuit. A second selection means;
    An offset pattern generator that selects an optimal frequency offset value based on a signal output from the integrator;
    The recovered clock signal is generated and input to the phase detector based on the phase step signal output from the phase controller, and the optimum frequency offset selected by the offset pattern generator is included. A CDR circuit, wherein a value is output to the phase control circuit.
  4.   In the integration period, the integrator determines low frequency jitter when the ratio of the same code in the integration result of the code signal exceeds a first threshold, and determines that it is high frequency jitter if it does not exceed the first threshold. The CDR circuit according to claim 1, wherein the CDR circuit is characterized in that:
  5. An input data signal and a recovered clock signal are input, a transition edge of the input data signal is detected, a binary relation of the early / rate is determined for the positional relationship of the recovered clock signal with respect to the data, and the recovered data signal, the first early signal And a phase detector for generating a first rate signal;
    The restored data signal, the first early signal, and the first rate signal are input, and the restored data signal, the first early signal, and the first rate signal are subjected to serial / parallel conversion. A parallel converter;
    The second early signal and the second rate signal are input, the pulse number difference between the second early signal and the second rate signal is compared at a predetermined time interval, and the total value of the differences is not less than a certain value The third early signal or the third rate signal is output when the value is equal to the value, and the sign signal has a value obtained by subtracting the number of pulses of the second rate signal from the second early signal at a predetermined time interval. And a phase controller that receives the third early signal and the third rate signal output from the digital filter and generates a phase step signal that determines a phase step;
    A phase interpolator that receives the phase step signal and the reference clock signal and generates the recovered clock signal based on the phase step signal;
    An integrator that inputs the code signal, monitors the code signal for a certain period, integrates it as frequency jitter, and outputs it as an output signal;
    Two or more threshold values having different values of the digital filter are input, the threshold value of the digital filter is selected based on the output signal of the integrator, and the selected threshold value of the digital filter is output to the digital filter. First selection means;
    Two or more values having different phase steps are input, a value of the phase step is selected based on the output signal of the integrator, and a second value of the selected phase step is output to the phase control circuit. And means for selecting
    A CDR circuit comprising:
JP2007085776A 2007-03-28 2007-03-28 Cdr circuit Pending JP2008245134A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011130435A (en) * 2009-12-17 2011-06-30 Intel Corp Adaptive digital phase locked loop
US8472278B2 (en) 2010-04-09 2013-06-25 Qualcomm Incorporated Circuits, systems and methods for adjusting clock signals based on measured performance characteristics
WO2015149298A1 (en) * 2014-04-02 2015-10-08 Qualcomm Incorporated Fast timing recovery in energy efficient ethernet devices
CN105720972A (en) * 2016-01-15 2016-06-29 北京大学(天津滨海)新一代信息技术研究院 Speculation type clock data recovery circuit system for high-speed data transmission receiver

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011130435A (en) * 2009-12-17 2011-06-30 Intel Corp Adaptive digital phase locked loop
US8472278B2 (en) 2010-04-09 2013-06-25 Qualcomm Incorporated Circuits, systems and methods for adjusting clock signals based on measured performance characteristics
WO2015149298A1 (en) * 2014-04-02 2015-10-08 Qualcomm Incorporated Fast timing recovery in energy efficient ethernet devices
CN105720972A (en) * 2016-01-15 2016-06-29 北京大学(天津滨海)新一代信息技术研究院 Speculation type clock data recovery circuit system for high-speed data transmission receiver

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