JP2008224535A - Semiconductor integrated circuit and its inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten a test time, and to reduce manufacturing cost. <P>SOLUTION: In a programmable logic circuit 100, a circuit configuration can be changed corresponding to configuration information. In a programmable input/output interface 101, input cells 301a, 301b use either of an output from ASIC 11 and scan-in as input corresponding to a scan shift signal SHIFT, and select scan-out corresponding to a select signal SELECT and the configuration information. Output cells 302a, 302b use either of an output from the programmable logic circuit 100 and scan-in as input corresponding to a test mode signal MODE, and select scan-out corresponding to the select signal SELECT and the configuration information. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a reconfigurable logic capable of reconfiguring a circuit configuration after manufacturing the semiconductor integrated circuit, and more particularly to a test method including a reconfigurable logic and a dedicated circuit for a specific application.

  In various types of digital signal processing, various semiconductor integrated circuits such as a microcomputer, a DSP (digital signal processing processor), a dedicated circuit (ASIC: Application Specific Integrated Circuit) for specific use, and a storage element (memory) are used. In recent years, programmable logic circuits (such as microcomputers and DSPs) whose processing can be changed by a program after circuit manufacture, programmable logic circuits whose circuit configuration can be freely changed after circuit manufacture, particularly reconfigurable logic that can switch the circuit configuration at high speed Is attracting attention.

  The reconfigurable logic can freely change the circuit configuration without newly manufacturing a semiconductor integrated circuit when there is a change in standard or specification, a circuit failure, or the like. On the other hand, the ASIC cannot freely change the circuit configuration after the LSI is manufactured, but has a feature that it has a small area and high speed and low power compared to the reconfigurable logic.

With the progress of miniaturization of semiconductor integrated circuits, development of a system-on-chip (SoC) that realizes a system with one LSI is progressing. In recent SoCs, in order to cope with rising manufacturing costs and product development in a short period of time, development of SoCs that combine the flexibility of programmable logic circuits and the enhancement of ASIC performance is required. As a conventional technique, there is a technique such as Japanese Patent No. 3392062 (Patent Document 1). The integrated circuit described in Patent Document 1 enables an LSI including a programmable logic circuit and an ASIC to be manufactured by an AIC interface that connects a programmable logic array and a specific application block.
Japanese Patent No. 3391262

  However, in the prior art, when shipping an LSI including a programmable logic circuit and an ASIC, in order to test the connection between the programmable logic circuit and the ASIC, the programmable logic circuit and the programming memory cell in the AIC interface are configured in a predetermined state (configuration). It is necessary to This requires time for configuration, resulting in increased test time and increased cost.

  An object of the present invention is to solve the above problems, and it is possible to perform a connection test between a programmable logic circuit and a dedicated circuit without configuring the programmable logic circuit, and to reduce the manufacturing cost.

  According to the present invention, a semiconductor integrated circuit includes a dedicated circuit configured for a predetermined application, a programmable logic circuit whose circuit configuration can be changed according to configuration information, the dedicated circuit, and the programmable logic circuit. And a programmable input / output interface having a normal state for transferring a signal between the dedicated circuit and the programmable logic circuit and a test state for executing a connection test with the dedicated circuit. When the input / output interface is in the normal state, the input / output interface has a circuit configuration corresponding to the configuration information. Configure.

  According to the semiconductor integrated circuit, the dedicated circuit and the programmable input / output interface can be controlled by the control signal from the outside. Thereby, the configuration of the programmable logic circuit can be omitted in the connection test between the dedicated circuit and the programmable input / output interface, and the test time can be shortened. Further, it is possible to reduce the manufacturing cost.

  Preferably, the semiconductor integrated circuit further includes a clock supply unit that supplies a first clock, the programmable logic circuit receives a first clock from the clock supply unit, and the programmable input / output interface supplies the clock supply The second clock of the programmable logic circuit is selected as the operation clock in the normal state, and the second clock is selected in the test state. One clock is selected as the operation clock.

  According to the semiconductor integrated circuit, the clock from the clock supply unit dedicatedly connected to the programmable input / output interface can be used as the operation clock for the programmable input / output interface when the scan test is performed.

  Preferably, the programmable input / output interface includes a plurality of scan cells connected in series and supplied with the control signal to each of the plurality of scan cells, and each of the plurality of scan cells is dedicated to the normal state. When a signal is transferred between the circuit and the programmable logic circuit and in the test state, the circuit operates as a part of the first scan chain according to the control signal.

  Preferably, at least one of the plurality of scan cells is an input cell for transferring a signal from the dedicated circuit to the programmable logic circuit in the normal state, and the control signal includes a test mode signal, A scan shift signal and a selector signal, wherein the input cell has a first clock input terminal for receiving a first clock from the clock supply unit, and a second clock for receiving a second clock from the programmable logic circuit. An input terminal; a first signal input terminal for receiving a signal or test data from a scan cell arranged in a preceding stage of the input cell; a second signal input terminal for receiving a signal from the dedicated circuit; and the test mode A clock applied to one of the first and second clock input terminals according to a signal A first selector that selects, a second selector that selects a signal applied to one of the first and second signal input terminals according to the scan shift signal, and a selection by the first selector A first holding unit that holds a signal selected by the second selector in synchronization with the generated clock; a signal from the first holding unit according to the selector signal and the configuration information; and And a third selector that selects one of the signals given to the second signal input terminal and outputs the signal as an output of the input cell.

  According to the semiconductor integrated circuit, the output of the dedicated circuit can be input to the programmable logic circuit, and the connection test can be performed without configuring the programmable logic circuit.

  Preferably, at least one of the plurality of scan cells is an output cell for transferring a signal from the programmable logic circuit to the dedicated circuit in the normal state, and the output cell is supplied from the clock supply unit. A third clock input terminal for receiving the first clock, a fourth clock input terminal for receiving the second clock from the programmable logic circuit, and a signal or test data from the scan cell arranged in the preceding stage of the output cell. A third signal input terminal for receiving the signal, a fourth signal input terminal for receiving a signal from the programmable logic circuit, and the third and fourth clock input terminals according to a test mode signal included in the control signal. A fourth selector for selecting a clock to be given to either one of the test modes; And a fifth selector for selecting a signal applied to one of the third and fourth signal input terminals according to the signal, and the fifth selector in synchronization with the clock selected by the fourth selector. A second holding unit for holding a signal selected by the selector, a signal from the second holding unit and a signal selected by the fifth selector in accordance with the selector signal and the configuration information A sixth selector that selects any one of them and outputs the signal as an output of the output cell.

  According to the semiconductor integrated circuit, the output of the programmable logic circuit can be input to the dedicated circuit, and the connection test can be performed without configuring the programmable logic circuit.

  Preferably, the dedicated circuit includes a plurality of flip-flops arranged in series and constituting a second scan chain according to the control signal, a second scan chain including the plurality of flip-flops, and the plurality of scan cells. And a logic circuit sandwiched between them.

  According to the semiconductor integrated circuit, the connection test can be performed by the first scan chain of the programmable input / output interface and the second scan chain of the dedicated circuit.

  Preferably, the first-stage scan cell among the plurality of scan cells receives the output of the last-stage flip-flop among the plurality of flip-flops.

  According to the semiconductor integrated circuit, a scan chain of the dedicated circuit and the programmable input / output interface can be configured.

  According to the present invention, the method for inspecting the semiconductor integrated circuit includes the step (a) of changing the programmable input / output interface from the normal state to the test state, and the test state in the step (a). Shifting test data into the programmable input / output interface, setting the test data in the programmable input / output interface (b), and causing the programmable input / output interface to output the test data set in step (b). (C) causing the programmable input / output interface to capture the operation result; and (d) shifting the test result captured in the step (c) to the programmable input / output interface. Equipped with a.

  According to the semiconductor integrated circuit inspection method, the connection test between the dedicated circuit and the programmable input / output interface can be performed without configuring the programmable logic circuit.

  As described above, the connection test between the programmable input / output interface and the dedicated circuit can be performed without configuring the programmable logic circuit, and the test time and the manufacturing cost can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
<Configuration>
FIG. 1 shows a configuration of a semiconductor integrated circuit (LSI) according to the first embodiment of the present invention. The LSI 1 includes an application specific circuit (ASIC) 11, a reconfigurable unit 12, and a clock supply unit 13. FIG. 1 shows an example of the configuration of the LSI 1. The LSI 1 may include an input / output cell, a pad, a microcomputer, a DSP, a memory, and the like in addition to the ASIC 11 and the reconfigurable unit 12.

  The ASIC 11 is configured for a specific application, processes a signal from the outside of the LSI 1 and outputs the processed signal to the reconfigurable unit 12, and processes a signal from the reconfigurable unit 12 to output the LSI 1 to the outside. Output to. The ASIC 11 is connected to the reconfigurable unit 12 via a plurality of wirings L11a and L11b.

  The reconfigurable unit 12 includes a programmable logic circuit 100, programmable input / output interfaces 101 and 102, and a configuration interface 103.

  The programmable logic circuit 100 can change a circuit configuration according to configuration information, and a plurality of switches that connect a plurality of programmable elements (PE) 111, a programmable element (PE) 111, and a wiring L112 in a switchable manner. (Not shown). Note that the programmable element (PE) 111 and the wiring L112 only need to have function operations and connections determined based on the configuration information. The programmable logic circuit 100 is connected to each of the programmable input / output interfaces 101 and 102 and the configuration interface 103 via a plurality of wirings L112.

  The configuration information is information indicating a desired circuit configuration for each of the programmable logic circuit 100 and the programmable input / output interfaces 101 and 102. Configuration information is set via the configuration interface 103. Note that the configuration information may be stored anywhere on the same silicon.

  The programmable input / output interface 101 can change the circuit configuration in accordance with the configuration information, transfers a signal from the ASIC 11 to the programmable logic circuit 100, and transfers a signal from the programmable logic circuit 100 to the ASIC 10. The programmable input / output interface 102 transfers a signal from outside the LSI 1 to the programmable logic circuit 100 and transfers a signal from the programmable logic circuit 100 to the outside of the LSI 1. Note that, like the programmable input / output interface 101, the programmable input / output interface 102 may be connected to another ASIC.

  The clock supply unit 13 receives a clock from outside the LSI 1 and supplies the clock to each of the ASIC 10 and the reconfigurable unit 12. In the programmable logic circuit 100, a clock is supplied to each of the programmable elements (PE) 111 via the wiring L112.

  The programmable input / output interface 101 receives a test mode signal MODE, a scan shift signal SHIFT, and a selector signal SELECT, and forms a scan chain for a connection test according to these control signals. The ASIC 11 includes a plurality of flip-flops, and these flip-flops operate as a scan chain according to the scan shift signal SHIFT. The test mode signal MODE, the scan shift signal SHIFT, and the selector signal SELECT are control signals output from a control unit (not shown), for example, and the signal level is controlled by the control unit.

<Internal configuration>
FIG. 2 shows an internal configuration of the dedicated circuit 11 and the programmable input / output interface 101 shown in FIG.

  The dedicated circuit 11 includes a plurality of flip-flops 201a to 201d and logic circuits 202a and 202b. The flip-flops 201a to 201d constitute a scan chain according to the scan shift signal SHIFT, the first flip-flop 201a receives the scan-in signal SIN (test data), and the output of the final flip-flop 201d is scanned out. It is output as a signal SOUT (test result).

  Programmable input / output interface 101 includes input cells 301a and 301b and output cells 302a and 302b connected in series. The first-stage input cell 301a receives a scan-in signal SIN (test data). The output of the output cell 302b at the final stage is output as a scan-out signal SOUT (test result). Each of the input cells 301a and 301b either latches the signal from the ASIC 11 or transfers the signal from the ASIC 11 as it is without latching according to the configuration information. Similarly, the output cell 302a latches the signal from the programmable logic circuit 100 or transfers the signal from the programmable logic circuit 100 as it is without latching according to the configuration information.

  Note that the connection order of the input cell and the output cell may be any. The scan chain of the programmable input / output interface 101 may be connected to the scan chain of the ASIC 11. That is, the first stage input cell 301a may receive the output of the flip-flop 201d instead of the scan-in signal SIN.

<Input cell>
FIG. 3 shows an internal configuration of the input cell 301a shown in FIG. The input cell 301a includes control terminals 401a to 401d, an OR circuit 402, clock input terminals 403a and 403b, signal input terminals 404a and 404b, selectors 405a to 405c, a flip-flop 406, and output terminals 407 and 408. including.

  The control terminals 401a to 401d receive a test mode signal MODE, a scan shift signal SHIFT, a selector signal SELECT, and configuration information Info, respectively. The OR circuit 402 outputs a logical sum of the selector signal SELECT and the configuration information Info. The clock input terminals 403a and 403b receive the clock CLKa (first clock) from the clock supply unit 13 and the clock CLKb (second clock) from the programmable logic circuit 100, respectively. The signal input terminal 404a (first signal input terminal) is a scan-in terminal and receives test data or an output of an input cell (or output cell) arranged in the previous stage. The signal input terminal 404b (second signal input terminal) receives the output of the ASIC 11.

  The selector 405a (first selector) selects the clock CLKa of the clock input terminal 403a if the test mode signal MODE is "1", and the clock CLKb of the clock input terminal 403b if the test mode signal MODE is "0". And the selected clock is supplied as the clock CLK1. The selector 405b (second selector) selects the signal IN1a (scan-in) of the signal input terminal 404a if the scan shift signal SHIFT is “1”, and the signal input terminal if the scan shift signal SHIFT is “0”. The signal IN1b 404b is selected and the selected signal is supplied. The flip-flop 406 (first holding unit) holds the signal from the selector 405b in synchronization with the clock CLK1 from the selector 405a.

  The selector 405c (third selector) selects the output Q1 of the flip-flop 406 if the output of the OR circuit 402 is “0”, and the signal at the signal input terminal 404b if the output of the OR circuit 402 is “1”. Select IN1b. The output OUT1 of the selector 405c is supplied to the programmable logic circuit 100 via the output terminal 407 and also to the output terminal 408. The output terminal 408 is a scan-out terminal, and is connected to the input of an input cell (or output cell) arranged in the subsequent stage, or test results are sequentially taken out from the output terminal 408.

  Note that the configuration information Info may be on the same silicon as the input cell 301a. The input cell 301b has the same configuration as the input cell 301a.

<Output cell>
FIG. 4 shows an internal configuration of the output cell 302a shown in FIG. The output cell 302a includes control terminals 501a to 501c, an OR circuit 502, clock input terminals 503a and 503b, signal input terminals 504a and 504b, selectors 505a to 505c, a flip-flop 506, and output terminals 507 and 508. including.

  The control terminals 501a, 501b, and 501c receive a test mode signal MODE, a selector signal SELECT, and configuration information Info, respectively. The OR circuit 502 outputs a logical sum of the selector signal SELECT and the configuration information Info. Clock input terminals 503a and 503b receive clock signals CLKa (clock from clock supply unit 13) and CLKb (clock from programmable logic circuit 100), respectively. The signal input terminal 504a (third signal input terminal) is a scan-in terminal, and receives test data or an output of an input cell (or output cell) arranged in the previous stage. The signal input terminal 504b (fourth signal input terminal) receives the output of the programmable logic circuit 100.

  The selector 505a (fourth selector) selects the clock CLKa of the clock input terminal 503a if the test mode signal MODE is "1", and the clock CLKb of the clock input terminal 503b if the test mode signal MODE is "0". And the selected clock is supplied as the clock CLK2. The selector 505b (fifth selector) selects the signal IN2a (scan-in) of the signal input terminal 504a if the test mode signal MODE is "1", and the signal input terminal if the test mode signal MODE is "0". The signal IN2b of 504b is selected and the selected signal is supplied. The flip-flop 506 (second holding unit) holds the signal from the selector 505b in synchronization with the clock CLK2 from the selector 505a.

  The selector 505c (sixth selector) selects the output Q1 of the flip-flop 506 if the output of the OR circuit 502 is “0”, and selects the output of the selector 505b if the output of the OR circuit 502 is “1”. To do. The output OUT2 of the selector 505c is supplied to the ASIC 11 via the output terminal 507 and also to the output terminal 508. The output terminal 508 is a scan-out terminal, and is connected to the input of an input cell (or output cell) arranged in the subsequent stage, or test results are sequentially taken out from the output terminal 508.

  Note that the configuration information Info may be on the same silicon as well as inside the output cell 302a. The output cell 302b has the same configuration as the output cell 302a.

<Operation of input cell>
Next, the operation of the input cell shown in FIG. 3 will be described with reference to FIG. Here, it is assumed that the programmable logic circuit 100 and the programmable input / output interface 101 are not configured. That is, in the programmable input / output interface 101, the configuration information included in each of the input cell and the output cell is “0”. The clock CLKb from the programmable logic circuit 100 is “0” because it is not configured in the initial state.

  At time t0 (initial state), the test mode signal MODE becomes “1” to perform the connection test, and the clock CLKa is selected as the clock CLK1 of the flip-flop 406. Further, the scan shift signal SHIFT becomes “1”, and the signal IN 1 a (scan-in) is selected as the input of the flip-flop 406. Further, since the configuration information Info is “0” and the selector signal SELECT is “0”, the output Q1 of the flip-flop 406 is selected as the output OUT1 (scanout).

  At time t1, the flip-flop 406 latches the signal IN1a (scan-in), the output Q1 of the flip-flop 406 becomes “0”, and the signal OUT1 becomes “0”. Further, the scan shift signal SHIFT becomes “0”, and the signal IN1b (output of the ASIC 11) is selected as the input of the flip-flop 406.

  At time t2, the flip-flop 406 latches the signal IN1b (the output of the ASIC 11), the output Q1 of the flip-flop 406 becomes “1”, and the output OUT1 becomes “1”. Further, the scan shift signal SHIFT becomes “1”, and the signal IN 1 a (scan-in) is selected as the input of the flip-flop 406.

  At time t3, the flip-flop 406 latches the signal IN1a (scan-in), the output Q1 of the flip-flop 406 becomes “0”, and the output OUT1 becomes “0”. Further, the scan shift signal SHIFT becomes “0”, and the signal IN1b (output of the ASIC 11) is selected as the input of the flip-flop 406.

  At time t4, the flip-flop 406 latches the signal IN1b (the output of the ASIC 11), the output Q1 of the flip-flop 406 becomes “0”, and the output OUT1 becomes “0”. Further, the scan shift signal SHIFT becomes “1”, and the signal IN 1 a (scan-in) is selected as the input of the flip-flop 406.

  At time t5, the selector signal SELECT becomes “1”, and the signal IN1b (output of the ASIC 11) is selected as the output OUT1. Therefore, the value of the output OUT1 is the value “0” of the signal IN1b.

  Thus, by setting the scan shift signal SHIFT to “1”, the value of the flip-flop 406 can be freely set via the scan-in terminal (signal input terminal 404a). Thereby, test data can be set in the input cell.

  Further, the signal IN1b of the flip-flop 406 or the signal input terminal 404b can be output to the scan-out terminal (output terminal 408) by the selector signal SELECT. Accordingly, a connection test between the selector 405c and the flip-flop 406 and a connection test between the selector 405c and the signal input terminal 404b can be performed.

  Further, in the connection test between the programmable input / output interface 101 and the ASIC 11, since the signal from the scan-out terminal (output terminal 408) is compared and verified outside the LSI, what value is output from the output terminal 408? It may be.

  Further, by setting the test mode signal MODE to “1”, the clock CLKa from the clock supply unit 13 is selected, so that the clock CLKb from the programmable logic circuit 100 is not necessary.

  Note that the configuration information Info may remain in the initial state in the connection test, and the configuration information Info may be rewritten depending on whether or not the output of the ASIC 11 is latched by the flip-flop 406 during application processing. That is, the flip-flop 406 can be shared by connection tests and applications.

<Operation of output cell>
Next, the operation of the output cell 302 shown in FIG. 4 will be described with reference to FIG. Like the input cell, the configuration information included in the output cell 302 is “0”, and the clock CLKb from the programmable logic circuit 100 is “0”.

  At time t0 (initial state), in order to perform the connection test, the test mode signal MODE becomes “1”, the clock CLKa is selected as the clock CLK2 of the flip-flop 506, and the signal IN2a ( Scan in) is selected. Since the configuration information Info is “0” and the selector signal SELECT is “0”, the output Q2 of the flip-flop 406 is selected as the output OUT2 (scanout). Further, the signal IN2a (scan-in) becomes “0”.

  At time t1, the flip-flop 506 latches the signal IN2a (scan-in), the output Q2 of the flip-flop 506 becomes “0”, and the signal OUT2 becomes “0”.

At time t2, the flip-flop 506 latches the signal IN2a (scan-in), the output Q2 of the flip-flop 506 becomes “1”, and the signal OUT2 becomes “1”. At time t3, the selector signal SELECT becomes “1”. Therefore, the output of the selector 505b is selected as the output OUT2 (scanout). Therefore, the value of the output OUT2 becomes the value “1” of the signal IN2a.

  At time t4 as well as at time t3, since the output of the selector 505b is selected as the output OUT2 (scanout), the value of the output OUT2 becomes the value “0” of the signal IN2a.

  Thus, by setting the test mode signal MODE to “1”, it is possible to always latch the input of the flip-flop 506 and the signal (scan-in) of the signal input terminal 504a. Thereby, the output of the programmable logic circuit 100 becomes unnecessary.

  In addition, the output of the flip-flop 506 or the signal (scan-in) of the signal input terminal 504a can be output to the output terminals 507 and 508 by the selector signal SELECT. Accordingly, a connection test between the selector 505c and the flip-flop 506 and a connection test between the selector 505c and the selector 505b can be performed.

  Further, by setting the test mode signal MODE to “1”, the clock CLKa from the clock supply unit 13 is selected, so that the clock CLKb from the programmable logic circuit 100 is not necessary.

  Note that the configuration information Info may remain in the initial state in the connection test, and the configuration information Info can be rewritten depending on whether or not the output of the programmable logic circuit 100 is latched by the flip-flop 506 during application processing. That's fine. That is, the flip-flop 506 can be shared by connection tests and applications.

<Inspection method>
Next, the procedure of the connection test between the ASIC 11 and the programmable logic circuit 100 shown in FIG. 2 will be described with reference to FIG. Here, in the initial state, the test mode signal MODE, the scan shift signal SHIFT, and the selector signal SELECT are all “0”.

[Step ST101]
First, in order to perform a connection test, the test mode signal MODE is changed from “0” to “1”. Thereby, in the programmable input / output interface 101, the clock CLKa from the clock supply unit 13 is selected as the operation clock in each of the input cells 301a and 301b and the output cells 302a and 302b. In the output cell 302a, not the output of the programmable logic circuit 100 but the output of the previous input cell 301b is selected as the input of the output cell 302a (that is, scan-in is selected as the input of the output cell 302a). ). The same applies to the output cell 302b.

[Step ST102]
Further, the scan shift signal SHIFT is changed from “0” to “1”. Thereby, in each of the input cells 301a and 301b, scan-in is selected as the input of the input cell. Similarly, in the ASIC 11, in each of the flip-flops 201a to 201d, scan-in (output of the preceding flip-flop) is selected as the input of the flip-flop. Thus, a scan chain is constructed in each of the programmable input / output interface 101 and the ASIC 11.

[Step ST103]
Next, the test data is shifted into the signal input terminal 404a of the input cell 301a. Accordingly, test data is set in the input cells 301a and 301b and the output cells 302a and 302b. Similarly, the test data is shifted in the flip-flop 201a, and the test data is set in the flip-flops 201a to 201d.

[Step ST104]
Next, the scan shift signal SHIFT is changed from “1” to “0”.

[Step ST105]
Next, the selector signal SELECT is set to “0” or “1”. Thus, after a predetermined operation is executed between the ASIC 11 and the programmable input / output interface 101, the input cells 301a and 301b and the output cells 302a and 302b capture the test results. The flip-flops 201a to 201d also capture test results.

[Step ST106]
Next, the scan shift signal SHIFT is changed from “0” to “1”. Thus, the input cells 301a and 301b and the output cells 302a and 302b again form a scan chain, and the test result is shifted out from the output terminal 408 of the output cell 302b. Similarly, the flip-flops 201a to 201d also constitute a scan chain, and the test result is shifted out of the flip-flop 201d. In this way, the test result can be obtained. When the test is repeated, after the processing of steps ST101 and ST102 is executed, the next test data may be shifted in at step ST103. When the scan test is completed, pass or fail is determined.

<Effect>
As described above, according to the present embodiment, there is no need to set configuration information in order to configure a programmable input / output interface or a programmable logic circuit to a predetermined state, and control signals (test mode signal, scan shift signal) , And selector signal) can be used to control the programmable input / output interface. Therefore, the connection test between the programmable input / output interface and the ASIC can be performed without configuring the programmable logic circuit.

  In addition, it is possible to easily generate a connection test pattern between the ASIC and the programmable input / output interface by using an ATPG (Auto Pattern Generator) tool. Thereby, the configuration can be omitted, and the test time can be shortened.

  In addition, since the flip-flops of the input cell and the output cell can be shared in the application and the connection test, it is not necessary to add a new circuit for the connection test, and the area can be minimized. As a result, it brings about the effect of reducing the manufacturing cost.

  Note that the select signals given to the input cells and the output cells of the programmable input / output interface may all have the same signal level or may be different.

  As described above, since the present invention can perform a scan test without configuring a programmable logic circuit, a semiconductor integrated circuit on which a dedicated circuit and a programmable logic circuit are mounted, a test method thereof, and the like Useful.

1 is a block diagram showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention. It is a figure which shows the structure of ASIC and programmable input / output interface which were shown in FIG. FIG. 3 is a diagram illustrating a configuration of an input cell illustrated in FIG. 2. It is a figure which shows the structure of the output cell shown in FIG. FIG. 4 is a timing chart for explaining the operation by the input cell shown in FIG. 3. FIG. 5 is a timing chart for explaining an operation by the output cell shown in FIG. 4. 3 is a flowchart for explaining a connection test method between the ASIC and the programmable logic circuit shown in FIG. 2.

Explanation of symbols

1 Semiconductor integrated circuit (LSI)
11 Application-specific dedicated circuit (ASIC)
12 reconfigurable unit 13 clock supply unit L11a, L11b wiring 100 programmable logic circuit 101, 102 programmable input / output interface 103 configuration interface 111 programmable element (PE)
L112 wiring 201a-201d flip-flops 202a, 202b logic circuits 301a, 301b input cells 302a, 302b output cells 401a-401d, 501a-501c control terminals 402, 502 OR circuits 403a, 403b, 503a, 503b clock input terminals 404a, 404b, 504a, 504b Signal input terminals 405a-405c, 505a-505c Selector 406, 506 Flip-flops 407, 408, 507, 508 Output terminals

Claims (8)

A dedicated circuit configured for a given application;
A programmable logic circuit whose circuit configuration can be changed according to configuration information;
Programmable intervening between the dedicated circuit and the programmable logic circuit, and having a normal state for transferring a signal between the dedicated circuit and the programmable logic circuit and a test state for executing a connection test between the dedicated circuit and the dedicated circuit I / O interface and
When the programmable input / output interface is in the normal state, the programmable input / output interface has a circuit configuration according to the configuration information. When the programmable input / output interface is in the test state, the programmable input / output interface has a first configuration in accordance with an external control signal. A semiconductor integrated circuit comprising a scan chain. In claim 1,
A clock supply unit for supplying a first clock;
The programmable logic circuit receives a first clock from the clock supply unit,
The programmable input / output interface receives a first clock from the clock supply unit and a second clock of the programmable logic circuit, and in the normal state, selects the second clock as an operation clock, A semiconductor integrated circuit, wherein the first clock is selected as an operation clock in a test state. In claim 2,
The programmable input / output interface is
A plurality of scan cells connected in series and each of which is provided with the control signal;
Each of the plurality of scan cells transfers a signal between the dedicated circuit and the programmable logic circuit when in the normal state, and according to the control signal when in the test state. A semiconductor integrated circuit which operates as a part of the first scan chain. In claim 3,
At least one of the plurality of scan cells is an input cell for transferring a signal from the dedicated circuit to the programmable logic circuit in the normal state,
The control signal is
Including a test mode signal, a scan shift signal, and a selector signal;
The input cell is
A first clock input terminal for receiving a first clock from the clock supply unit;
A second clock input terminal for receiving a second clock from the programmable logic circuit;
A first signal input terminal for receiving a signal or test data from a scan cell arranged in a preceding stage of the input cell;
A second signal input terminal for receiving a signal from the dedicated circuit;
A first selector that selects a clock applied to one of the first and second clock input terminals in response to the test mode signal;
A second selector that selects a signal applied to one of the first and second signal input terminals according to the scan shift signal;
A first holding unit for holding a signal selected by the second selector in synchronization with a clock selected by the first selector;
According to the selector signal and the configuration information, one of the signal from the first holding unit and the signal given to the second signal input terminal is selected, and the signal is input to the input cell. A semiconductor integrated circuit comprising: a third selector that outputs as an output. In claim 3 or claim 4,
At least one of the plurality of scan cells is an output cell for transferring a signal from the programmable logic circuit to the dedicated circuit in the normal state,
The output cell is
A third clock input terminal for receiving a first clock from the clock supply unit;
A fourth clock input terminal for receiving a second clock from the programmable logic circuit;
A third signal input terminal for receiving a signal or test data from a scan cell arranged in the preceding stage of the output cell;
A fourth signal input terminal for receiving a signal from the programmable logic circuit;
A fourth selector that selects a clock applied to one of the third and fourth clock input terminals according to a test mode signal included in the control signal;
A fifth selector for selecting a signal applied to one of the third and fourth signal input terminals according to the test mode signal;
A second holding unit that holds the signal selected by the fifth selector in synchronization with the clock selected by the fourth selector;
According to the selector signal and the configuration information, one of the signal from the second holding unit and the signal selected by the fifth selector is selected, and the signal is used as the output of the output cell. A semiconductor integrated circuit comprising: a sixth selector for outputting. In any one of Claims 3-5,
The dedicated circuit is
A plurality of flip-flops arranged in series and constituting a second scan chain in response to the control signal;
A semiconductor integrated circuit comprising: a second scan chain composed of the plurality of flip-flops; and a logic circuit sandwiched between the plurality of scan cells. In claim 6,
The first stage scan cell among the plurality of scan cells receives the output of the last stage flip-flop among the plurality of flip-flops. A method for inspecting a semiconductor integrated circuit according to claim 1, comprising:
Changing the programmable input / output interface from the normal state to the test state;
(B) shifting test data into the programmable input / output interface tested in step (a) and setting the test data in the programmable input / output interface;
(C) causing the programmable input / output interface to output the test data set in step (b), and causing the programmable input / output interface to capture a calculation result;
And (d) shifting the test result captured in the step (c) to the programmable input / output interface.

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