JP2008199045A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method enabling effective utilization of a region on a semiconductor layer. <P>SOLUTION: The semiconductor device 100 includes: an SOI substrate 110, comprising a semiconductor substrate 120, an insulating layer 130 provided on the semiconductor substrate 120, and an SOI layer 140 provided on the insulating layer 130. On the semiconductor substrate 120, there is an impurity diffusion layer 122. The impurity diffusion layer 122 is electrically connected to a wiring layer 162 provided on the SOI layer 140. The impurity diffusion layer 122 can function as the wiring layer or a resistance layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having an SOI substrate and a manufacturing method thereof.

  Currently, with the demand for higher speed LSI and lower power consumption, a technique for forming an LSI on an SOI substrate has been proposed.

As illustrated in FIG. 11, the SOI substrate 410 has a stacked structure of a semiconductor substrate 420, an insulating layer 430, and a semiconductor layer 440. In general, semiconductor element (eg, MOSFET) 450 is formed in semiconductor layer 440.
JP-A-4-30471

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can effectively use a region on a semiconductor layer.

(Semiconductor device)
(A) The first semiconductor device of the present invention is
A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A semiconductor device including a semiconductor layer provided on the insulating layer,
In the semiconductor substrate, a first conductive layer is provided,
The first conductive layer is electrically connected to a second conductive layer provided on or in the semiconductor layer.

  In the present invention, the first conductive layer is provided in the semiconductor substrate. For this reason, the region above the semiconductor layer can be effectively used as much as the first conductive layer is formed on the semiconductor substrate. As a result, the degree of integration of the semiconductor device can be improved.

  The first conductive layer may be constituted by an impurity diffusion layer. By forming the first conductive layer from the impurity diffusion layer, the first conductive layer can be formed on the semiconductor substrate by ion implantation of impurities.

  The first conductive layer can function as a wiring layer. Alternatively, the first conductive layer can function as a resistance layer.

  A connection hole for connecting the first conductive layer and the second conductive layer may be provided, and a contact layer may be provided in the connection hole. A side wall may be provided in the connection hole.

(B) The second semiconductor device of the present invention is
A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A semiconductor device including a semiconductor layer provided on the insulating layer,
In the semiconductor substrate, a contact region is provided,
The contact region is electrically connected to a conductive layer provided on or in the semiconductor layer, and has a function of flowing charges to the semiconductor substrate.

  The second semiconductor device of the present invention has a contact region in the semiconductor substrate. The contact region is electrically connected to the conductive layer and has a function of flowing charge to the semiconductor substrate. As a result, the charge charged in the semiconductor layer can be passed through the semiconductor substrate.

  The contact region may include an impurity diffusion layer.

  A PN junction may be formed by the contact region and the semiconductor substrate. Specifically, there are the following two modes.

  (1) First, the semiconductor substrate is N-type, and the contact region is P-type. In this case, a current can be passed through the semiconductor substrate.

  (2) Second, the semiconductor substrate is P-type, and the contact region is N-type. In this case, charged electrons can flow through the semiconductor substrate.

  A connection hole for connecting the contact region and the conductive layer may be provided, and a contact layer may be provided in the connection hole. A side wall may be provided in the connection hole.

(C) The third semiconductor device of the present invention is
A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A semiconductor device including a semiconductor layer provided on the insulating layer,
In the semiconductor substrate, a first electrode is provided,
In the semiconductor layer, a second electrode is provided,
The first electrode, the second electrode, and the insulating layer constitute a capacitive element.

  In the present invention, the first electrode is provided on the semiconductor substrate, and the second electrode is provided on the semiconductor layer. The insulating layer interposed between the semiconductor substrate and the semiconductor layer functions as a dielectric film of the capacitor element. In other words, the capacitor can be formed without forming the capacitor on the semiconductor layer. For this reason, the region above the semiconductor layer can be used effectively. As a result, the degree of integration of the semiconductor device can be improved.

  The first electrode may be composed of a first impurity diffusion layer. The second electrode may be constituted by a second impurity diffusion layer.

  The first electrode may be electrically connected to a conductive layer provided on or in the semiconductor layer. A connection hole for connecting the first electrode and the conductive layer may be provided, and a contact layer may be provided in the connection hole. A side wall may be provided in the connection hole.

(Method for manufacturing semiconductor device)
(A) A first method for manufacturing a semiconductor device according to the present invention includes:
A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: a semiconductor layer provided on the insulating layer;
A step of ion-implanting impurities into a predetermined region of the semiconductor substrate to form a first conductive layer composed of an impurity diffusion layer; and a second layer provided on or in the semiconductor layer A step of electrically connecting the conductive layer and the first conductive layer;

  The first conductive layer can function as a wiring layer. Alternatively, the first conductive layer can function as a resistance layer.

And a step of forming a connection hole for electrically connecting the first conductive layer and the second conductive layer; and a step of forming a contact layer in the connection hole. it can.

  Furthermore, a step of forming a sidewall in the connection hole can be included.

(B) A second method for manufacturing a semiconductor device according to the present invention includes:
A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A method of manufacturing a semiconductor device comprising: a semiconductor layer provided on the insulating layer;
In the semiconductor substrate, a contact region is provided,
The contact region is electrically connected to a conductive layer provided on or in the semiconductor layer, and has a function of flowing charge to the semiconductor substrate;
Impurity ion implantation into the semiconductor substrate to form the contact region, and electrically connecting the conductive layer and the contact region.

And a step of forming a connection hole for electrically connecting the contact region and the conductive layer provided in the semiconductor layer, and a step of forming a contact layer in the connection hole. it can.

  Furthermore, a step of forming a sidewall in the connection hole can be included.

(C) A third method of manufacturing a semiconductor device according to the present invention includes:
A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A method of manufacturing a semiconductor device comprising: a semiconductor layer provided on the insulating layer;
Including a step (a) of forming a capacitive element;
The capacitor element includes a first electrode provided on the semiconductor substrate, the insulating layer, and a second electrode provided on the semiconductor layer. The step (a) includes impurities in the semiconductor substrate. A step (a-1) of forming the first electrode composed of the first impurity diffusion layer.

  The step (a) may further include a step (a-2) in which impurities are ion-implanted into the semiconductor layer to form the second electrode composed of the second impurity diffusion layer.

The semiconductor device has a conductive layer provided on or in the semiconductor layer,
A step of forming a connection hole for electrically connecting the first electrode and the conductive layer, and a step of forming a contact layer in the connection hole can be included.

  Furthermore, a step of forming a sidewall in the connection hole can be included.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[First Embodiment]
(Semiconductor device)
The semiconductor device according to the first embodiment will be described below. FIG. 1 is a cross-sectional view schematically showing the semiconductor device according to the first embodiment.

  The semiconductor device 100 includes an SOI substrate 110. The SOI substrate 110 has a stacked structure of a semiconductor substrate 120, an insulating layer 130, and an SOI layer (semiconductor layer) 140. A trench element isolation region 142 is formed in a predetermined region of the SOI layer 140.

  An impurity diffusion layer 122 is formed in the semiconductor substrate 120. The impurity diffusion layer 122 functions as a wiring layer. The impurity concentration of the impurity diffusion layer 122 is defined in consideration of the desired conductivity of the wiring layer.

  A connection hole 150 reaching the impurity diffusion layer 122 is formed in a predetermined region of the SOI substrate 110. A side wall 152 is formed on the side surface of the SOI substrate 110 in the connection hole 150. A contact layer 160 is formed in the connection hole 150. The side wall 152 has a role of preventing the active element region 144 and the contact layer 160 from being short-circuited when the connection hole 150 is formed in the active element region 144. A wiring layer 162 is formed on the SOI layer 140 and the contact layer 160.

  Hereinafter, functions and effects of the semiconductor device according to the first embodiment will be described.

  (A) In the present embodiment, an impurity diffusion layer 122 that functions as a wiring layer is formed in the semiconductor substrate 120. For this reason, the region above the semiconductor layer 140 can be effectively used as much as the impurity diffusion layer 122 is formed in the semiconductor substrate 120. As a result, according to the present embodiment, the degree of integration of the semiconductor device can be improved.

  (B) The impurity diffusion layer 122 functioning as a wiring layer formed on the semiconductor substrate includes a gate electrode 172 in the first transistor region 170 and a gate electrode in the second transistor region 180, as shown in FIG. It can be applied to the case of connecting to H.182. S1 represents a source region, and D1 represents a drain region.

(Method for manufacturing semiconductor device)
A method for manufacturing the semiconductor device according to the first embodiment will be described below. 2 and 3 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the embodiment.

  (A) First, as shown in FIG. 2A, a first resist layer R1 is formed on the SOI layer 140. The first resist layer R1 is opened above the region where the impurity diffusion layer 122 is to be formed.

  Next, an impurity 122a is ion-implanted into the semiconductor substrate 120 using the first resist layer R1 as a mask. Thereby, an impurity diffusion layer 122 is formed in the semiconductor substrate 120. Next, the first resist layer R1 is removed by ashing.

  (B) Next, as shown in FIG. 2B, a trench element isolation region 142 is formed in a predetermined region of the SOI layer 140 by a known method.

  (C) Next, as shown in FIG. 3A, a second resist layer R <b> 2 is formed on the SOI layer 140. The second resist layer R2 is opened above the region where the connection hole 150 is to be formed. Next, using the second resist layer R2 as a mask, the SOI layer 140, the insulating layer 130, and the semiconductor substrate 120 are etched to form the connection hole 150. Examples of the etching method include reactive ion etching. Next, the second resist layer R2 is removed.

  (D) Next, as shown in FIG. 3B, a side wall 152 is formed on the side surface of the SOI substrate 110 in the connection hole 150. The side wall 152 can be formed as follows, for example. An insulating layer (not shown) is formed on the SOI layer 140 so as to fill the connection hole 150. The insulating layer can be formed by, for example, a CVD method. The sidewall 152 can be formed by reactive ion etching of the insulating layer.

  (E) Next, as shown in FIG. 1, a contact layer 160 is formed in the connection hole 150. The contact layer 160 can be formed, for example, by forming a conductive layer filling the connection hole 150 on the SOI layer 140 and etching back the conductive layer. Examples of the material of the contact layer 160 include polysilicon, tungsten, aluminum, and titanium. If necessary, a wetting layer or a barrier layer may be formed in the connection hole 150 before forming the conductive layer.

  Next, a wiring layer 162 having a predetermined pattern is formed on the SOI layer 140. Thus, the semiconductor device 100 according to the first embodiment is formed.

(Modification)
The first embodiment can be modified as follows, for example.

  (1) In the above embodiment, the impurity diffusion layer 122 is caused to function as a wiring layer. However, the impurity diffusion layer 122 may function as a resistance layer. In this case, the impurity concentration of the impurity diffusion layer 122 is defined in consideration of a desired resistance value.

  (2) In the above embodiment, the impurity diffusion layer 122 is connected to the wiring layer 162 formed on the SOI layer 140. However, the present invention is not limited to this, and the impurity diffusion layer 122 may be connected to a conductive layer formed in the SOI layer 140.

  (3) In the above embodiment, the connection hole 160 is formed in the trench element isolation region 142. However, the present invention is not limited to this, and the connection hole 160 may be formed in the active element region 144 as shown in FIG. This modification can be similarly applied to the following embodiments.

[Second Embodiment]
(Semiconductor device)
Hereinafter, a semiconductor device according to the second embodiment will be described. FIG. 5 is a cross-sectional view schematically showing a semiconductor device according to the second embodiment.

  The semiconductor device 200 has an SOI substrate 210. The SOI substrate 210 has a stacked structure of a semiconductor substrate 220, an insulating layer 230, and an SOI layer (semiconductor layer) 240. A trench element isolation region 242 is formed in a predetermined region of the SOI layer 240.

  A first impurity diffusion layer 222 is formed in the semiconductor substrate 220. In the SOI layer 240, a second impurity diffusion layer 244 is formed between the trench element isolation regions 242. The first impurity diffusion layer 222, the insulating layer 230, and the second impurity diffusion layer 244 form a capacitor element 270. That is, the first impurity diffusion layer 222 functions as a lower electrode, the insulating layer 230 functions as a dielectric film, and the second impurity diffusion layer 244 functions as an upper electrode.

  The impurity concentration of the first impurity diffusion layer 222 is defined in consideration of the desired performance of the capacitor 270. The impurity concentration of the second impurity diffusion layer 244 is determined in consideration of the desired performance of the capacitor 270. The thickness of the insulating layer 230 is determined in consideration of the desired performance of the capacitor 270.

  A connection hole 250 reaching the first impurity diffusion layer 222 is formed in a predetermined region of the SOI substrate 210. A side wall 252 is formed on the side surface of the SOI substrate 210 in the connection hole 250. A first contact layer 260 is formed in the connection hole 252. The side wall 252 has a role of preventing the active element region and the first contact layer 260 from being short-circuited when the connection hole 250 is formed in the active element region. A first wiring layer 262 having a predetermined pattern is formed on the SOI layer 240 and the first contact layer 260.

  An interlayer insulating layer 280 is formed on the SOI layer 240 and the first wiring layer 262. A through hole 282 is formed in a predetermined region of the interlayer insulating layer 280. The through hole 282 reaches the second impurity diffusion layer 244. A second contact layer 290 is formed in the through hole 242. A second wiring layer 292 having a predetermined pattern is formed on the interlayer insulating layer 280 and the second contact layer 290.

  Hereinafter, functions and effects of the semiconductor device according to the second embodiment will be described.

  In the present embodiment, the first impurity diffusion layer 222 formed in the semiconductor substrate 220, the insulating layer 230, and the second impurity diffusion layer 244 formed in the semiconductor layer 240 constitute the capacitor element 270. I am letting. Therefore, it is not necessary to form a capacitor on the semiconductor layer 240. As a result, the region on the semiconductor layer 240 can be used effectively. Therefore, the degree of integration of the semiconductor device can be improved.

(Method for manufacturing semiconductor device)
A method for manufacturing a semiconductor device according to the second embodiment will be described below. 6 and 7 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the embodiment.

  (A) First, as shown in FIG. 6A, a first resist layer R1 is formed on the SOI layer 240. The first resist layer R1 is opened above a region where the first impurity diffusion layer 222 is to be formed.

  Next, an impurity 222a is ion-implanted into the semiconductor substrate 220 using the first resist layer R1 as a mask. Thereby, the first impurity diffusion layer 222 is formed in the semiconductor substrate 220. Next, the first resist layer R1 is removed.

  (B) Next, as shown in FIG. 6B, a second resist layer R2 is formed on the SOI layer 240. The second resist layer R2 is opened above a region where the second impurity diffusion layer 244 is to be formed.

  Next, an impurity 244a is ion-implanted into the SOI layer 240 using the second resist layer R2 as a mask. Thereby, the second impurity diffusion layer 244 is formed in the SOI layer 240. Further, when the second impurity diffusion layer 244 is formed, the capacitor element 270 is formed by the first impurity diffusion layer 222, the insulating layer 230, and the first impurity diffusion layer 244. The second resist layer R2 is removed.

  (C) Next, as shown in FIG. 7A, a trench element isolation region 242 is formed in a predetermined region of the SOI layer 240 by a known method.

  (D) Next, as shown in FIG. 7B, a third resist layer R3 is formed on the SOI layer 240. The third resist layer R3 is opened above the region where the connection hole 250 is to be formed.

  Next, using the third resist layer R3 as a mask, the SOI layer 240, the insulating layer 230, and the semiconductor substrate 220 are etched to form connection holes 250. This etching can be performed, for example, by reactive ion etching. Next, the third resist layer R3 is removed.

  (E) Next, as shown in FIG. 7C, a side wall 252 is formed on the side surface of the SOI substrate 210 in the connection hole 250. The sidewall 252 can be formed in the same manner as in the first embodiment, for example.

  Next, the first contact layer 260 is formed in the connection hole 250. The first contact layer 260 can be formed, for example, in the same manner as in the first embodiment. If necessary, a wetting layer or a barrier layer may be formed in the connection hole 250 before forming the conductive layer.

  Next, a first wiring layer 262 having a predetermined pattern is formed on the SOI layer 240.

  (F) Next, as shown in FIG. 5, an interlayer insulating layer 280 made of a silicon oxide layer is formed on the SOI layer 240 and the first wiring layer 262 by a CVD method. Then, a predetermined region of the interlayer insulating layer 280 is selectively removed by etching to form a through hole 282 that reaches the first impurity diffusion layer 244. Thereafter, a second contact layer 290 is formed in the through hole 282. Next, a second wiring layer 292 having a predetermined pattern is formed on the interlayer insulating layer 280 and the second contact layer 290. Thus, the semiconductor device 200 according to the second embodiment is formed.

(Modification)
In the second embodiment, for example, the following changes are possible.

  In the above embodiment, the first impurity diffusion layer 222 is connected to the first wiring layer 262 formed on the SOI layer 240. However, the present invention is not limited to this, and the first impurity diffusion layer 222 may be connected to a conductive layer formed in the SOI layer 240.

[Third Embodiment]
(Semiconductor device)
The semiconductor device according to the third embodiment will be described below. FIG. 8 is a cross-sectional view schematically showing a semiconductor device according to the third embodiment.

  The semiconductor device 300 includes an SOI substrate 310. The SOI substrate 310 has a stacked structure of a semiconductor substrate 320, an insulating layer 330, and an SOI layer (semiconductor layer) 340. In a predetermined region of the SOI layer 340, a trench element isolation region 342 is formed.

  The conductivity type of the semiconductor substrate 320 is N type. An impurity diffusion layer (contact region) 322 is formed in the semiconductor substrate 320. The impurity diffusion layer 322 has a function of flowing charge to the semiconductor substrate 320. The impurity diffusion layer 322 is P-type. That is, the impurity diffusion layer 322 and the semiconductor substrate 320 form a PN junction diode.

  A connection hole 350 reaching the impurity diffusion layer 322 is formed in a predetermined region of the SOI substrate 310. A side wall 352 is formed on the side surface of the SOI substrate 310 in the connection hole 350. A contact layer 360 is formed in the connection hole 350. The side wall 352 has a role of preventing the active element region and the contact layer 360 from being short-circuited when the connection hole 350 is formed in the active element region. A wiring layer 362 having a predetermined pattern is formed on the SOI layer 340 and the contact layer 360.

  Hereinafter, functions and effects of the semiconductor device according to the third embodiment will be described.

  In this embodiment mode, an impurity diffusion layer 322 that is electrically connected to the wiring layer 362 is formed in the semiconductor substrate 320. The impurity diffusion layer 322 and the semiconductor substrate 320 constitute a PN junction diode. Therefore, current can be released to the semiconductor substrate 420 via the PN junction diode. For this reason, the impurity diffusion layer 322 can function as an electrostatic protection region.

(Method for manufacturing semiconductor device)
A method for manufacturing a semiconductor device according to the third embodiment will be described below. 9 and 10 are cross-sectional views schematically showing the manufacturing process of the semiconductor device according to the embodiment.

  (A) First, an SOI substrate 310 having an N-type semiconductor substrate is prepared. Next, as shown in FIG. 9, a first resist layer R <b> 1 is formed on the SOI layer 340. The first resist layer R1 is opened above the region where the impurity diffusion layer 322 is to be formed.

  Next, P-type impurities 322a are ion-implanted into the semiconductor substrate 320 using the first resist layer R1 as a mask. As a result, a P-type impurity diffusion layer 322 is formed in the semiconductor substrate 320. Further, by forming the P-type impurity diffusion layer 322, a PN junction diode is formed at the boundary of the impurity diffusion layer 322. Next, the first resist layer R1 is removed.

  (B) Next, as shown in FIG. 10A, a trench element isolation region 342 is formed in a predetermined region of the SOI layer 340 by a known method.

  (C) Next, as shown in FIG. 10B, a second resist layer R2 is formed on the SOI layer 340. The second resist layer R <b> 2 is opened above the region where the connection hole 350 is to be formed reaching the impurity diffusion layer 322.

  Next, using the second resist layer R2 as a mask, the SOI layer 340, the insulating layer 330, and the semiconductor substrate 320 are etched to form connection holes 350. This etching can be performed, for example, by reactive ion etching. Next, the second resist layer R2 is removed.

  (D) Next, as shown in FIG. 8, a side wall 352 is formed on the side surface of the SOI substrate 310 in the connection hole 350. The side wall 352 can be formed in the same manner as in the first embodiment, for example.

  Next, the contact layer 360 is formed in the connection hole 350. Contact layer 360 can be formed, for example, in the same manner as in the first embodiment. If necessary, a wetting layer or a barrier layer may be formed in the connection hole 250 before forming the conductive layer. Next, a wiring layer 362 having a predetermined pattern is formed on the SOI layer 340. Thus, the semiconductor device 300 according to the third embodiment is formed.

  Hereinafter, a method for manufacturing the semiconductor device according to the present embodiment will be described.

  (A) The present embodiment includes a step of forming an impurity diffusion layer 322 constituting a PN junction diode with the semiconductor substrate 320 in the semiconductor substrate 320. For this reason, the charge generated in the ion implantation process or the etching process can be released to the semiconductor substrate 320 through the PN junction diode during the manufacturing process. As a result, the semiconductor element can be prevented from being destroyed by the charge.

(Modification)
In the third embodiment, for example, the following changes are possible.

  (1) In the third embodiment, the impurity diffusion layer 322 is P-type and the semiconductor substrate 320 is N-type. However, the present invention is not limited to this, and the impurity diffusion layer 322 can be N-type and the semiconductor substrate 320 can be P-type. In this case, charged electrons can be released to the semiconductor substrate 320 through the impurity diffusion layer 322.

  (2) In the above embodiment, the impurity diffusion layer 322 is connected to the wiring layer 362 formed on the SOI layer 340. However, the present invention is not limited to this, and the impurity diffusion layer 322 may be connected to a conductive layer formed in the SOI layer 340.

  The present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the present invention.

1 is a cross-sectional view schematically showing a semiconductor device according to a first embodiment. It is sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a top view which shows typically the example of application of the impurity diffusion layer which functions as a wiring layer. It is sectional drawing which shows typically the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows typically the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows typically the manufacturing process of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing which shows typically the semiconductor device which has the SOI substrate which concerns on a prior art example. It is sectional drawing which shows typically the modification concerning 1st Embodiment.

Explanation of symbols

100, 200, 300 Semiconductor device, 110, 210, 310 SOI substrate, 120, 220, 320 Semiconductor substrate, 122, 322 Impurity diffusion layer, 122a, 322a Impurity, 130, 230, 330 Insulating layer, 140, 240, 340 SOI Layer, 142, 242, 342 trench element isolation region, 144 active element region, 150, 250, 350 connection hole, 152, 252, 352 side wall, 160, 360 contact layer, 162, 362 wiring layer, 170 first transistor 172 gate electrode, 180 second transistor, 182 gate electrode, 222 first impurity diffusion layer, 222a impurity, 244 second impurity diffusion layer, 244a impurity, 260 first contact layer, 262 first wiring layer 270 capacitive element, 80 interlayer insulating layer, 282 through hole, 290 a second contact layer, 292 second wiring layer

Claims (31)

A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A semiconductor device including a semiconductor layer provided on the insulating layer,
In the semiconductor substrate, a first conductive layer is provided,
The semiconductor device, wherein the first conductive layer is electrically connected to a second conductive layer provided on or in the semiconductor layer. In claim 1,
The semiconductor device, wherein the first conductive layer includes an impurity diffusion layer. In claim 1 or 2,
The semiconductor device in which the first conductive layer functions as a wiring layer. In claim 1 or 2,
The semiconductor device, wherein the first conductive layer functions as a resistance layer. In any one of Claims 1-4,
A connection hole is provided for connecting the first conductive layer and the second conductive layer;
A semiconductor device in which a contact layer is provided in the connection hole. In any one of Claims 1-5,
A semiconductor device in which a side wall is provided in the connection hole. A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A semiconductor device including a semiconductor layer provided on the insulating layer,
In the semiconductor substrate, a contact region is provided,
The contact region is electrically connected to a conductive layer provided on or in the semiconductor layer, and has a function of flowing charges to the semiconductor substrate. In claim 7,
The contact region is a semiconductor device comprising an impurity diffusion layer. In claim 7 or 8,
A semiconductor device in which a PN junction is formed by the contact region and the semiconductor substrate. In claim 9,
The semiconductor substrate is N-type,
The contact region is a P-type semiconductor device. In claim 9,
The semiconductor substrate is P-type,
The contact region is an N-type semiconductor device. In any one of Claims 7-11,
A connection hole for connecting the contact region and the conductive layer is provided,
A semiconductor device in which a contact layer is provided in the connection hole. In claim 12,
A semiconductor device in which a side wall is provided in the connection hole. A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A semiconductor device including a semiconductor layer provided on the insulating layer,
In the semiconductor substrate, a first electrode is provided,
In the semiconductor layer, a second electrode is provided,
A semiconductor device in which a capacitor element is configured by the first electrode, the second electrode, and the insulating layer. In claim 14,
The semiconductor device, wherein the first electrode is constituted by a first impurity diffusion layer. In claim 14 or 15,
The semiconductor device, wherein the second electrode is constituted by a second impurity diffusion layer. In any one of Claims 14-16,
The semiconductor device, wherein the first electrode is electrically connected to a conductive layer provided on or in the semiconductor layer. In claim 17,
A connection hole is provided for connecting the first electrode and the conductive layer;
A semiconductor device in which a contact layer is provided in the connection hole. In claim 18,
A semiconductor device in which a side wall is provided in the connection hole. A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: a semiconductor layer provided on the insulating layer;
A step of ion-implanting impurities into a predetermined region of the semiconductor substrate to form a first conductive layer composed of an impurity diffusion layer; and a second layer provided on or in the semiconductor layer A method for manufacturing a semiconductor device, comprising: electrically connecting a conductive layer and the first conductive layer. In claim 20,
The method for manufacturing a semiconductor device, wherein the first conductive layer functions as a wiring layer. In claim 20,
The method for manufacturing a semiconductor device, wherein the first conductive layer functions as a resistance layer. In any one of Claims 20-22,
And a step of forming a connection hole for electrically connecting the first conductive layer and the second conductive layer, and a step of forming a contact layer in the connection hole. Device manufacturing method. In claim 23,
Furthermore, the manufacturing method of a semiconductor device including the process of forming a side wall in the said connection hole. A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A method of manufacturing a semiconductor device comprising: a semiconductor layer provided on the insulating layer;
In the semiconductor substrate, a contact region is provided,
The contact region is electrically connected to a conductive layer provided on or in the semiconductor layer, and has a function of flowing charge to the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: implanting impurities into the semiconductor substrate to form the contact region; and electrically connecting the conductive layer and the contact region. In claim 25,
And a step of forming a connection hole for electrically connecting the contact region and the conductive layer provided in the semiconductor layer, and a step of forming a contact layer in the connection hole. Device manufacturing method. In claim 26,
Furthermore, the manufacturing method of a semiconductor device including the process of forming a side wall in the said connection hole. A semiconductor substrate;
An insulating layer provided on the semiconductor substrate;
A method of manufacturing a semiconductor device comprising: a semiconductor layer provided on the insulating layer;
Including a step (a) of forming a capacitive element;
The capacitor element includes a first electrode provided on the semiconductor substrate, the insulating layer, and a second electrode provided on the semiconductor layer. The step (a) includes impurities in the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: (a-1) a step of forming a first electrode composed of the first impurity diffusion layer by ion implantation of a first impurity diffusion layer. In claim 28,
The step (a) further includes a step (a-2) of forming the second electrode composed of the second impurity diffusion layer by ion-implanting impurities into the semiconductor layer. Production method. In claim 28 or 29,
The semiconductor device has a conductive layer provided on or in the semiconductor layer,
A method for manufacturing a semiconductor device, comprising: forming a connection hole for electrically connecting the first electrode and the conductive layer; and forming a contact layer in the connection hole. In claim 30,
Furthermore, the manufacturing method of a semiconductor device including the process of forming a side wall in the said connection hole.

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