JP2008177523A - Method for manufacturing group iii nitride compound semiconductor light-emitting element, the group iii nitride compound semiconductor light-emitting element and lamp - Google Patents

Method for manufacturing group iii nitride compound semiconductor light-emitting element, the group iii nitride compound semiconductor light-emitting element and lamp Download PDF

Info

Publication number
JP2008177523A
JP2008177523A JP2007211377A JP2007211377A JP2008177523A JP 2008177523 A JP2008177523 A JP 2008177523A JP 2007211377 A JP2007211377 A JP 2007211377A JP 2007211377 A JP2007211377 A JP 2007211377A JP 2008177523 A JP2008177523 A JP 2008177523A
Authority
JP
Japan
Prior art keywords
group iii
iii nitride
compound semiconductor
nitride compound
semiconductor light
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007211377A
Other languages
Japanese (ja)
Inventor
Hisayuki Miki
Taisuke Yokoyama
久幸 三木
泰典 横山
Original Assignee
Showa Denko Kk
昭和電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP2006343019 priority Critical
Application filed by Showa Denko Kk, 昭和電工株式会社 filed Critical Showa Denko Kk
Priority to JP2007211377A priority patent/JP2008177523A/en
Publication of JP2008177523A publication Critical patent/JP2008177523A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/0242Crystalline insulating materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02455Group 13/15 materials
    • H01L21/02458Nitrides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02494Structure
    • H01L21/02496Layer structure
    • H01L21/02502Layer structure consisting of two layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02631Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/30Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a group III nitride compound semiconductor light-emitting element for producing an element that has superior light emission characteristics, while exhibiting superior productivity, and to provide the group III nitride compound semiconductor light-emitting element and a lamp. <P>SOLUTION: An intermediate layer 12 comprising a group III nitride compound is formed on a substrate 11, by activating a metal material and gas containing a group V element by plasma and causing reaction, and an n-type semiconductor layer 14 comprising a group III nitride compound semiconductor, a light-emitting layer 15, and a p-type semiconductor layer 16 are sequentially laminated on the intermediate layer 12; and in this manufacturing method, the group V element is nitride and the molar fraction of nitrogen gas in the gas is set to be in a range of 20-99%, when the intermediate layer 12 is formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a group III nitride compound semiconductor light-emitting device, a group III nitride compound semiconductor light-emitting device, and a lamp that are suitably used for light-emitting diodes (LEDs), laser diodes (LD), electronic devices, and the like. .

Group III nitride semiconductor light-emitting devices have a direct transition type band gap of energy corresponding to the range from visible light to ultraviolet light, and are excellent in luminous efficiency, and are therefore used as light-emitting devices such as LEDs and LDs. It has been.
Even when used in an electronic device, the group III nitride semiconductor can provide an electronic device having superior characteristics as compared to the case of using a conventional group III-V compound semiconductor.

Conventionally, as a group III nitride semiconductor single crystal wafer, a method in which crystals are grown on single crystal wafers of different materials is generally used. There is a large lattice mismatch between such a heterogeneous substrate and a group III nitride semiconductor crystal epitaxially grown thereon. For example, when gallium nitride (GaN) is grown on a sapphire (Al 2 O 3 ) substrate, there is a 16% lattice mismatch between the two, and when gallium nitride is grown on a SiC substrate. There is a 6% lattice mismatch between the two.
In general, when there is a large lattice mismatch as described above, it is difficult to epitaxially grow a crystal directly on a substrate, and a crystal with good crystallinity cannot be obtained even when grown. There is.

  Therefore, when a group III nitride semiconductor crystal is epitaxially grown on a sapphire single crystal substrate or SiC single crystal substrate by metal organic chemical vapor deposition (MOCVD), first, aluminum nitride (AlN) or A method of laminating a layer called a low temperature buffer layer made of aluminum gallium nitride (AlGaN) and epitaxially growing a group III nitride semiconductor crystal on the layer at a high temperature has been proposed (for example, Patent Document 1). 2).

  A technique for forming the buffer layer by a method other than MOCVD has also been proposed. For example, a buffer layer is formed on a substrate by sputtering, and sapphire, silicon, silicon carbide, zinc oxide, gallium phosphide, gallium arsenide, magnesium oxide, manganese oxide, and group III nitride are used as substrate materials. A method using a system compound semiconductor single crystal or the like has been proposed, and among these, a sapphire a-plane substrate is suitable (for example, Patent Documents 3 and 4).

  However, the methods described in Patent Documents 1 to 4 have a problem that a sufficiently crystalline Group III nitride compound semiconductor cannot be obtained.

  On the other hand, a method has been proposed in which crystals having the same composition are grown by MOCVD on a buffer layer formed by sputtering using high frequency (for example, Patent Document 5). However, the method described in Patent Document 5 has a problem that a good crystal cannot be stably stacked on the substrate.

In addition, when a buffer layer is formed on a substrate by sputtering, a method has been proposed in which the initial voltage of the sputtering apparatus is 110% or less of the sputtering voltage (for example, Patent Document 6). In the method described in Patent Document 6, an expensive material used in the MOCVD method is not used, and the buffer layer is formed by a sputtering method.
Japanese Patent No. 3026087 Japanese Patent Laid-Open No. 4-297003 Japanese Patent No. 3440873 Japanese Patent No. 3700492 Japanese Patent Publication No. 5-86646 JP 2001-308010 A

  The method described in Patent Document 3 is to anneal in a mixed gas composed of ammonia and hydrogen after the growth of the buffer layer, and the method described in Patent Document 4 is a method in which the buffer layer is heated to 400 ° C. or higher. It is considered important to form a film by DC sputtering at a temperature. However, as a result of diligent experiments conducted by the present inventors, it has become clear that a favorable group III nitride compound semiconductor cannot be obtained under the conditions described in Patent Documents 3 and 4.

Here, the MOCVD method described in Patent Documents 1 and 2 is a method in which the source gas is decomposed at a temperature equal to or higher than the decomposition temperature of the source gas, and a decomposition product thereby is grown on the template, and the growth rate is increased. Although it is low, it is known as a method for obtaining a film with high crystallinity.
On the other hand, the sputtering method is a method in which atoms are struck out from a target and the struck atoms are forcibly formed on a substrate. Although the growth rate is high, the obtained film is a crystal compared to the MOCVD method. It is thought that the nature is not high. For this reason, conventionally, after the buffer layer is formed on the substrate by MOCVD, an undoped GaN layer is grown on the substrate by several μm, thereby increasing the crystallinity of the light emitting layer grown thereon. Was used.

  However, in the method of forming the buffer layer by the MOCVD method as described above, sufficient crystallinity cannot be obtained, and a method capable of obtaining a film having good crystallinity has been desired.

  The present invention has been made in view of the above problems, and a group III nitride semiconductor excellent in uniformity can be grown on a substrate in a short time, has excellent productivity, and has excellent light emitting characteristics. It is an object of the present invention to provide a method for producing a group III nitride compound semiconductor light emitting device, a group III nitride compound semiconductor light emitting device, and a lamp from which the above device is obtained.

As a result of intensive investigations to solve the above problems, the inventors of the present invention have a very high deposition rate compared to the MOCVD method, and the raw material is produced by plasma, such as a sputtering method for forcibly forming a film on a substrate. An intermediate layer (buffer layer) is formed by using an activation method, and the substrate is formed as an alignment film having specific anisotropy by setting the partial pressure of a nitrogen raw material that is a group V element to an appropriate range. It was found that the film can be formed on top and that the film formation rate can be improved to prevent impurities such as in-furnace deposits from entering the film, thus completing the present invention.
That is, the present invention relates to the following.

[1] An intermediate layer made of a group III nitride compound is formed on a substrate by activating and reacting a gas containing a group V element and a metal material with plasma, and a group III nitride is formed on the intermediate layer. A method of manufacturing a group III nitride compound semiconductor light emitting device in which an n-type semiconductor layer made of a compound compound semiconductor, a light emitting layer, and a p type semiconductor layer are sequentially laminated, wherein the group V element is nitrogen and the intermediate layer is formed. A method for producing a Group III nitride compound semiconductor light-emitting device, wherein the gas fraction of nitrogen in the gas is in the range of more than 20% and 99% or less during film formation.
[2] The group III nitride compound semiconductor according to [1], wherein a gas fraction of nitrogen in the gas when forming the intermediate layer is in a range of more than 20% and 60% or less. Manufacturing method of light emitting element.
[3] The group III nitride compound semiconductor according to [1], wherein a gas fraction of nitrogen in the gas when forming the intermediate layer is in a range of more than 20% and 50% or less. Manufacturing method of light emitting element.

[4] The method for producing a Group III nitride compound semiconductor light-emitting device according to any one of [1] to [3], wherein the intermediate layer is formed by sputtering.
[5] The method for producing a Group III nitride compound semiconductor light-emitting device according to [4], wherein the intermediate layer is formed by RF sputtering.
[6] The method for producing a group III nitride compound semiconductor light-emitting device according to [5], wherein the intermediate layer is formed using an RF sputtering method while moving a cathode magnet.
[7] The group III nitride according to any one of [4] to [6], wherein the intermediate layer is formed by a reactive sputtering method in which a gas containing a group V element is circulated in the reactor. A method for producing a compound semiconductor light emitting device.
[8] The method for producing a group III nitride compound semiconductor light-emitting device according to any one of [1] to [7], wherein the metal material is a material containing Al.
[9] The method for producing a Group III nitride compound semiconductor light-emitting device according to any one of [1] to [8], wherein the intermediate layer is formed of AlN.
[10] The group III nitride compound semiconductor light-emitting device according to any one of [1] to [9], wherein the intermediate layer is formed at a temperature of the substrate in a range of room temperature to 1000 ° C. Method.
[11] The group III nitride compound semiconductor light-emitting device according to any one of [1] to [9], wherein the intermediate layer is formed at a temperature of the substrate in a range of 200 to 800 ° C. Method.

[12] The group III nitride compound semiconductor light-emitting device according to any one of [1] to [11], wherein a base layer provided in the n-type semiconductor layer is stacked on the intermediate layer. Method.
[13] The method for producing a Group III nitride compound semiconductor light-emitting device according to [12], wherein the underlayer is formed of a GaN-based compound semiconductor.
[14] The method for producing a group III nitride compound semiconductor light-emitting device according to [13], wherein the underlayer is formed of GaN.
[15] The method for producing a group III nitride compound semiconductor light-emitting device according to [13], wherein the underlayer is formed of AlGaN.
[16] The group III nitride compound semiconductor light-emitting device according to any one of [12] to [15], wherein the intermediate layer and the base layer are formed of different group III nitride compounds, respectively. Method.
[17] The method for producing a group III nitride compound semiconductor light-emitting device according to any one of [12] to [16], wherein the underlayer is formed on the intermediate layer by MOCVD.
[18] The group III nitride compound semiconductor light-emitting device according to any one of [12] to [17], wherein the temperature of the substrate when forming the base layer is 800 ° C. or higher. Method.
[19] A group III nitride compound semiconductor light-emitting device obtained by the production method according to any one of [1] to [18].

[20] An intermediate layer made of a group III nitride compound is formed on a substrate by reacting a gas containing a group V element and a metal material by being activated by plasma, and a group III nitride is formed on the intermediate layer. A group III nitride compound semiconductor light-emitting device in which an n-type semiconductor layer made of a nitride compound semiconductor, a light-emitting layer, and a p-type semiconductor layer are sequentially stacked, wherein the intermediate layer has nitrogen as the group V element And a group III nitride compound semiconductor light-emitting device, wherein the nitrogen gas fraction in the gas is in a range of more than 20% and 99% or less.
[21] The intermediate layer is formed such that the group V element is nitrogen and the gas fraction of nitrogen in the gas is in the range of more than 20% and not more than 60%. The group III nitride compound semiconductor light-emitting device according to [20].
[22] The intermediate layer is formed in such a manner that the group V element is nitrogen and the nitrogen gas fraction in the gas is in the range of more than 20% and 50% or less. The group III nitride compound semiconductor light-emitting device according to [20].

[23] The group III nitride compound semiconductor light-emitting device according to any one of [20] to [22], wherein the intermediate layer has a composition containing Al.
[24] The group III nitride compound semiconductor light-emitting device according to [23], wherein the intermediate layer is made of AlN.
[25] The group III nitride compound semiconductor light-emitting device according to any one of [20] to [24], wherein the intermediate layer covers at least 90% of the substrate surface .
[26] The group III nitride compound semiconductor light-emitting device according to any one of [20] to [25], wherein the intermediate layer is formed so as to cover at least a side surface of the substrate.
[27] The group III nitride compound semiconductor light-emitting device according to any one of [20] to [26], wherein the intermediate layer is formed so as to cover a side surface and a back surface of the substrate.
[28] The group III nitride compound semiconductor light-emitting device according to any one of [20] to [27], wherein the intermediate layer is made of an aggregate of columnar crystals.
[29] The group III nitride compound semiconductor light-emitting device according to [28], wherein the intermediate layer has an average grain width of 1 to 100 nm in each of the columnar crystals. .
[30] The group III nitride compound semiconductor light-emitting device according to [28], wherein the intermediate layer has an average grain width of the columnar crystals in the range of 2 to 70 nm. .
[31] The group III nitride compound semiconductor light-emitting element according to [28] to [30], wherein the intermediate layer is formed as a hexagonal close-packed structure.
[32] The group III nitride compound semiconductor light-emitting device according to any one of [20] to [31], wherein the thickness of the intermediate layer is in the range of 20 to 80 nm.

[33] The group III nitride compound semiconductor light-emitting device according to any one of [20] to [32], wherein a base layer provided in the n-type semiconductor layer is laminated on the intermediate layer. .
[34] The group III nitride compound semiconductor light-emitting element according to [33], wherein the underlayer is made of a GaN-based compound semiconductor.
[35] The group III nitride compound semiconductor light-emitting device according to [34], wherein the underlayer is made of GaN.
[36] The group III nitride compound semiconductor light-emitting element according to [34], wherein the underlayer is made of AlGaN.
[37] A lamp comprising the group III nitride compound semiconductor light-emitting device according to any one of [19] to [36].

According to the method for producing a Group III nitride compound semiconductor light emitting device of the present invention, with the above-described configuration, an intermediate layer is formed on the substrate by a method of activating the raw material with plasma, By defining the partial pressure within an appropriate range, it is possible to form an intermediate layer on which good uniformity and good crystalline group III nitride compound semiconductor can be formed by MOCVD.
Accordingly, an intermediate layer made of a group III nitride compound having good crystallinity and a semiconductor layer made of a group III nitride semiconductor can be efficiently grown on the substrate, and the productivity is excellent and the price is low. A group III nitride compound semiconductor light emitting device having light emitting characteristics is obtained.

  Hereinafter, an embodiment of a group III nitride compound semiconductor light emitting device, a group III nitride compound semiconductor light emitting device, and a lamp according to an embodiment of the present invention will be described with reference to FIGS.

  In the method of manufacturing a group III nitride compound semiconductor light emitting device (hereinafter sometimes abbreviated as a light emitting device) of this embodiment, a gas containing a group V element and a metal material are activated on a substrate 11 by plasma. By reacting, an intermediate layer 12 made of a group III nitride compound is formed, and an n-type semiconductor layer 14, a light emitting layer 15, and a p-type semiconductor layer 16 made of a group III nitride compound semiconductor are formed on the intermediate layer 12. In which the V group element is nitrogen and the intermediate layer 12 is formed with a nitrogen gas fraction in the range of more than 20% and 99% or less. is there.

  In the manufacturing method of the present embodiment, when a group III nitride compound semiconductor crystal is epitaxially grown on the substrate 11, for example, a sputtering method or the like is used to form a raw material activated and reacted with plasma on the substrate 11. This is a method of forming the intermediate layer 12, and by forming the intermediate layer 12 with the nitrogen gas fraction in the gas within the above range, the intermediate layer 12 having good crystallinity has a specific anisotropy. The alignment film can be formed on the substrate 11 in a short time. Thereby, a group III nitride semiconductor with good crystallinity can be efficiently grown on the intermediate layer 12.

  A stacked structure of light-emitting elements obtained by the manufacturing method of this embodiment will be described using the stacked semiconductor 10 shown in FIG. In this laminated semiconductor 10, an intermediate layer 12 made of a group III nitride compound is formed on a substrate 11 by activating and reacting a metal material and a gas containing a group V element with plasma. On the layer 12, an n-type semiconductor layer 14 made of a group III nitride compound semiconductor, a light-emitting layer 15, and a p-type semiconductor layer 16 are sequentially laminated to have a schematic configuration.

Further, the laminated semiconductor 10 illustrated in FIG. 1 has a configuration in which an underlayer 14a made of a group III nitride compound semiconductor is laminated on an intermediate layer 12, and the intermediate layer 12 and the underlayer are formed on the substrate 11. 14a, an n-type semiconductor layer 14 composed of an n-type contact layer 14b and an n-type cladding layer 14c, a light emitting layer 15 in which barrier layers 15a and well layers 15b are alternately stacked, a p-type cladding layer 16a and a p-type contact layer 16b A p-type semiconductor layer 16 is sequentially stacked.
In the laminated semiconductor 10 according to the present embodiment, a translucent positive electrode 17 is laminated on a p-type semiconductor layer 16 and a positive electrode bonding pad 18 is formed thereon, as in the example shown in FIGS. In addition, the light-emitting element 1 in which the negative electrode 19 is stacked on the exposed region 14d formed in the n-type contact layer 14b of the n-type semiconductor layer 14 can be configured.
Hereinafter, the manufacturing method of the light emitting element of this embodiment and the light emitting element will be described in detail.

[substrate]
In the present embodiment, the substrate 11 on which the group III nitride compound semiconductor crystal is epitaxially grown on the surface is not particularly limited, and various materials can be selected and used. For example, sapphire, SiC, silicon, zinc oxide , Magnesium oxide, manganese oxide, zirconium oxide, manganese zinc iron oxide, magnesium aluminum oxide, zirconium boride, gallium oxide, indium oxide, lithium gallium oxide, lithium aluminum oxide, neodymium gallium oxide, lanthanum strontium aluminum tantalum, strontium titanium oxide , Titanium oxide, hafnium, tungsten, molybdenum and the like.

  In addition, while forming an intermediate | middle layer without using ammonia, the base layer mentioned later is formed into a film by the method of using ammonia, and also it is chemical by contacting ammonia at high temperature among the above-mentioned substrate materials. When an oxide substrate or a metal substrate that is known to cause modification is used, the intermediate layer of this embodiment acts as a coating layer, which is effective in preventing chemical alteration of the substrate. is there.

[Middle layer]
In the laminated semiconductor 10 of the present embodiment, an intermediate layer 12 made of a group III nitride compound is formed on a substrate 11 by reacting a metal raw material and a gas containing a group V element by being activated by plasma. Has been. A film formed by a method using a plasma metal raw material as in this embodiment has an effect that alignment is easily obtained.

  A group III nitride compound semiconductor device such as an LED or LD needs to have a current flowing in a certain fixed direction. For this reason, the group III nitride compound semiconductor element is required to have good crystallinity and orientation. Since the group III nitride compound semiconductor element is epitaxially grown on the intermediate layer 12, the intermediate layer 12 also needs to have good crystallinity and orientation.

The MOCVD method is a method of decomposing organometallic molecules and laminating metal elements. Therefore, a substrate serving as a template is required to orient the film. For this reason, in the case where the intermediate layer 12 is a low-temperature buffer layer grown on the substrate 11, the substrate is the base, so that the substrates that can be used are limited.
On the other hand, in the case of the reactive sputtering method, the charged particles struck into the plasma do not necessarily exist in an atomic state, but also exist as charged particles having a bond such as a dimer. Such charged particles serve as a raw material for forming the film. Further, since such charged particles have a moment, the charged particles are affected by the electric field due to sputtering and are deposited on the substrate 11 with specific anisotropy. Because of this anisotropy, the film exhibits an alignment structure, so that the alignment film can be formed by sputtering regardless of the type of substrate used.

The intermediate layer 12 needs to cover at least 60% or more, preferably 80% or more, of the surface 11a of the substrate 11, and is formed so as to cover 90% or more as a coat layer of the substrate 11. It is preferable from a functional aspect. The intermediate layer 12 is most preferably formed so as to cover 100% of the surface 11a, that is, the surface 11a of the substrate 11 without a gap.
When the region in which the intermediate layer 12 covers the surface 11a of the substrate 11 is reduced, the substrate 11 is exposed greatly, so that it does not function as a coat layer, and a reaction occurs between the semiconductor raw material for growing the group III nitride semiconductor crystal and the substrate. As a result, the flatness of the n-type semiconductor layer formed on the intermediate layer 12 may be impaired.

In addition, when forming an intermediate | middle layer on the board | substrate 11, you may form so that only the surface 11a of the board | substrate 11 may be covered, You may form so that the surface 11a and the side surface of the board | substrate 11 may be covered. In addition, it is most preferable to form the substrate 11 so as to cover the front surface 11a, the side surface, and the back surface from the functional surface as a coat layer.
In the MOCVD method, since the source gas may circulate to the side surface or back surface of the substrate, when forming any of the layers made of a group III nitride compound semiconductor crystal described later by the MOCVD method, In order to avoid reaction with the substrate, it is preferable to form an intermediate layer so that the side surface or back surface of the substrate can be protected.

  The crystal of the group III nitride compound forming such an intermediate layer has a hexagonal crystal structure and can be formed into a columnar crystal having a texture based on a hexagonal column by controlling the film forming conditions. it can. Note that the columnar crystal described here is a crystal which is separated by forming a crystal grain boundary between adjacent crystal grains, and is itself a columnar shape as a longitudinal sectional shape.

  The intermediate layer 12 preferably has a columnar crystal structure as described above from the viewpoint of the buffer function. As described above, the group III nitride compound crystal has a hexagonal crystal and forms a structure based on a hexagonal column. When the intermediate layer 12 having such a columnar crystal structure is formed on the substrate 11, the buffer function of the intermediate layer 12 works effectively, so that the group III nitride semiconductor layer formed thereon is A crystal film having good orientation and crystallinity is obtained.

In addition, the intermediate layer 12 preferably has an average width of each grain of the columnar crystal in the range of 1 to 100 nm in terms of the function as the buffer layer, and is in the range of 2 to 70 nm. Is more preferable.
In order to improve the crystallinity of the intermediate layer 12 made of columnar crystals, it is necessary to appropriately control the grain width of each crystal of the columnar crystals, and specifically, it is preferably within the above range. Such a crystal grain width can be easily measured by cross-sectional TEM observation or the like.
In addition, the intermediate layer 12 desirably has the crystal grains in a substantially columnar shape as described above, and desirably forms a layer by collecting the columnar grains.
Further, when the intermediate layer is formed as an aggregate of columnar crystals, it is more preferable to use a layer having a hexagonal close-packed structure.
Here, the grain width described in the present invention means the distance between crystal interfaces when the intermediate layer is an aggregate of columnar grains. On the other hand, when the grains are scattered in the form of islands, the grain width means the length of the forehead that is the largest of the surfaces where the crystal grains are in contact with the substrate surface.

The thickness of the intermediate layer 12 is preferably in the range of 20 to 80 nm. By setting the thickness of the intermediate layer 12 within this range, the intermediate layer 12 having good crystallinity can be formed on the substrate 11 as an alignment film having specific anisotropy in a short time. .
If the thickness of the intermediate layer 12 is less than 20 nm, a film having good crystallinity may not be obtained as an alignment film having specific anisotropy, and the function as a coat layer as described above may be obtained. Not enough.
In addition, when the intermediate layer 12 is formed with a film thickness exceeding 80 nm, a film having good crystallinity may not be obtained as an alignment film having specific anisotropy, and the function as a coating layer may be obtained. In spite of no change, there is a possibility that the film formation processing time becomes long and the productivity is lowered.

The intermediate layer 12 preferably has a composition containing Al, and particularly preferably has a configuration made of AlN.
As the material constituting the intermediate layer 12, any material can be used as long as it is a group III nitride compound semiconductor represented by the general formula AlGaInN. Furthermore, as V group, it is good also as a structure containing As and P.
When the intermediate layer 12 has a composition containing Al, it is preferable to use GaAlN. In this case, the composition of Al is preferably 50% or more.
Further, the intermediate layer 12 is more preferably made of AlN because it can efficiently form a columnar crystal aggregate.

Below, the film-forming method of the intermediate | middle layer 12 is demonstrated.
As a method of forming the intermediate layer 12 made of a group III nitride compound by activating and reacting a group III metal raw material and a gas containing a group V element with plasma, a sputtering method, a PLD method, and a PED method are used. And CVD method.
As a method of generating plasma, a sputtering method that discharges by applying a high voltage at a specific degree of vacuum, a PLD method that generates a plasma by irradiating a laser with a high energy density, or a plasma that is generated by irradiating an electron beam. There are several methods such as the PED method. Among these, the sputtering method is the most convenient and suitable for mass production, and is therefore a preferred method. It is known that nitrogen is adsorbed on the surface of a target (metal material) when performing film formation using nitrogen gas as a group V element by sputtering (Mat. Res. Soc. Symp. Proc. Vol. .68, 357, 1986).
In general, when sputtering is performed using a metal target, DC sputtering is preferable in terms of film formation efficiency, but nitrogen adheres to the target, leading to charge-up of the target surface and stable film formation speed. Therefore, it is desirable to use pulse DC sputtering or RF sputtering.

  In the sputtering method, a technique for improving efficiency by confining plasma in a magnetic field is generally used. As a method for using the target without bias, the position of the cathode magnet is moved within the target. It is preferable to use an RF sputtering method for film formation. A specific magnet movement method can be appropriately selected depending on the sputtering apparatus. For example, the magnet can be swung or rotationally moved.

  In the RF sputtering apparatus 40 of the example shown in FIG. 5, a magnet 42 is disposed below the metal target 47 (downward in FIG. 5), and the magnet 42 swings below the metal target 47 by a drive device (not shown). Nitrogen gas and argon gas are supplied to the chamber 41, and an intermediate layer is formed on the substrate 11 attached to the heater 44. At this time, since the magnet 42 is oscillated below the metal target 47 as described above, the plasma confined in the chamber 41 moves, and unevenness is also caused on the side surface in addition to the surface 11 a of the substrate 11. The intermediate layer can be formed without any problem.

  When the intermediate layer 12 is formed by sputtering, the reactive sputtering method in which a gas containing nitrogen is circulated in the reactor is used to improve the crystallinity by controlling the reaction. It is more preferable in that it can be maintained and its good crystallinity can be stably reproduced.

  When the intermediate layer 12 is formed by sputtering, particularly reactive sputtering, important parameters other than the temperature of the substrate 11 include nitrogen partial pressure, furnace pressure, and the like.

The nitrogen gas fraction in the gas containing nitrogen, that is, the ratio of the nitrogen flow rate to the flow rate of nitrogen (N 2 ) and Ar is preferably greater than 20%. When nitrogen is 20% or less, the amount of nitrogen present is small and metal is deposited on the substrate 11, so that the intermediate layer 12 does not have the crystal structure required for the group III nitride compound. Further, if the flow rate ratio of nitrogen exceeds 99%, the amount of Ar is too small and the sputtering rate is greatly reduced, which is not preferable. Further, the nitrogen gas fraction in the gas containing nitrogen is more preferably in the range of more than 20% and not more than 60%, and most preferably in the range of more than 20% and not more than 50%.

In the present embodiment, by supplying active nitrogen reactive species on the substrate 11 at a high concentration, migration on the substrate 11 can be suppressed, thereby suppressing self-organization and making the intermediate layer 12 appropriate. A columnar crystal structure can be obtained.
Further, in the intermediate layer 12, by appropriately controlling the density of the crystal interface of the columnar crystals, the crystallinity of the semiconductor layer made of GaN stacked thereon can be favorably controlled.

  Moreover, it is preferable that the pressure in the furnace when forming the intermediate layer 12 using the sputtering method is 0.2 Pa or more. When the pressure in the furnace is less than 0.2 Pa, the kinetic energy of the generated reactive species becomes too large, and the film quality of the formed intermediate layer becomes insufficient. In addition, the upper limit of the pressure in the furnace is not particularly limited, but if the pressure is 0.8 Pa or more, the dimer charged particles contributing to the film orientation will be subjected to the interaction of charged particles in the plasma. The internal pressure is preferably in the range of 0.2 to 0.8 Pa.

  The substrate 11 is preferably subjected to wet pretreatment. For example, for a substrate made of silicon, a conventionally known RCA cleaning method or the like is performed, and the surface of the substrate is hydrogen-terminated to form an intermediate layer on the substrate in a sputtering process, which will be described in detail later. The process is stable.

In addition, after introducing the substrate 11 into the reactor and before forming the intermediate layer 12, pretreatment can be performed using a method such as reverse sputtering. Specifically, the surface can be prepared by exposing the substrate 11 to Ar or N 2 plasma.
For example, by applying plasma such as Ar gas or N 2 gas to the surface of the substrate 11, organic substances and oxides attached to the surface of the substrate 11 can be removed. In this case, if a voltage is applied between the substrate 11 and the chamber, the plasma particles efficiently act on the substrate 11. By applying such pretreatment to the substrate 11, the intermediate layer 12 can be formed on the entire surface 11a of the substrate 11, and the crystallinity of the film formed thereon can be improved.

The pretreatment of the substrate 11 is preferably performed by plasma treatment performed in an atmosphere in which an ionic component and a radical component having no charge are mixed as described above.
Here, when removing contaminants such as organic substances and oxides from the surface of the substrate, for example, when an ionic component or the like is supplied to the substrate surface alone, the energy is too strong and the substrate surface is damaged, There is a problem that the quality of the crystal grown on the substrate is lowered.
In the present invention, the pretreatment of the substrate 11 is a method using plasma treatment performed in an atmosphere in which an ionic component and a radical component are mixed as described above, and reactive species having appropriate energy is applied to the substrate 11. By acting, it becomes possible to remove contamination and the like without damaging the surface of the substrate 11. As a mechanism for obtaining such an effect, damage to the substrate surface is suppressed by using plasma with a small proportion of ion components, and contamination can be effectively removed by causing plasma to act on the substrate surface. Etc. are considered.

  Further, the film formation rate when forming the intermediate layer 12 is preferably in the range of 0.01 nm / s to 10 nm / s. If the film formation rate is less than 0.01 nm / s, the film does not become a layer but grows in an island shape, which may prevent the surface of the substrate 11 from being covered. When the film formation rate exceeds 10 nm / s, the film does not become crystalline but becomes amorphous.

The temperature of the substrate 11 when forming the intermediate layer 12 is preferably in the range of room temperature to 1000 ° C, and more preferably in the range of 200 to 800 ° C. If the temperature of the substrate 11 is lower than the lower limit, the intermediate layer 12 cannot cover the entire surface of the substrate 11 and the surface of the substrate 11 may be exposed. When the temperature of the substrate 11 exceeds the above upper limit, the migration of the metal raw material becomes too active, and there is a possibility that the layer becomes unsuitable from the viewpoint of the function as a buffer layer.
In addition, although the room temperature demonstrated by this invention is a temperature influenced also by the environment of a process etc., as a specific temperature, it is the range of 0-30 degreeC.

  When a mixed crystal is formed as an intermediate layer using a film forming method in which a metal raw material is turned into a plasma, for example, a mixture of metal materials containing Al or the like (although it is not always necessary to form an alloy) May be used as a target, or two targets made of different materials may be prepared and simultaneously sputtered. For example, when a film having a constant composition is formed, a mixed material target is used, and when several kinds of films having different compositions are formed, a plurality of targets may be installed in the chamber.

As a gas containing nitrogen (group V element) used in the present embodiment, generally known nitrogen compounds can be used without any limitation, but ammonia and nitrogen (N 2 ) are easy to handle. In addition, it is preferable because it is relatively inexpensive and available.
Ammonia has good decomposition efficiency and can be deposited at a high growth rate. However, because of its high reactivity and toxicity, it requires a detoxification facility and a gas detector. It is necessary to make these materials chemically stable.
In addition, when nitrogen (N 2 ) is used as a raw material, a simple apparatus can be used, but a high reaction rate cannot be obtained. However, if the method of introducing nitrogen into the apparatus after decomposing nitrogen by an electric field, heat, etc. is possible, it is possible to obtain a film formation rate that is lower than that of ammonia but usable for industrial production. Considering the trade-off, it is the most suitable nitrogen source.

  Further, as described above, the intermediate layer 12 is preferably formed so as to cover the side surface of the substrate 11. Furthermore, the intermediate layer 12 is most preferably formed so as to cover the side surface and the back surface of the substrate 11. However, when the intermediate layer is formed by the conventional film forming method, it is necessary to perform the film forming process about 6 to 8 times at the maximum, which is a long time process. As another film forming method, a method of forming a film on the entire surface of the substrate by placing it in the chamber without holding the substrate can be considered, but the apparatus becomes complicated when it is necessary to heat the substrate. There is a fear.

  Thus, for example, a method of forming a film while changing the position of the substrate with respect to the sputtering direction of the film forming material by swinging or rotating the substrate is conceivable. By adopting such a method, it is possible to form a film on the front surface and side surfaces of the substrate in a single process, and then cover the entire surface of the substrate in a total of two processes by performing a film forming process on the back surface of the substrate. It becomes possible.

  Alternatively, a method may be employed in which the film formation material source is formed from a generation source having a large area, and the material generation position is moved to form a film over the entire surface of the substrate without moving the substrate. As such a method, as described above, there is an RF sputtering method in which film formation is performed while moving the position of the cathode magnet within the target by swinging or rotating the magnet. Further, when film formation is performed by such an RF sputtering method, both the substrate side and the cathode side may be moved. Furthermore, by arranging the cathode, which is a material generation source, in the vicinity of the substrate, the generated plasma is not supplied to the substrate in the form of a beam, but is supplied so as to wrap the substrate. Simultaneous film formation on the front and side surfaces is possible.

[Multilayer semiconductor]
As shown in FIG. 1, the laminated semiconductor 10 of this embodiment includes an n-type semiconductor layer 14 made of a nitride-based compound semiconductor, a light emitting layer 15, and a p on a substrate 11 through the intermediate layer 12 as described above. A semiconductor layer 20 made of a type semiconductor layer 16 is laminated.
The n-type semiconductor layer 14 has a base layer 14 a made of at least a group III nitride compound semiconductor, and the base layer 14 a is laminated on the intermediate layer 12.

On the base layer 14a made of a group III nitride compound semiconductor, as described above, a crystal stacked structure having functionality like the stacked semiconductor 10 shown in FIG. 1 can be formed. For example, when forming a semiconductor multilayer structure for a light-emitting element, an n-type conductive layer doped with an n-type dopant such as Si, Ge, or Sn, or a p-type conductive layer doped with a p-type dopant such as magnesium. A stacked semiconductor can be formed by stacking layers and the like. As a material, InGaN can be used for the light emitting layer and the like, and AlGaN can be used for the cladding layer and the like. Thus, by forming a group III nitride semiconductor crystal layer having further functions on the base layer 14a, it has a semiconductor laminated structure used for manufacturing a light emitting diode, a laser diode, an electronic device or the like. A wafer can be produced.
Hereinafter, the laminated semiconductor 10 will be described in detail.

As the nitride-based compound semiconductor, for example, and by the general formula Al X Ga Y In Z N 1 -A M A (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1, X + Y + Z = 1. Symbol M Represents a group V element different from nitrogen (N), and 0 ≦ A <1). Many gallium nitride-based compound semiconductors are known. In the present invention, these well-known gallium nitrides are also known. including system compound semiconductor and the general formula Al X Ga Y in Z N 1 -a M a (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1, X + Y + Z = 1. symbol M nitrogen ( N) represents another group V element, and 0 ≦ A <1)). A gallium nitride-based compound semiconductor represented by 0) can be used without any limitation.

  Gallium nitride compound semiconductors can contain other group III elements in addition to Al, Ga, and In, and contain elements such as Ge, Si, Mg, Ca, Zn, Be, P, and As as necessary. You can also Furthermore, it is not limited to the element added intentionally, but may include impurities that are inevitably included depending on the film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.

The growth method of these gallium nitride-based compound semiconductors is not particularly limited, and nitride semiconductors such as MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy) are grown. All methods known to be applied are applicable. A preferred growth method is the MOCVD method from the viewpoint of film thickness controllability and mass productivity. In the MOCVD method, hydrogen (H 2 ) or nitrogen (N 2 ) as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) as a Ga source which is a group III source, trimethyl aluminum (TMA) or triethyl aluminum as an Al source (TEA), trimethylindium (TMI) or triethylindium (TEI) as an In source, ammonia (NH 3 ), hydrazine (N 2 H 4 ), or the like as an N source as a group V source. In addition, as a dopant, for n-type, monosilane (SiH 4 ) or disilane (Si 2 H 6 ) is used as a Si raw material, germanium gas (GeH 4 ) or tetramethyl germanium ((CH 3 ) 4 Ge) is used as a Ge raw material. And organic germanium compounds such as tetraethylgermanium ((C 2 H 5 ) 4 Ge) can be used. In the MBE method, elemental germanium can also be used as a doping source. For the p-type, for example, biscyclopentadienyl magnesium (Cp 2 Mg) or bisethylcyclopentadienyl magnesium (EtCp 2 Mg) is used as the Mg raw material.

<N-type semiconductor layer>
The n-type semiconductor layer 14 is usually laminated on the intermediate layer 12, and is composed of a base layer 14a, an n-type contact layer 14b, and an n-type cladding layer 14c. The n-type contact layer can also serve as an underlayer and / or an n-type cladding layer, but the underlayer can also serve as an n-type contact layer and / or an n-type cladding layer. It is.

"Underlayer"
The underlayer 14a is made of a group III nitride compound semiconductor, and is deposited on the intermediate layer 12.
As the material of the underlayer 14a, a material different from that of the intermediate layer 12 formed on the substrate 11 may be used. However, the Al X Ga 1-X N layer (0 ≦ x ≦ 1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1).

As a material used for the underlayer 14a, a group III nitride compound containing Ga, that is, a GaN-based compound semiconductor is used, and in particular, AlGaN or GaN can be preferably used.
Further, when the intermediate layer 12 has a hexagonal close-packed structure, it is necessary to loop dislocations by migration so that the base layer 14a does not inherit the crystallinity of the intermediate layer 12 as it is. In addition, GaN-based compound semiconductors containing Ga are mentioned, and AlGaN or GaN is particularly preferable.

The film thickness of the underlayer is preferably 0.1 μm or more, more preferably 0.5 μm or more, and most preferably 1 μm or more. An Al X Ga 1-X N layer with good crystallinity is more easily obtained when the thickness is increased.

The underlayer 14a may be configured to be doped with a dopant as necessary, or may be configured not to be doped.
When a conductive substrate is used as the substrate 11, as described above, the base layer 14 a is doped so that current flows in the vertical direction in the layer structure of the base layer 14 a, so It can be set as the structure which provides an electrode in this.
Further, when an insulating substrate is used as the substrate 11, a chip structure in which electrodes are formed on the same surface of the chip of the light emitting element is adopted, so that the substrate 11 is laminated on the substrate 11 via the intermediate layer 12. The underlying layer 14a can be an undoped crystal, which has better crystallinity.

  In the present embodiment, after the intermediate layer 12 is formed on the substrate 11 by the method described above, the underlayer 14a made of a group III nitride compound semiconductor can be formed thereon. It is not particularly necessary to perform an annealing process before film formation. However, generally, when a film formation of a group III nitride compound semiconductor is performed by a vapor phase chemical film formation method such as MOCVD, MBE, or VPE, it is processed through a temperature rising process and a temperature stabilization process without film formation. However, since the V group source gas is often circulated in the chamber in these processes, an annealing effect may occur as a result.

  In addition, as a carrier gas to be circulated at that time, a general one can be used without any limitation, and hydrogen or nitrogen widely used in a vapor phase chemical film forming method such as MOCVD may be used. However, when chemically relatively active hydrogen is used as the carrier gas, it is preferable to shorten the processing time because there is a risk of impairing the crystallinity and the flatness of the crystal surface.

  The method of laminating the underlayer 14a is not particularly limited, and any crystal growth method that can cause dislocation looping as in the above-described methods can be used without any limitation. In particular, the MOCVD method, the MBE method, and the VPE method are preferable because the above-described migration can be generated, and a film having a favorable crystallinity can be formed. Among these, the MOCVD method can be used more suitably in that a film having the best crystallinity can be obtained.

It is also possible to form the underlayer 14a made of a group III nitride compound semiconductor by sputtering. When the sputtering method is used, the apparatus can have a simple configuration as compared with the MOCVD method, the MBE method, or the like.
In the case where the underlayer 14a is formed by sputtering, the reactive sputtering method in which a group V material (nitrogen) is circulated in the reactor is used to control the crystallinity by controlling the reaction. Can be kept good, and the good crystallinity can be stably reproduced.

The temperature of the substrate 11 when forming the underlayer 14a, that is, the growth temperature of the underlayer 14a is preferably 800 ° C. or higher. This is because, by increasing the temperature of the substrate 11 when forming the base layer 14a, atom migration is likely to occur, and dislocation looping easily proceeds, more preferably 900 ° C. or more. 1000 ° C. or higher is most preferable.
In addition, the temperature of the substrate 11 when forming the base layer 14a needs to be lower than the temperature at which the crystal decomposes, and is preferably less than 1200 ° C. If the temperature of the substrate 11 when forming the underlayer 14a is within the above temperature range, the underlayer 14a with good crystallinity can be obtained.

"N-type contact layer"
As the n-type contact layer 14b, an Al X Ga 1-X N layer (0 ≦ x ≦ 1, preferably 0 ≦ x ≦ 0.5, and more preferably 0 ≦ x ≦ 0.1) as in the base layer 14a. It is preferable that it is comprised. Further, the n-type impurity is preferably doped, and the n-type impurity is contained at a concentration of 1 × 10 17 to 1 × 10 19 / cm 3 , preferably 1 × 10 18 to 1 × 10 19 / cm 3. In view of maintaining good ohmic contact with the negative electrode, suppressing crack generation, and maintaining good crystallinity. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably it is Si and Ge. The growth temperature is the same as that of the underlayer. Further, as described above, the n-type contact layer 14b can also be configured to serve also as a base layer.

  The gallium nitride-based compound semiconductor constituting the underlayer 14a and the n-type contact layer 14b preferably has the same composition, and the total film thickness thereof is 0.1 to 20 μm, preferably 0.5 to 15 μm, more preferably It is preferable to set in the range of 1 to 12 μm. When the film thickness is within this range, the crystallinity of the semiconductor is maintained well.

"N-type cladding layer"
It is preferable to provide an n-type cladding layer 14c between the n-type contact layer 14b and a light emitting layer 15 described later. By providing the n-type cladding layer 14c, it is possible to improve the deterioration of flatness generated on the outermost surface of the n-type contact layer 14b. The n-type cladding layer 14c can be formed of AlGaN, GaN, GaInN, or the like. Alternatively, a heterojunction of these structures or a superlattice structure in which a plurality of layers are stacked may be used. Needless to say, in the case of using GaInN, it is desirable to make it larger than the band gap of GaInN of the light emitting layer 15.

The film thickness of the n-type cladding layer 14c is not particularly limited, but is preferably in the range of 5 to 500 nm, more preferably in the range of 5 to 100 nm.
Further, the n-type doping concentration of the n-type cladding layer 14c is preferably in the range of 1 × 10 17 to 1 × 10 20 / cm 3 , more preferably in the range of 1 × 10 18 to 1 × 10 19 / cm 3 . A doping concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the light emitting element.

<P-type semiconductor layer>
The p-type semiconductor layer 16 is usually composed of a p-type cladding layer 16a and a p-type contact layer 16b. However, the p-type contact layer may also serve as the p-type cladding layer.

"P-type cladding layer"
The p-type cladding layer 16a is not particularly limited as long as it has a composition larger than the band gap energy of the light emitting layer 15 and can confine carriers in the light emitting layer 15. Preferably, the Al d Ga 1-d is used. N (0 <d ≦ 0.4, preferably 0.1 ≦ d ≦ 0.3). When the p-type cladding layer 16a is made of such AlGaN, it is preferable in terms of confining carriers in the light emitting layer 15. The thickness of the p-type cladding layer 16a is not particularly limited, but is preferably 1 to 400 nm, and more preferably 5 to 100 nm. The p-type doping concentration of the p-type cladding layer 16a is preferably 1 × 10 18 to 1 × 10 21 / cm 3 , more preferably 1 × 10 19 to 1 × 10 20 / cm 3 . When the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.

"P-type contact layer"
The p-type contact layer 16b includes at least Al e Ga 1-e N (0 ≦ e <0.5, preferably 0 ≦ e ≦ 0.2, more preferably 0 ≦ e ≦ 0.1). This is a gallium nitride compound semiconductor layer. When the Al composition is in the above range, it is preferable in terms of maintaining good crystallinity and good ohmic contact with a p-ohmic electrode (see translucent electrode 17 described later).
In addition, when the p-type dopant is contained at a concentration in the range of 1 × 10 18 to 1 × 10 21 / cm 3 , in terms of maintaining good ohmic contact, preventing generation of cracks, and maintaining good crystallinity. More preferably, it is the range of 5 * 10 < 19 > -5 * 10 < 20 > / cm < 3 >.
Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned.
Although the film thickness of the p-type contact layer 16b is not specifically limited, 10-500 nm is preferable, More preferably, it is 50-200 nm. When the film thickness is within this range, it is preferable in terms of light emission output.

<Light emitting layer>
The light emitting layer 15 is a layer that is stacked on the n-type semiconductor layer 14 and a p-type semiconductor layer 16 is stacked thereon, and as shown in FIG. 1, a barrier layer 15a made of a gallium nitride-based compound semiconductor and The well layers 15b made of gallium nitride compound semiconductor containing indium are alternately and repeatedly stacked, and the barrier layers 15a are stacked in the order of the n-type semiconductor layer 14 side and the p-type semiconductor layer 16 side. Formed.
In the example shown in FIG. 1, the light emitting layer 15 includes six barrier layers 15 a and five well layers 15 b that are alternately stacked, and the barrier layers 15 a are formed on the uppermost layer and the lowermost layer of the light emitting layer 15. The well layer 15b is arranged between the barrier layers 15a.

As the barrier layer 15a, for example, a gallium nitride-based material such as Al c Ga 1-c N (0 ≦ c <0.3) having a larger band gap energy than the well layer 15b made of a gallium nitride-based compound semiconductor containing indium. A compound semiconductor can be suitably used.
Furthermore, the well layer 15b can be formed using indium as the semiconductor gallium nitride-based compound containing, for example, can be used Ga 1-s In s N ( 0 <s <0.4) GaN such as indium.

  Further, the film thickness of the entire light emitting layer 15 is not particularly limited, but it is preferably a film thickness to the extent that a quantum effect is obtained, that is, a critical film thickness region. For example, the thickness of the light emitting layer 15 is preferably in the range of 1 to 500 nm, and more preferably around 100 nm. When the film thickness is in the above range, it contributes to the improvement of the light emission output.

[Translucent positive electrode]
The translucent positive electrode 17 is a translucent electrode formed on the p-type semiconductor layer 16 of the laminated semiconductor 10 manufactured as described above.
The material of the translucent positive electrode 17 is not particularly limited, but ITO (In 2 O 3 —SnO 2 ), AZO (ZnO—Al 2 O 3 ), IZO (In 2 O 3 —ZnO), GZO (ZnO— Materials such as Ga 2 O 3 ) can be provided by conventional means well known in the art. Further, any structure including a conventionally known structure can be used without any limitation.

  The translucent positive electrode 17 may be formed so as to cover almost the entire surface of the Mg-doped p-type semiconductor layer 16, or may be formed in a lattice shape or a tree shape with a gap. After forming the translucent positive electrode 17, thermal annealing may be performed for the purpose of alloying or transparency, but it may not be performed.

[Positive electrode bonding pad and negative electrode]
The positive electrode bonding pad 18 is an electrode formed on the translucent positive electrode 17 described above.
As the material of the positive electrode bonding pad 18, various structures using Au, Al, Ni, Cu and the like are well known, and those known materials and structures can be used without any limitation.
The thickness of the positive electrode bonding pad 18 is preferably in the range of 100 to 1000 nm. Further, in view of the characteristics of the bonding pad, the larger the thickness, the higher the bondability. Therefore, the thickness of the positive electrode bonding pad 18 is more preferably 300 nm or more. Furthermore, it is preferable to set it as 500 nm or less from a viewpoint of manufacturing cost.

The negative electrode 19 is formed to be in contact with the n-type contact layer 14 b of the n-type semiconductor layer 14 in the semiconductor layer in which the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are sequentially stacked on the substrate 11. The
Therefore, when forming the negative electrode 19, a part of the p-type semiconductor layer 16, the light emitting layer 15 and the n-type semiconductor layer 14 is removed to form an exposed region 14 d of the n-type contact layer 14 b, and the negative electrode is formed thereon. 19 is formed.
As the material of the negative electrode 19, negative electrodes having various compositions and structures are well known, and these known negative electrodes can be used without any limitation, and can be provided by conventional means well known in this technical field.

According to the manufacturing method of the group III nitride compound semiconductor light emitting device of the present embodiment as described above, the intermediate layer 12 is formed on the substrate 11 by the method of activating the raw material by plasma, such as sputtering. In addition, the partial pressure of nitrogen, which is a group V element, is regulated within the above range. As a result, the intermediate layer 12 made of a crystal film having good uniformity can be formed in a short time, and the intermediate layer 12 can be used as an alignment film having specific anisotropy for any substrate. 11 can be deposited. In addition, since the deposition rate of the intermediate layer 12 is improved, it is possible to prevent impurities such as deposits in the furnace from entering the film. Further, when the intermediate layer 12 is formed as a hexagonal close-packed structure, the intermediate layer 12 effectively functions as a buffer layer, and thus the semiconductor layer 20 made of a group III nitride compound semiconductor formed thereon is formed. Becomes a crystal film having good crystallinity.
Therefore, the intermediate layer 12 made of a group III nitride compound having good crystallinity and the semiconductor layer 20 made of a group III nitride semiconductor can be efficiently grown on the substrate 11, and the productivity is excellent and the cost is low. Thus, a group III nitride compound semiconductor light emitting device having excellent light emission characteristics can be obtained.

[lamp]
By combining the group III nitride compound semiconductor light emitting device according to the present invention and the phosphor as described above, a lamp can be configured by means well known to those skilled in the art. Conventionally, a technique for changing the emission color by combining a light emitting element and a phosphor is known, and such a technique can be adopted without any limitation.
For example, it is possible to obtain light having a longer wavelength than that of the light emitting element by appropriately selecting the phosphor, and white light emission by mixing the light emission wavelength of the light emitting element itself with the wavelength converted by the phosphor. It can also be set as the lamp which exhibits.
Further, the lamp can be used for any purpose such as a general bullet type, a side view type for a portable backlight, and a top view type used for a display.

  For example, as in the example shown in FIG. 4, when the coplanar electrode group III nitride compound semiconductor light-emitting element 1 is mounted in a shell shape, one of the two frames (frame 31 in FIG. 4). The light-emitting element 1 is bonded to the light-emitting element 1, and the negative electrode (see reference numeral 19 shown in FIG. 3) of the light-emitting element 1 is bonded to the frame 32 with a wire 34. Is joined to the frame 31 with a wire 33. And the bullet-type lamp 3 as shown in FIG. 4 can be produced by molding the periphery of the light emitting element 1 with a mold 35 made of a transparent resin.

  Further, the group III nitride compound laminated semiconductor according to the present invention can be used for a photoelectric conversion element such as a laser element or a light receiving element, or an electronic device such as HBT or HEMT, in addition to the above light emitting element. These semiconductor elements have various structures, and the semiconductor element structure stacked on the base layer 14a of the light emitting element 1 of the present embodiment is not limited at all including these known element structures.

  Next, the group III nitride compound semiconductor light-emitting device of the present invention will be described in more detail with reference to examples, but the present invention is not limited to these examples.

[Example]
FIG. 1 is a schematic cross-sectional view of a laminated semiconductor of a group III nitride compound semiconductor light-emitting device manufactured in this example.
In this example, on the c-plane of the substrate 11 made of sapphire, a layer of columnar crystal aggregates made of AlN is formed as an intermediate layer 12 using RF sputtering, and an underlayer 14a is formed thereon by MOCVD. Was used to form a layer made of GaN.

First, the substrate 11 made of sapphire that had been mirror-polished to such an extent that only one side could be used for epitaxial growth was introduced into the sputtering apparatus without any pretreatment such as wet processing. Here, an apparatus having a high-frequency power source and a mechanism capable of moving the position of the magnet in the target was used as the sputtering apparatus.
Then, after heating the substrate 11 to 750 ° C. in the sputtering apparatus and introducing nitrogen gas at a flow rate of 15 sccm, the pressure in the chamber is maintained at 0.08 Pa, and a high frequency bias of 50 W is applied to the substrate 11 side, The surface of the substrate 11 was cleaned by exposure to nitrogen plasma.

Next, argon and nitrogen gas were introduced into the sputtering apparatus while keeping the temperature of the substrate 11 as it was. Then, a high frequency bias of 2000 W was applied to the metal Al target side, the pressure in the furnace was maintained at 0.5 Pa, Ar gas was flowed at 15 sccm, and nitrogen gas was flowed at 5 sccm (the ratio of nitrogen in the entire gas was 25%) ), A columnar crystal intermediate layer 12 made of AlN was formed on the substrate 11 made of sapphire.
The magnet in the target was swung both when the substrate 11 was cleaned and when the film was formed.
Then, according to the film formation rate (0.067 nm / s) measured in advance, after the film formation of 40 nm of AlN (intermediate layer 12) by the treatment for the specified time, the plasma operation is stopped and the temperature of the substrate 11 is lowered. It was.

Further, the same operation as described above was performed under the condition that the sputtering time was fixed and the argon gas was circulated at 20 sccm (the ratio of nitrogen to the whole gas was 0%), the argon gas was circulated at 16 sccm, and the nitrogen gas was circulated at 4 sccm (gas The ratio of nitrogen to the whole is 20%), argon gas is supplied at 12 sccm, nitrogen gas is flowed at 8 sccm (the ratio of nitrogen to the whole gas is 40%), argon gas is flowed at 8 sccm, and nitrogen gas is flowed at 12 sccm (gas) The ratio of nitrogen to the whole is 60%), the condition that argon gas is 4 sccm and the nitrogen gas is circulated 16 sccm (ratio of nitrogen gas to the whole gas is 80%), the condition that only nitrogen gas is circulated 20 sccm (nitrogen gas relative to the whole gas) The ratio is 100%), and it is made of AlN on a substrate made of sapphire at 6 levels. To prepare a sample which was deposited layer. The magnet in the target was swung both when the substrate 11 was cleaned and when the film was formed.
Then, processing for a specified time was performed according to the film formation rate measured in advance, and after the 40 nm AlN (intermediate layer) was formed, the plasma operation was stopped and the temperature of the substrate was lowered.

Then, the substrate 11 on which the intermediate layer 12 was formed was taken out from the sputtering apparatus and introduced into the MOCVD furnace. Then, a sample on which a GaN layer (Group III nitride semiconductor) was formed was produced by the following procedure using the MOCVD method.
First, the substrate 11 was introduced into the reaction furnace. The substrate 11 was placed on a carbon susceptor for heating in a glove box substituted with nitrogen gas. And after circulating nitrogen gas in a furnace, the temperature of the board | substrate 11 was heated up to 1150 degreeC with the heater. After confirming that the substrate 11 was stabilized at a temperature of 1150 ° C., the valve of the ammonia piping was opened and the circulation of ammonia into the furnace was started. Next, hydrogen containing trimethylgallium (TMG) vapor was supplied into the furnace, and a process of attaching a GaN-based semiconductor constituting the underlayer 14 a onto the intermediate layer 12 formed on the substrate 11 was performed. . The amount of ammonia was adjusted so that the V / III ratio was 6000. After the growth of the GaN-based semiconductor for about 1 hour, the valve of the TMG piping was switched to stop the supply of the raw material into the reactor to stop the growth. Then, after the growth of the GaN-based semiconductor was completed, the energization to the heater was stopped, and the temperature of the substrate 11 was lowered to room temperature.

  Through the above steps, an intermediate layer 12 of an aggregate of columnar crystals made of AlN is formed on a substrate 11 made of sapphire, and further, an underlying layer 14a made of a GaN-based semiconductor having a thickness of 2 μm is formed thereon. A sample was prepared.

And the X-ray rocking curve (XRC) measurement of the undoped GaN layer (underlayer) grown by the above method was performed. For this measurement, a Cuβ ray X-ray generation source was used as a light source, and the measurement was performed on the (0002) plane which is the orientation plane and the (10-10) plane which is the vertical plane.
In general, in the case of a group III nitride compound semiconductor, the XRC spectrum half width of the (0002) plane is an index of crystal flatness (mosaicity), and the XRC spectrum half width of the (10-10) plane is It is an index of dislocation density (twist).

  The graph of FIG. 6 and Table 1 show the half width of the X-ray rocking curve (XRC) of the undoped GaN layer (underlayer) grown on the intermediate layer at each nitrogen concentration described above.

  As shown in FIG. 6 and Table 1, when an intermediate layer made of AlN is formed on a substrate using a sputtering method with a nitrogen concentration of 40%, (0002) ) Plane XRC spectrum half-width is 132.8 arcsec, (10-10) plane XRC spectrum half-width is 331.4 arcsec, both have good crystallinity and have a mirror-like surface. It could be confirmed. In this example, when the intermediate layer is formed with a nitrogen concentration in the range of 60 to 80%, the crystallinity of the undoped GaN layer formed thereon is good. In particular, the nitrogen concentration is set to 80%. When the intermediate layer is formed, the undoped GaN layer formed on the intermediate layer has a (0002) plane XRC spectrum half width of 77.8 arcsec and a (10-10) plane XRC spectrum half width of 218. It became 8 arcsec, and it became clear that it was the optimal nitrogen concentration.

  On the other hand, when the intermediate layer is formed with a nitrogen concentration of 20% or less, when AlN is sputtered, Al is formed as a metal on the substrate, and the surface of the intermediate layer becomes clouded. Measurement of line rocking curve (XRC) became impossible.

FIG. 7 shows an XRC spectrum half-value width of (20-24) plane on the surface of an undoped GaN layer (underlayer) formed on an intermediate layer made of AlN with a nitrogen concentration of 95%. A reciprocal lattice space map of a sample having a value of 185 arcsec is shown. Further, in FIG. 8, the intermediate layer was formed with a nitrogen concentration of 75%, and the XRC spectrum half-value width of the (20-24) plane was 69 arcsec on the surface of the undoped GaN layer formed thereon. A reciprocal space map of the sample is shown. Here, in FIGS. 7 and 8, the horizontal axis is a-axis information, and the vertical axis is c-axis information, which is a comparison at substantially the same scale.
In the reciprocal space map shown in FIG. 8, the diffraction pattern on the (20-24) plane of the undoped GaN layer is distributed in both the a-axis direction and the c-axis direction compared to the diffraction pattern shown in the reciprocal space map of FIG. Is small, and the peak area is small. This corresponds to a decrease in dislocation density (twist), and indicates that the lower the dislocation density, the better the crystallinity of the undoped GaN layer.

  From the above results, it is clear that the group III nitride compound semiconductor light emitting device according to the present invention is excellent in productivity and has excellent light emitting characteristics.

  The group III nitride compound semiconductor light emitting device according to the present invention has a surface layer made of a group III nitride compound semiconductor crystal having good crystallinity. Accordingly, by forming a group III nitride compound semiconductor crystal layer having further functions thereon, a semiconductor such as a light emitting diode (LED), a laser diode (LD), or an electronic device having excellent light emission characteristics. A light emitting element can be manufactured.

It is a figure which illustrates typically an example of the group III nitride compound semiconductor light-emitting device based on this invention, and is the schematic which shows the cross-section of a laminated semiconductor. It is a figure which illustrates typically an example of the group III nitride compound semiconductor light-emitting device based on this invention, and is the schematic which shows a planar structure. It is a figure which illustrates typically an example of the group III nitride compound semiconductor light-emitting device concerning the present invention, and is a schematic diagram showing a section structure. It is the schematic explaining typically the lamp | ramp comprised using the group III nitride compound semiconductor light-emitting device based on this invention. It is a figure which illustrates typically an example of the manufacturing method of the group III nitride compound semiconductor light-emitting device based on this invention, and is the schematic which shows the structure of a sputtering device. It is a figure explaining the Example of the group III nitride compound semiconductor light-emitting device based on this invention, and is a graph which shows the XRC spectrum half value width in the (0002) plane of a base layer and a (10-10) plane. It is a figure explaining the Example of the group III nitride compound semiconductor light-emitting device based on this invention, and is a map which shows the reciprocal lattice space in the (20-24) plane of a base layer. It is a figure explaining the Example of the group III nitride compound semiconductor light-emitting device based on this invention, and is a map which shows the reciprocal lattice space in the (20-24) plane of a base layer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Group III nitride compound semiconductor light emitting element, 10 ... Multilayer semiconductor, 11 ... Substrate, 11a ... Surface, 12 ... Intermediate layer, 13 ... Underlayer, 14 ... N-type semiconductor layer, 14a ... Underlayer, 15 ... Light emitting layer 16 ... p-type semiconductor layer, 17 ... translucent positive electrode, 3 ... lamp

Claims (37)

  1. An intermediate layer made of a group III nitride compound is formed on a substrate by activating and reacting a gas containing a group V element and a metal material with plasma, and the group III nitride compound semiconductor is formed on the intermediate layer. A group III nitride compound semiconductor light-emitting device comprising sequentially stacking an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer comprising:
    Group III nitride compound semiconductor light emission characterized in that the group V element is nitrogen and the gas fraction of nitrogen in the gas when forming the intermediate layer is in the range of more than 20% and 99% or less Device manufacturing method.
  2.   The group III nitride compound semiconductor light-emitting element according to claim 1, wherein a gas fraction of nitrogen in the gas when forming the intermediate layer is in a range of more than 20% and 60% or less. Production method.
  3.   2. The group III nitride compound semiconductor light-emitting element according to claim 1, wherein a gas fraction of nitrogen in the gas when forming the intermediate layer is in a range of more than 20% and 50% or less. Production method.
  4.   The method for manufacturing a group III nitride compound semiconductor light-emitting element according to claim 1, wherein the intermediate layer is formed by sputtering.
  5.   The method for producing a group III nitride compound semiconductor light-emitting device according to claim 4, wherein the intermediate layer is formed by RF sputtering.
  6.   6. The method for producing a group III nitride compound semiconductor light-emitting device according to claim 5, wherein the intermediate layer is formed using an RF sputtering method while moving a cathode magnet.
  7.   The group III nitride compound semiconductor light emitting device according to any one of claims 3 to 6, wherein the intermediate layer is formed by a reactive sputtering method in which a gas containing a group V element is circulated in the reactor. Device manufacturing method.
  8.   The method for manufacturing a group III nitride compound semiconductor light-emitting element according to claim 1, wherein the metal material is a material containing Al.
  9.   The method for producing a group III nitride compound semiconductor light-emitting element according to claim 1, wherein the intermediate layer is formed of AlN.
  10.   The method for manufacturing a group III nitride compound semiconductor light-emitting element according to any one of claims 1 to 9, wherein the intermediate layer is formed by setting the temperature of the substrate in a range of room temperature to 1000 ° C.
  11.   The method for manufacturing a group III nitride compound semiconductor light-emitting element according to any one of claims 1 to 9, wherein the intermediate layer is formed with a temperature of the substrate in a range of 200 to 800 ° C.
  12.   The method for producing a group III nitride compound semiconductor light-emitting element according to claim 1, wherein an underlayer provided in the n-type semiconductor layer is laminated on the intermediate layer.
  13.   13. The method for manufacturing a group III nitride compound semiconductor light-emitting element according to claim 12, wherein the underlayer is formed of a GaN-based compound semiconductor.
  14.   The method of manufacturing a group III nitride compound semiconductor light-emitting element according to claim 13, wherein the underlayer is formed of GaN.
  15.   The method of manufacturing a group III nitride compound semiconductor light-emitting element according to claim 13, wherein the underlayer is formed of AlGaN.
  16.   The method for producing a group III nitride compound semiconductor light-emitting element according to any one of claims 12 to 15, wherein the intermediate layer and the base layer are formed of different group III nitride compounds, respectively.
  17.   The method of manufacturing a group III nitride compound semiconductor light-emitting element according to any one of claims 12 to 16, wherein the underlayer is formed on the intermediate layer by MOCVD.
  18.   18. The method for producing a group III nitride compound semiconductor light-emitting element according to claim 12, wherein the temperature of the substrate when forming the underlayer is 800 ° C. or higher.
  19.   A group III nitride compound semiconductor light-emitting device obtained by the manufacturing method according to claim 1.
  20. An intermediate layer made of a group III nitride compound is formed on a substrate by reacting a gas containing a group V element and a metal material by being activated by plasma, and the group III nitride compound is formed on the intermediate layer. A group III nitride compound semiconductor light-emitting device in which an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer made of a semiconductor are sequentially stacked,
    The intermediate layer is formed in such a manner that the group V element is nitrogen and the nitrogen gas fraction in the gas is in the range of more than 20% and 99% or less. III Group nitride compound semiconductor light emitting device.
  21.   The intermediate layer is formed in such a manner that the group V element is nitrogen and the nitrogen gas fraction in the gas is in the range of more than 20% and 60% or less. Item 21. A Group III nitride compound semiconductor light-emitting device according to Item 20.
  22.   The intermediate layer is formed in such a manner that the group V element is nitrogen and the gas fraction of nitrogen in the gas is in the range of more than 20% and 50% or less. Item 21. A Group III nitride compound semiconductor light-emitting device according to Item 20.
  23.   The group III nitride compound semiconductor light-emitting element according to any one of claims 20 to 22, wherein the intermediate layer has a composition containing Al.
  24.   24. The group III nitride compound semiconductor light-emitting element according to claim 23, wherein the intermediate layer is made of AlN.
  25.   The group III nitride compound semiconductor light-emitting element according to any one of claims 20 to 24, wherein the intermediate layer is formed so as to cover at least 90% or more of the substrate surface.
  26.   The group III nitride compound semiconductor light-emitting element according to any one of claims 20 to 25, wherein the intermediate layer is formed so as to cover at least a side surface of the substrate.
  27.   27. The group III nitride compound semiconductor light-emitting element according to claim 20, wherein the intermediate layer is formed so as to cover a side surface and a back surface of the substrate.
  28.   The group III nitride compound semiconductor light-emitting device according to any one of claims 20 to 27, wherein the intermediate layer is made of an aggregate of columnar crystals.
  29.   29. The group III nitride compound semiconductor light-emitting element according to claim 28, wherein the intermediate layer has an average grain width of 1 to 100 nm in each of the columnar crystals.
  30.   29. The group III nitride compound semiconductor light emitting device according to claim 28, wherein the intermediate layer has an average grain width of 2 to 70 nm in each of the columnar crystals.
  31.   31. The group III nitride compound semiconductor light-emitting device according to claim 28, wherein the intermediate layer is formed as a hexagonal close-packed structure.
  32.   32. The group III nitride compound semiconductor light-emitting element according to claim 20, wherein the intermediate layer has a thickness in a range of 20 to 80 nm.
  33.   The group III nitride compound semiconductor light-emitting element according to any one of claims 20 to 32, wherein a base layer provided in the n-type semiconductor layer is laminated on the intermediate layer.
  34.   34. The group III nitride compound semiconductor light-emitting element according to claim 33, wherein the underlayer is made of a GaN-based compound semiconductor.
  35.   The group III nitride compound semiconductor light-emitting element according to claim 34, wherein the underlayer is made of GaN.
  36.   The group III nitride compound semiconductor light-emitting device according to claim 34, wherein the underlayer is made of AlGaN.
  37.   37. A lamp comprising the group III nitride compound semiconductor light-emitting device according to any one of claims 19 to 36.
JP2007211377A 2006-12-20 2007-08-14 Method for manufacturing group iii nitride compound semiconductor light-emitting element, the group iii nitride compound semiconductor light-emitting element and lamp Pending JP2008177523A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006343019 2006-12-20
JP2007211377A JP2008177523A (en) 2006-12-20 2007-08-14 Method for manufacturing group iii nitride compound semiconductor light-emitting element, the group iii nitride compound semiconductor light-emitting element and lamp

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007211377A JP2008177523A (en) 2006-12-20 2007-08-14 Method for manufacturing group iii nitride compound semiconductor light-emitting element, the group iii nitride compound semiconductor light-emitting element and lamp

Publications (1)

Publication Number Publication Date
JP2008177523A true JP2008177523A (en) 2008-07-31

Family

ID=39704297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007211377A Pending JP2008177523A (en) 2006-12-20 2007-08-14 Method for manufacturing group iii nitride compound semiconductor light-emitting element, the group iii nitride compound semiconductor light-emitting element and lamp

Country Status (2)

Country Link
JP (1) JP2008177523A (en)
CN (1) CN101542756A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2862199A4 (en) * 2012-06-18 2016-02-24 Government Of The U S A As Represented By The Secretary Of The Navy Plasma-assisted atomic layer epitaxy of cubic and hexagonal inn films and its alloys with ain at low temperatures

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60173829A (en) * 1984-02-14 1985-09-07 Nippon Telegr & Teleph Corp <Ntt> Growing method of compound semiconductor thin-film
JPH04297023A (en) * 1991-01-31 1992-10-21 Nichia Chem Ind Ltd Crystal growth method of gallium nitride compound semiconductor
JPH0586646A (en) * 1991-09-30 1993-04-06 Maeda Corp Construction of steel pipe column with beam connected thereto
JPH11354846A (en) * 1996-01-19 1999-12-24 Matsushita Electric Ind Co Ltd Gallium nitride type compound semiconductor light emitting element and manufacture of gallium nitride type compound semiconductor
JP3026087B2 (en) * 1989-03-01 2000-03-27 名古屋大学長 Gas phase growth method of gallium nitride based compound semiconductor
JP2001094150A (en) * 1999-09-21 2001-04-06 Toyoda Gosei Co Ltd Group iii nitride compound semiconductor element
JP2001308010A (en) * 2000-04-21 2001-11-02 Toyoda Gosei Co Ltd Method of manufacturing iii nitride compound semiconductor device
JP2003096561A (en) * 2001-09-25 2003-04-03 Sharp Corp Sputtering apparatus
JP3440873B2 (en) * 1999-03-31 2003-08-25 豊田合成株式会社 Method for manufacturing group III nitride compound semiconductor device
JP2004153062A (en) * 2002-10-31 2004-05-27 Shin Etsu Handotai Co Ltd Zn-based semiconductor light emitting element and its manufacturing method
JP2004179457A (en) * 2002-11-28 2004-06-24 Toyoda Gosei Co Ltd Method for manufacturing group iii nitride compound semiconductor element
JP2005244202A (en) * 2004-01-26 2005-09-08 Showa Denko Kk Group iii nitride semiconductor laminate
JP2006120841A (en) * 2004-10-21 2006-05-11 Toyoda Gosei Co Ltd Method of manufacturing semiconductor

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60173829A (en) * 1984-02-14 1985-09-07 Nippon Telegr & Teleph Corp <Ntt> Growing method of compound semiconductor thin-film
JP3026087B2 (en) * 1989-03-01 2000-03-27 名古屋大学長 Gas phase growth method of gallium nitride based compound semiconductor
JPH04297023A (en) * 1991-01-31 1992-10-21 Nichia Chem Ind Ltd Crystal growth method of gallium nitride compound semiconductor
JPH0586646A (en) * 1991-09-30 1993-04-06 Maeda Corp Construction of steel pipe column with beam connected thereto
JPH11354846A (en) * 1996-01-19 1999-12-24 Matsushita Electric Ind Co Ltd Gallium nitride type compound semiconductor light emitting element and manufacture of gallium nitride type compound semiconductor
JP3440873B2 (en) * 1999-03-31 2003-08-25 豊田合成株式会社 Method for manufacturing group III nitride compound semiconductor device
JP3700492B2 (en) * 1999-09-21 2005-09-28 豊田合成株式会社 Group III nitride compound semiconductor device
JP2001094150A (en) * 1999-09-21 2001-04-06 Toyoda Gosei Co Ltd Group iii nitride compound semiconductor element
JP2001308010A (en) * 2000-04-21 2001-11-02 Toyoda Gosei Co Ltd Method of manufacturing iii nitride compound semiconductor device
JP2003096561A (en) * 2001-09-25 2003-04-03 Sharp Corp Sputtering apparatus
JP2004153062A (en) * 2002-10-31 2004-05-27 Shin Etsu Handotai Co Ltd Zn-based semiconductor light emitting element and its manufacturing method
JP2004179457A (en) * 2002-11-28 2004-06-24 Toyoda Gosei Co Ltd Method for manufacturing group iii nitride compound semiconductor element
JP2005244202A (en) * 2004-01-26 2005-09-08 Showa Denko Kk Group iii nitride semiconductor laminate
JP2006120841A (en) * 2004-10-21 2006-05-11 Toyoda Gosei Co Ltd Method of manufacturing semiconductor

Also Published As

Publication number Publication date
CN101542756A (en) 2009-09-23

Similar Documents

Publication Publication Date Title
US8513694B2 (en) Nitride semiconductor device and manufacturing method of the device
US8471266B2 (en) Group III nitride semiconductor multilayer structure and production method thereof
JP5246213B2 (en) Group III nitride semiconductor light emitting device manufacturing method
KR101416838B1 (en) Method for conductivity control of (Al,In,Ga,B)N
JP5399552B2 (en) Nitride semiconductor element manufacturing method, nitride semiconductor light emitting element, and light emitting device
US5239188A (en) Gallium nitride base semiconductor device
US6852161B2 (en) Method of fabricating group-iii nitride semiconductor crystal, method of fabricating gallium nitride-based compound semiconductor, gallium nitride-based compound semiconductor, gallium nitride-based compound semiconductor light-emitting device, and light source using the semiconductor light-emitting device
EP2012372B1 (en) Method for manufacturing gallium nitride compound semiconductor light emitting element
KR100902576B1 (en) Type group ? nitride semiconductor stacked layer structure
KR100692267B1 (en) Production method of group ? nitride semiconductor crystal
JP4734786B2 (en) Gallium nitride compound semiconductor substrate and manufacturing method thereof
WO2009139376A1 (en) Process for producing group iii nitride semiconductor light-emitting element, group iii nitride semiconductor light-emitting element, and lamp
JP5201563B2 (en) Group III nitride semiconductor light emitting device
CN102017082B (en) Group III nitride semiconductor device and method for manufacturing the same, group III nitride semiconductor light-emitting device and method for manufacturing the same, and lamp
EP1673815B1 (en) Group iii nitride semiconductor element and semiconductor devices incorporating the same
US8882910B2 (en) AlGaN substrate and production method thereof
JP4963763B2 (en) Semiconductor element
TWI413279B (en) Group iii nitride semiconductor light emitting device, process for producing the same, and lamp
KR20080003913A (en) Group 3-5 nitride semiconductor multilayer substrate, method for manufacturing group 3-5 nitride semiconductor free-standing substrate, and semiconductor element
JP4833616B2 (en) Method for producing group III nitride semiconductor
US7749785B2 (en) Manufacturing method of group III nitride semiconductor light-emitting device
CN101689592B (en) III nitride semiconductor light emitting element, method for manufacturing the iii nitride semiconductor light emitting element, and lamp
KR101580033B1 (en) 3 method for producing group nitride semiconductor
WO2013005789A1 (en) Method of manufacture for nitride semiconductor light emitting element, wafer, and nitride semiconductor light emitting element
DE112005000296B4 (en) Gallium nitride compound semiconductor multilayer structure, lamp with it and manufacturing method for it

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20100510

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120125

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121030

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20130206

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130312