JP2008160513A - Imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging device enabled to control the quantity of emission of auxiliary light by performing direct light measurement based upon an output signal of a pixel signal itself of an imaging element. <P>SOLUTION: The imaging device comprises an auxiliary light emission unit 116 which emits the auxiliary light to an object, an imaging means 105 which has many pixels arrayed in a matrix, pixel signal weighted average circuits B1, B2, ..., which nondestructively detect potentials of a plurality of pixels of the imaging element and generate an auxiliary light control signal based upon a weighted average value of the nondestructively detected potentials, and a system controller 113 which controls the quantity of emission of the auxiliary light based upon the auxiliary light control signal. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an imaging apparatus that performs exposure control by direct photometry.

  Conventionally, in Japanese Patent Laid-Open No. 5-316411, in an electronic still camera that receives imaging light by a solid-state image sensor and performs still imaging of a subject image, reflected light of the imaging light is collected from the imaging surface of the solid-state image sensor. Thus, there is disclosed an electronic still camera that includes a photometric element to be detected and controls exposure based on a photometric output from the photometric element.

Japanese Patent Laid-Open No. 2003-15181 discloses a transparent photometry unit in which a plurality of transparent light receiving elements are provided in a thin film shape on a transparent glass substrate between a photographing lens and a CCD image sensor. And a camera that realizes the light emission control of the strobe by direct photometry based on the output signal of the light receiving element.
Japanese Patent Laid-Open No. 5-316411 JP 2003-15181 A

  By the way, in the electronic still camera disclosed in JP-A-5-316411, the reflecting surface of the solid-state image sensor is close to a mirror surface, so that the reflected light of the imaging light does not diffuse and depends on the focal length and aperture value of the photographing lens. It performs regular reflection depending on the incident angle and position of the changing light beam. Therefore, there is a problem that the photometric accuracy of the reflected light is lowered. In the camera disclosed in Japanese Patent Laid-Open No. 2003-15181, since the light receiving element is arranged in front of the imaging surface, the sensitivity of the CCD image sensor is lowered. In addition, since the light receiving element is disposed in front of the imaging surface, there is a problem that unevenness in transmittance due to the wiring of the light receiving element is picked up as it is and the image quality is deteriorated.

  The present invention has been made in order to solve the above-mentioned problems in conventional electronic cameras or cameras, and can directly control light emission based on the output signal of the pixel signal itself of the image sensor to control the amount of auxiliary light emitted. An object is to provide an imaging device.

  In order to solve the above-described problems, an invention according to claim 1 is directed to an auxiliary light emitting unit that emits auxiliary light to a subject, a solid-state imaging device in which a large number of pixels are arranged in a matrix, and an amount of light received by the solid-state imaging device. The imaging device is configured to include a light emission amount control unit that detects the potential of the pixel in accordance with the non-destructive and controls the light emission amount of the auxiliary light based on the non-destructive detected potential.

  According to a second aspect of the present invention, in the imaging apparatus according to the first aspect, the light emission amount control unit detects potentials of a plurality of pixels of the solid-state imaging device in a nondestructive manner, and weights the potentials detected in the nondestructive manner. The light emission amount of the auxiliary light is controlled based on an average value.

  According to a third aspect of the present invention, in the imaging device according to the first aspect, the solid-state image sensor has green (G), red (R), and blue (B) filter segments on the imaging surface of the solid-state image sensor. The light emission amount control unit detects the potential of the pixels corresponding to the filter segments of R (red), G (green), and B (blue) in a nondestructive manner. A luminance signal is generated based on a weighted average value of potential detected by destruction, and a light emission amount of the auxiliary light is controlled based on the luminance signal.

  According to a fourth aspect of the present invention, in the imaging apparatus according to the first aspect, the solid-state imaging device has green (G), red (R), blue (B), and colorless (W) filter segments on the imaging surface. The light emission amount control unit includes a regularly arranged color filter, and detects the potential of a pixel corresponding to the colorless (W) filter segment in a nondestructive manner, and based on the potential detected in the nondestructive manner, The light emission amount is controlled.

  According to a fifth aspect of the present invention, in the imaging apparatus according to the first aspect, the light emission amount control unit determines a potential of a pixel in a subject area (focus area) to be autofocused among the pixels of the solid-state imaging element. The non-destructive detection is performed, and the emission amount of the auxiliary light is controlled based on the non-destructive detected potential.

  According to a sixth aspect of the present invention, in the imaging device according to the fifth aspect, the imaging device can detect the focus of a subject in a plurality of focus areas, and the light emission amount control unit corresponds to each focus area. The weighted average value is detected nondestructively for each partial region of the solid-state imaging device, and the light emission amount of the auxiliary light is controlled based on the weighted average value of the potential detected nondestructively. It is.

  According to a seventh aspect of the present invention, in the imaging apparatus according to the first aspect, the light emission amount control unit detects the potential of the pixel of the solid-state imaging element nondestructively by a source follower circuit, and the potential detected nondestructively. The amount of the auxiliary light emitted is controlled based on the above.

  According to an eighth aspect of the present invention, in the imaging apparatus according to the first aspect, the light emission amount control unit detects potentials of a plurality of pixels in a predetermined partial region of the solid-state imaging element in a nondestructive manner. The weighted average value is calculated by receiving the detected potentials of the plurality of pixels at the input portion of the νMOS transistor, and the light emission amount of the auxiliary light is controlled based on the weighted average value.

  According to the present invention, since the exposure amount received by the image sensor is directly read out and the light emission amount of the auxiliary light is controlled, the direct light metering of the small and simple configuration is performed by the auxiliary light without providing a member such as a half mirror to block the light beam. The amount of exposure can be controlled. In addition, the brightness of the desired subject area can be controlled very accurately. Further, the weighted average can be obtained with a simple configuration, and the emission amount of the auxiliary light can be controlled.

  Next, the best mode for carrying out the present invention will be described.

(Example 1)
First, a first embodiment of the imaging apparatus according to the present invention will be described. FIG. 1 is a block diagram illustrating the overall configuration of the imaging apparatus (camera) according to the first embodiment. As shown in FIG. 1, this camera includes a lens system 101, a lens driving mechanism 102, an exposure control mechanism 103, a mechanical shutter 104, a shutter driving circuit 121, an image sensor 105, and a TG block (in the drawing). 106, a preprocess circuit 107, an A / D converter 108, a digital process circuit 109, a card interface (abbreviated as card I / F in the figure) 110, and a memory card. 111, LCD display unit 112, system controller 113, operation switch 114, lens driver 115, auxiliary light emitting unit 116, exposure control driver 117, AF (autofocus) mechanism 118, EEPROM 119, communication An interface 120 and a shutter drive circuit 121 are provided.

  The lens system 101 includes various lenses such as a focus lens for adjusting the focal position and a zoom lens for adjusting the focal distance, for example. The lens driving mechanism 102 is for driving the lens system 101 to perform, for example, focus adjustment. When the lens system 101 is a zoom lens system capable of power zooming, the lens driving mechanism 102 may further perform zoom adjustment. The exposure control mechanism 103 includes a stop provided on the optical path of the lens system 101 and a control mechanism for controlling the stop. The mechanical shutter 104 is for mechanically controlling the time required for the light beam incident from the lens system 101 via the exposure control mechanism 103 to reach the image sensor 105. The shutter drive circuit 121 is for driving the mechanical shutter 104 under the control of the system controller 113. The image sensor 105 captures a subject image and also serves as a light receiving element for direct photometry. As the image sensor 105, for example, a solid-state image sensor such as a CMOS image sensor is used. The TG block 106 is a timing generator for driving the image sensor 105. The TG block 106 synchronizes the drive timing of the image sensor 105 with the operation timing of the preprocess circuit 107, the A / D converter 108 and the digital process circuit 109.

  The preprocess circuit 107 is a circuit for pre-processing a signal output from the image sensor 105, and includes, for example, an amplifier and a clamp circuit. The A / D converter 108 is a circuit that converts the analog image signal processed by the preprocess circuit 107 into digital data. The digital process circuit 109 is for performing various digital processing including color signal generation processing, matrix conversion processing, and preview processing. The digital process circuit 109 includes a buffer memory 109a for storing image data and an AF processing circuit 109b. The AF processing circuit 109b is a circuit that extracts a high frequency component from a luminance component of image data for one frame stored in the buffer memory 109a by a high-pass filter or the like and calculates a cumulative addition value.

  The card interface 110 performs control (recording control) for recording the image data processed by the digital process circuit 109 on the memory card 111, or performs control (reading control) for reading the image data already recorded on the memory card 111. The interface to perform. The memory card 111 is a non-volatile recording medium for recording image data, various information related to the image data, and the like, and is configured to be detachable from the camera, for example. The LCD display unit 112 is a display means for displaying an image immediately after photographing, displaying a photographed image recorded in the memory card 111, and displaying various information relating to the camera. The system controller 113 is a control means for comprehensively controlling each unit in the camera, and includes a CPU, for example. The system controller 113 has an internal memory or the like (not shown). The operation switch 114 is an operation means including all the various operation buttons provided on the camera. The operation switch 114 includes, for example, a shooting mode changeover switch and a release switch.

  The lens driver 115 is a driver for controlling the lens driving mechanism 102 described above. The auxiliary light emitting unit 116 is light emitting means for irradiating the subject with illumination light. A strobe light, a high brightness LED, or the like is used as the auxiliary light emitting unit. The exposure control driver 117 is exposure control means for controlling the above-described exposure control mechanism 103. The AF mechanism 118 is for detecting the amount of deviation from the focus matching position of the focus lens constituting the lens system 101. The EEPROM 119 is a nonvolatile memory for storing various setting information related to the camera. The communication interface 120 is an interface that controls communication with an external device.

  FIG. 2 is a block diagram showing the configuration of the image sensor 105. The imaging element 105 includes an imaging area 201, a vertical shift register 202, a CDS circuit (correlated double sampling circuit) 203, and a horizontal shift register 204. In the imaging area 201, a plurality of unit pixels are arranged in a matrix, and a mosaic color filter is arranged in front of the unit pixels. The vertical shift register 202 is a register for sequentially selecting pixel rows arranged in the imaging area 201. The CDS circuit 203 is for removing reset noise from the pixel signal output from the imaging area 201. The horizontal shift register 204 outputs a signal for sequentially reading out the pixel signal in the horizontal direction for each row selected by the vertical shift register 202.

  FIG. 3 is a circuit configuration diagram showing a detailed configuration of the unit pixels constituting the imaging area 201. FIG. 3 shows a configuration of a unit pixel 305 that constitutes a CMOS image sensor which is an example of the image sensor 105. As shown in FIG. 3, unit pixels 305 including a photodiode (PD) 301 serving as a photoelectric conversion element and a plurality of MOS transistors (302, 303, 304) are two-dimensionally arranged in a matrix and their outputs are connected. The column signal line 306 is connected to the CDS circuit 203 shown in FIG.

  The unit pixel 305 includes one PD 301 and three MOS transistors, a reset transistor 302 and an amplification transistor 303. The cathode of PD 301 is connected to the reset and the source of transistor 302, the gate is connected to row reset line 307, and the drain is connected to power supply wiring 310. The cathode of the PD 301 is also connected to the gate of the charge readout transistor 303, and the source of the charge readout transistor 303 is connected to the drain of the row selection transistor 304 and the monitor signal line 309. The drain of the charge readout transistor 303 is connected to the power supply wiring 310. The monitor signal line 309 is connected to the gate of a later-described neuro MOS (νMOS) transistor as a non-destructive readout signal line for the amount of charge generated in the unit pixel 305 for direct photometry. This will be described in detail later. The source of the row selection transistor 304 is connected to the column signal line 306.

  The operation of the unit pixel 305 is roughly as follows. When the pulse φRS is applied to the row reset line 307, the reset transistor 302 is turned on, and the charge accumulated in the junction capacitance of the PD 301 is reset. Immediately after resetting, the PD 301 accumulates an optical signal in the junction capacitance. When the accumulation of the optical signal for a predetermined time is completed, the row selection transistor 304 is turned on by the pulse φSEL applied to the row selection line 308, and the level of the charge accumulated in the PD 301 passes through the column signal line 306 and the CDS circuit 203. Read out. The configuration and operation of the unit pixel 305 are known except for the monitor signal line 309.

  The pixel signal weighted average circuit B1 shown in FIG. 4 includes a weighted average value of the amount of charge generated by the plurality of pixels 305 and read to the monitor signal line 309 in a nondestructive manner (hereinafter also including an average value when all the weighting coefficients are equal). And a signal that controls the light emission amount of the auxiliary light by comparing the average value with a predetermined threshold value Vref.

  Next, the configuration and operation of the auxiliary light emission amount control signal output circuit shown in FIG. 4 will be described. A Bayer color filter as shown in FIG. 5 is arranged in front of the imaging surface of the imaging element 105 in this embodiment. In FIG. 4, pixels 1 to 27 are pixels having the same configuration as the unit pixel 305 shown in FIG. Among these, the pixel (3n-2) (n = 1 to 9) is a pixel corresponding to the R (red) filter segment of the color filter, and the pixel (3n-1) (n = 1 to 9) is the color filter. Pixels 3n (n = 1 to 9) corresponding to the G (green) filter segment are pixels corresponding to the filter segment B (blue) of the color filter. It is assumed that nine sets of pixels (3n-2), (3n-1), and 3n (n = 1 to 9) are arranged at adjacent positions. The monitor signal lines 309-1 to 309-27 are respectively connected to the sources of the charge readout transistors 303-1 to 303-27 of the nine sets of R, G, and B pixels shown in FIG. Yes. Note that the nine sets of RGB pixels are pixels at the nine positions in the enlarged view 702 of the area A1 among the five autofocus areas A1 to A5 of the screen 701 as shown in FIG.

  Common to the sources of the charge readout transistors 303-1 to 303-27 of each pixel, that is, the gates of the load transistors 403-1 to 403-27, each having a drain connected to the monitor signal lines 309-1 to 309-27. The control signal line 404 is connected to the source, and the source is grounded. Thus, the charge readout transistors 303-1 to 303-27 are grounded via the load transistors 403-1 to 403-27, respectively, and constitute source follower circuits using n-type MOS transistors, respectively. . Therefore, when the load transistors 403-1 to 403-27 are turned on by applying the gate voltage φLD1 from the control signal line 404, the potentials of the monitor signal lines 309-1 to 309-27 are substantially equal to the photodiodes of each pixel. The potential of the cathode is proportional to the amount of the optical signal accumulated in each pixel. The monitor signal lines 309-1 to 309-27 are connected to the gates G1 to G27 of the n-type νMOS transistor 401, respectively.

Next, the n-type νMOS transistor 401 will be described. The νMOS transistor is described in detail in Japanese Patent Application Laid-Open No. 2000-222386. The n-type νMOS transistor 401 has a plurality of gate electrodes G1 to G27 and a floating gate FLT1. The potentials of the monitor signal lines 309-1 to 309-27, that is, the potentials of the gate electrodes G1 to G27 are V1 to V27, the potential of the floating gate FLT1 is Vf, the potential of the substrate is V0, and the gate electrodes G1 to G27 and the floating gate FLT1 And the capacitance between the floating gate and the substrate is C0, the potential Vf of the floating gate FLT1 is
Vf = (C1V1 + C2V2 +... + C27V27) / (C0 + C1 + C2 +... C27) = ΣCiVi / ΣCj (i = 1 to 27, j = 0 to 27) (1)
It becomes.

  Since the capacitances C1 to C27 between the gate electrodes G1 to G27 and the floating gate FLT1 are proportional to the area of the gate electrodes G1 to G27, the expression (1) can be obtained by appropriately selecting the areas of the gate electrodes G1 to G27. This shows that the potential Vf of the floating gate FLT1 corresponding to the weighted average value of the potentials V1 to V27 of the monitor signal lines 309-1 to 309-27 can be obtained. That is, the luminance signal Y is represented by Y = 0.299 × R + 0.587 × G + 0.114 × B. Therefore, if the area of the gate electrode corresponding to R, G, B is 0.299: 0.587: 0.114, A corresponding potential Vf of the floating gate FLT1 can be obtained.

  Assuming that the floating gate FLT1 of the n-type νMOS transistor 401 is the MOS transistor having the gate electrode, the n-type νMOS transistor 401 has the potential V1 of the monitor signal lines 309-1 to 309-27 of the pixels 1 to 27 at the gate electrode. It can be regarded as a MOS transistor to which a voltage corresponding to V27, that is, a weighted average value of the optical signal generated in each of the pixels 1 to 27 is applied.

  The drain of the n-type νMOS transistor 401 is connected to the power supply terminal 310 and the source thereof is connected to the drain of the load transistor 402 and the input of the comparator C1. The source of the load transistor 402 is grounded, and its gate is connected to the control signal line 404. Thus, the n-type νMOS transistor 401 and the load transistor 402 constitute a source follower circuit using an n-type MOS transistor. Therefore, when the load transistor 402 is turned on by applying the gate voltage φLD1 from the control signal line 405, the potential corresponding to the weighted average value of the optical signals generated in the pixels 1 to 27 is applied to the source of the n-type νMOS transistor 401. Appears. Then, this potential is compared with a predetermined threshold voltage Vref by the comparator C1, and the light emission amount of the auxiliary light is controlled by the compared signal.

  The circuit configuration and operation for controlling the amount of auxiliary light based on the signal corresponding to the weighted average value of the optical signals of the nine pixels in the focus detection area A1 in FIG. 6 have been described. Also for A2 to A5, pixel signal weighted averaging circuits B2 to B5 are configured similarly to B1 of FIG. The output signals are connected to the comparators C2 to C5 in FIG. Similarly, a predetermined threshold voltage Vref is applied to the other inputs of the comparators C2 to C5. Output lines S1 to S5 of the comparators C1 to C5 are connected to the selection circuit 405. The selection signal line 406 of the selection circuit 405 includes comparators C1 to C5 based on the photoelectric charges of the pixels in the same region as one of the focus detection regions A1 to A5 selected by the photographer based on the control by the system controller 113. A selection signal for selecting one of the output signals is input. The selection circuit 405 connects one of the output signal lines S1 to S5 of the comparators C1 to C5 to the auxiliary light control signal line 407 based on the selection signal.

  Next, the overall operation flow of the imaging apparatus according to the present embodiment will be described with reference to FIG. First, the photographer operates a predetermined selection unit of the operation switch 114 to select one area from the focus detection areas A1 to A5 in FIG. Assume that the focus detection area A1 is selected. Next, when the photographer presses the release operation button of the operation switch 114 with a light force (1st release), the aperture of the taking lens is controlled via the exposure control driver 117 under the control of the system controller 113.

  The system controller 113 sequentially compares the accumulated value of the high-frequency component of the image signal in the focus detection area A1 calculated in the AF processing circuit 109b while driving the lens system 101 via the lens driver 115 and the lens driving mechanism 102. However, the lens system 101 is driven to the peak position of the accumulated value. Further, the gate voltage φLD1 is applied to the load transistors 402 and 403-1 to 403-27 of each source follower circuit of FIG. 4 to turn on all the load transistors.

  Next, when the photographer presses the release operation button of the operation switch 114 with a relatively strong force (2nd release), the system controller 113 performs exposure by running the shutter front curtain of the mechanical shutter 104 via the shutter drive circuit 121. To start. When the running of the shutter front curtain is completed and the shutter is fully opened, the system controller 113 then outputs a signal for starting the emission of auxiliary light to the auxiliary light emitting unit 116.

  In the signal weighted average circuits B1 to B5 in FIG. 4, a value corresponding to the weighted average of the optical signal amounts of nine RGB pixels in the corresponding focus detection areas A1 to A5 is calculated, and the value and a predetermined threshold voltage are calculated. Vref is compared by comparators C1-C5. In the selection circuit 405, one of the outputs of the comparators C1 to C5 is selected based on the selection signal of the selection signal line 406. In this example, since A1 is selected as the focus detection area, the selection circuit 405 selects the output of the comparator C1.

  When the auxiliary light emitting unit 116 emits light and the light emission amount reaches a predetermined value, the output signal of the auxiliary light control signal (auxiliary light emission stop signal) is inverted and the emission of auxiliary light is stopped. When the auxiliary light emission stop signal is output, the system controller 113 then starts running the shutter rear curtain of the mechanical shutter 104 via the shutter drive circuit 121. When the travel of the shutter rear curtain is completed, reading of the image signal from the image sensor 105 is started.

  In the present embodiment, the light emission amount of the auxiliary light is controlled based on the weighted average value of the nine RGB pixel outputs in each focus detection region. This number is required depending on the size of the focus detection region and the requirement. Of course, it can be appropriately selected according to the photometric accuracy.

(Example 2)
In the first embodiment, the Bayer arrangement is described as the color filter, but in this second embodiment, four types as shown in FIG. 8, that is, G (green), W (colorless), R (red), A color filter employing a B (blue) filter segment is used. Other main configurations are the same as those in the first embodiment. In this color filter, W filter segments are arranged vertically and horizontally with G as the center, and pixel outputs corresponding to the W filter segments are used as luminance signals. If such a color filter is used, the gate electrodes of the n-type νMOS transistor 401 may all have the same size. Further, the signal weighted average circuits B1 to B5 can calculate the same luminance with 1/3 the number of pixels as compared with the Bayer color filter.

(Example 3)
In the first and second embodiments, the light emission amount of the auxiliary light is controlled based on the weighted average value of the pixels in the region selected from the focus detection regions A1 to A5. The light emission amount of the auxiliary light is controlled based on the weighted average value of the optical signals of the pixels in all areas A1 to A5. In this case, problems such as an excessive increase in the number of gates of the n-type νMOS transistor and difficulty in arranging the n-type νMOS transistor occur.

  In order to solve this problem, the following configuration is adopted in the third embodiment. That is, in the first embodiment, an appropriate luminance signal is obtained by adjusting the area of the gate electrode of the n-type νMOS transistor with respect to the RGB pixels, but in this third embodiment, separation is performed for each of R, G, and B colors. Then, an average value was obtained, and a weighted average value of each average value was used as an average luminance signal of a plurality of pixels in each focus detection region. By doing so, the configuration of the n-type νMOS transistor can be simplified.

  FIG. 9 shows a pixel signal weighted average circuit of the third embodiment. Each gate of the n-type νMOS transistor 501 is connected to a monitor signal line of pixels (R pixels) of a predetermined number of R filter segments in the focus detection area A1 of FIG. The configuration of the circuit for deriving the monitor signal line from the pixel is the same as that of the first embodiment shown in FIG. The source of the n-type νMOS transistor 501 is connected to the drain of the load transistor 504, and its drain is connected to the power supply terminal 511. The source of the load transistor 504 is grounded, and its gate is connected to the control signal line 512. The source of the n-type νMOS transistor 501 is connected to the gate Gr of the n-type νMOS transistor 507.

  With such a configuration, the source potential of the n-type νMOS transistor 501 becomes an average value of the signal output of the R pixel connected to the gate thereof. With the same configuration, the average values of the G pixel and B pixel are applied to the gates Gg and Gb of the n-type νMOS transistor 507, respectively. The source of the n-type νMOS transistor 507 is connected to the drain of the load transistor 508, and its drain is connected to the power supply terminal 511. The source of the load transistor 508 is grounded, and its gate is connected to the control signal line 512. The size of the electrodes of the gates Gr, Gb, and Gb of the n-type νMOS transistor 507 is 0.299: 0.587: 0.114. Therefore, the potential of the source of the n-type νMOS transistor 507 is the predetermined pixel in the focus detection area A1. The value corresponds to the average luminance signal. The source of the n-type νMOS transistor 507 is connected to the gate of the n-type νMOS transistor 509.

  With the same configuration as described above, an average luminance signal of a predetermined number of pixels in the focus detection areas A2 to A5 is applied to the gate of the n-type νMOS transistor 509, respectively. The source of the n-type νMOS transistor 509 is connected to the drain of the load transistor 510, and its drain is connected to the power supply terminal 511. The source of the load transistor 510 is grounded, and its gate is connected to the control signal line 512. The source of the n-type νMOS transistor 509 is connected to one input portion of the comparator 513. A threshold voltage Vref is applied to the other input portion of the comparator 513, and its output signal is connected to the auxiliary light control signal line 514.

  With the configuration as described above, the source potential of the n-type νMOS transistor becomes equal to the average luminance signal of a predetermined number of pixels in all the focus detection areas A1 to A5. Then, by comparing this signal with the threshold voltage Vref by the comparator 512, the amount of auxiliary light emitted can be controlled by the output signal of the comparator 512.

  According to the third embodiment, since the role of the νMOS transistor is distributed for each color signal, the degree of freedom in design is increased and the design of the νMOS transistor is facilitated. In the third embodiment, the exposure amount of the auxiliary light is controlled based on the weighted average value of the pixels in the focus detection area. However, it is not always necessary to correspond to the focus detection area. For example, as shown in FIG. Of course, it can be selected. In the first to third embodiments, the weighted average weight is changed only to obtain the luminance signal Y. However, the gate of the n-type MOS transistor reduces the pixel output weight from the center of the screen to the periphery. You may make it adjust the magnitude | size of an electrode. By doing so, center-weighted metering can be easily performed.

1 is a block diagram illustrating an overall configuration of Embodiment 1 of an imaging apparatus according to the present invention. It is a block diagram which shows the structure of the image pick-up element in Example 1 shown in FIG. It is a circuit block diagram which shows the structure of the unit pixel which comprises the imaging area of the image pick-up element shown in FIG. FIG. 3 is a circuit configuration diagram showing a configuration of a pixel signal weighted average circuit added to the image sensor shown in FIG. 2. It is a figure which shows the structure of the color filter of a Bayer arrangement | positioning arrange | positioned in the imaging surface front surface of the image pick-up element shown in FIG. It is a figure which shows the pixel position corresponding to the five autofocus area | regions of an imaging screen. 2 is a timing chart for explaining the overall operation flow of the first embodiment shown in FIG. 1; FIG. 10 is a diagram illustrating a configuration of a color filter having four types of filter segments arranged in front of an imaging surface of an imaging element in Embodiment 2. FIG. 10 is a circuit configuration diagram illustrating a configuration of a pixel signal weighted average circuit in Embodiment 3. It is a figure which shows the aspect of the other photometry area | region in an imaging screen.

Explanation of symbols

101 Lens system
102 Lens drive mechanism
103 Exposure control mechanism
104 Mechanical shutter
105 Image sensor
106 TG block
107 Preprocess circuit
108 A / D converter
109 Digital process circuit
109a Buffer memory
109b AF processing circuit
110 card interface
111 Memory card
112 LCD display
113 System controller
114 Operation switch
115 Lens driver
116 Auxiliary light emitter
117 Exposure control driver
118 AF mechanism
119 EEPROM
120 Communication interface
121 Shutter drive circuit
201 Imaging area
202 Vertical shift register
203 CDS circuit
204 Horizontal shift register
301 photodiode
302 Reset transistor
303, 303-1 to 303-27 Amplifying transistor
304 Row selection transistor
305 unit pixel
306 column signal line
307 line reset line
308 row selection line
309,309-1 to 309-27 Monitor signal line
310 Power supply wiring
401 n-type νMOS transistor
402 Load transistor
403-1 to 403-27 Load transistor
404 Gate control signal line
405 selection circuit
406 Selection signal line
407 Auxiliary light control signal line
501, 502, 503, 507, 509 n-type νMOS transistor
504, 505, 506, 508, 510 load transistors
511 Power supply terminal
512 Gate control signal line
513 Comparator
514 Auxiliary light control signal line
701 screen
702 Enlarged view of area A1

Claims (8)

An auxiliary light emitting unit for emitting auxiliary light to the subject;
A solid-state imaging device in which a large number of pixels are arranged in a matrix, and
A light emission amount control unit that detects non-destructively the pixel potential according to the amount of light received by the solid-state imaging device, and controls the light emission amount of the auxiliary light based on the non-destructive potential detected;
An imaging apparatus comprising:   The light emission amount control unit detects potentials of a plurality of pixels of the solid-state imaging device in a non-destructive manner, and controls the light emission amount of the auxiliary light based on a weighted average value of the potentials detected in the non-destructive manner. An imaging apparatus according to claim 1.   The solid-state imaging device includes a color filter in which green (G), red (R), and blue (B) filter segments are regularly arranged on the imaging surface of the solid-state imaging device, and the light emission amount control unit includes: The pixel potential corresponding to the R (red), G (green), and B (blue) filter segments is detected non-destructively, and a luminance signal is generated based on a weighted average value of the non-destructed potential detected. The imaging apparatus according to claim 1, wherein a light emission amount of the auxiliary light is controlled based on the luminance signal.   The solid-state imaging device includes a color filter in which green (G), red (R), blue (B), and colorless (W) filter segments are regularly arranged on the imaging surface, and the light emission amount control unit includes: 2. The light emission amount of the auxiliary light is controlled based on a non-destructive detection of a potential of a pixel corresponding to the colorless (W) filter segment, and based on the non-destructive detection potential. Imaging device.   The light emission amount control unit detects a potential of a pixel in a subject area (focus area) that is a target of autofocus among pixels of the solid-state imaging device, and based on the potential detected in the nondestructive manner, The imaging apparatus according to claim 1, wherein the light emission amount of the auxiliary light is controlled.   The imaging apparatus can detect the focus of a subject in a plurality of focus areas, and the light emission amount control unit nondestructively calculates the weighted average value for each partial region of the solid-state imaging device corresponding to each focus area. The imaging apparatus according to claim 5, wherein the light emission amount of the auxiliary light is controlled based on a weighted average value of the potential detected in a non-destructive manner.   The light emission amount control unit detects a potential of a pixel of the solid-state imaging element nondestructively by a source follower circuit, and controls the light emission amount of the auxiliary light based on the potential detected nondestructively. The imaging device according to claim 1.   The light emission amount control unit detects the non-destructive potentials of a plurality of pixels in a predetermined partial area of the solid-state imaging device, and receives the non-destructive potentials of the plurality of pixels at an input unit of the νMOS transistor to perform weighting. The imaging apparatus according to claim 1, wherein an average value is calculated, and a light emission amount of the auxiliary light is controlled based on the weighted average value.

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