JP2008135606A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008135606A
JP2008135606A JP2006321323A JP2006321323A JP2008135606A JP 2008135606 A JP2008135606 A JP 2008135606A JP 2006321323 A JP2006321323 A JP 2006321323A JP 2006321323 A JP2006321323 A JP 2006321323A JP 2008135606 A JP2008135606 A JP 2008135606A
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semiconductor
die pad
semiconductor chip
semiconductor chips
adhesive
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Inventor
Kazuyuki Misumi
和幸 三角
Tetsuya Matsuura
哲也 松浦
Naotsugu Yasuda
直世 安田
Akira Yamazaki
暁 山崎
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
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  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device that prevents exfoliation and the occurrence of cracks. <P>SOLUTION: The semiconductor device has a first semiconductor chip mounted on a die pad via a first adhesive, a second semiconductor chip mounted on the die pad via a second adhesive while being arranged so as to make its one side face and one side face of the first semiconductor chip face each other across a through hole, a wire connecting between the first/second semiconductor chips, and a transfer mold resin. A distance between the first and the second semiconductor chips is less than or equal to 1 mm. The first and second adhesives respectively exist immediately under each edge of the side faces, facing each other, of the first and second semiconductor chips. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、ダイパッド上に２つの半導体チップを並べて搭載し、トランスファーモールドを行った半導体装置に関し、特に、剥離及びクラックの発生を防止することができる半導体装置に関するものである。   The present invention relates to a semiconductor device in which two semiconductor chips are mounted side by side on a die pad and subjected to transfer molding, and more particularly to a semiconductor device that can prevent peeling and cracks from occurring.

ダイパッド上に２つの半導体チップを並べて搭載し、トランスファーモールドを行ったマルチチップパッケージ（半導体装置）が提案されている（例えば、特許文献１参照）。図７は、このような従来の半導体装置を示す上面図であり、図８は、図７のＣ−Ｃ´における断面図である。   There has been proposed a multichip package (semiconductor device) in which two semiconductor chips are mounted side by side on a die pad and subjected to transfer molding (see, for example, Patent Document 1). FIG. 7 is a top view showing such a conventional semiconductor device, and FIG. 8 is a cross-sectional view taken along the line CC 'in FIG.

図示のように、ダイパッド１１にスルーホール１２が設けられている。そして、半導体チップ１３は、ダイパッド１１上に接着剤１４を介して搭載されている。また、半導体チップ１５は、ダイパッド１１上に接着剤１６を介して搭載され、スルーホール１２を挟んで半導体チップ１３と互いの一側面が対向するように配置されている。そして、半導体チップ１３と半導体チップ１５は、金ワイヤ１７により接続されている。また、半導体チップ１３，１５は金ワイヤ１８，１９によりそれぞれリード２０，２１に接続されている。これらのダイパッド１１、半導体チップ１３，１５及び金ワイヤ１７〜１９は樹脂２２により封止されている。   As shown, a through hole 12 is provided in the die pad 11. The semiconductor chip 13 is mounted on the die pad 11 via an adhesive 14. Further, the semiconductor chip 15 is mounted on the die pad 11 via an adhesive 16 and is disposed so that one side surface of the semiconductor chip 13 faces each other across the through hole 12. The semiconductor chip 13 and the semiconductor chip 15 are connected by a gold wire 17. The semiconductor chips 13 and 15 are connected to leads 20 and 21 by gold wires 18 and 19, respectively. These die pad 11, semiconductor chips 13 and 15, and gold wires 17 to 19 are sealed with resin 22.

ここで、半導体チップ１３，１５の熱膨張係数は約３ｐｐｍ／Ｋ、接着剤１４，１６の熱膨張係数は数十ｐｐｍ／Ｋ、ダイパッド１１の熱膨張係数は１３〜１５ｐｐｍ／Ｋである。このように各部材の熱膨張係数が異なることで、リフロー加熱時において応力集中点が発生する。   Here, the thermal expansion coefficient of the semiconductor chips 13 and 15 is about 3 ppm / K, the thermal expansion coefficient of the adhesives 14 and 16 is several tens of ppm / K, and the thermal expansion coefficient of the die pad 11 is 13 to 15 ppm / K. As described above, since the coefficients of thermal expansion of the members are different, stress concentration points are generated during reflow heating.

特開２００５−３０３２２２号公報JP-A-2005-303222

金ワイヤ１７に用いられる金の値段が上がっている。そこで、発明者は、半導体チップ１３，１５を１ｍｍ以下に近づけて金ワイヤ１７を短くすることで、製造コストを削減することを検討した。しかし、この半導体装置において、リフロー加熱によって剥離及びクラックが生じるという問題が発生した。この剥離及びクラックは以下のメカニズムにより生じたと推定される。   The price of gold used for the gold wire 17 is rising. Therefore, the inventor considered reducing the manufacturing cost by shortening the gold wire 17 by bringing the semiconductor chips 13 and 15 closer to 1 mm or less. However, this semiconductor device has a problem that peeling and cracking occur due to reflow heating. This peeling and cracking is presumed to have been caused by the following mechanism.

半導体チップ１３，１５間が狭くなることで、半導体チップ１３，１５間の空間への樹脂２２の注入圧力が落ちる。従って、この空間において、樹脂２２の密度が上がりずらく、接着力が落ちる。さらに、半導体チップ１３，１５が接着剤１４，１６に対してオーバーハングし、かつスルーホール１２の幅が狭い場合、半導体チップ１３，１５とダイパッド１１との間に樹脂２２が注入され切れず、隙間ができる。これにより、図９に示すように、ダイパッド１１と樹脂２２との界面で剥離が生じる。そして、半田実装時などの熱ストレスにより、樹脂内に溜まった水分が気化しようとして、内部の圧力が上昇すると、接着力の低い界面、もしくは、隙間が形成された部分を起点とする剥離を促進する。さらに、ダイパッド１１と接着剤１４，１６との界面にも剥離が進行する。その後、図１０に示すように、剥離が進展し、スルーホール１２内においてクラックが発生する。   By narrowing the space between the semiconductor chips 13 and 15, the injection pressure of the resin 22 into the space between the semiconductor chips 13 and 15 decreases. Therefore, in this space, the density of the resin 22 is difficult to increase and the adhesive force is reduced. Further, when the semiconductor chips 13 and 15 overhang with respect to the adhesives 14 and 16 and the width of the through hole 12 is narrow, the resin 22 is not completely injected between the semiconductor chips 13 and 15 and the die pad 11, There is a gap. As a result, as shown in FIG. 9, peeling occurs at the interface between the die pad 11 and the resin 22. Then, when the internal pressure rises due to the heat accumulated in the resin due to thermal stress during solder mounting, etc., it promotes peeling starting from the interface where the adhesive strength is low or where the gap is formed To do. Further, peeling also proceeds at the interface between the die pad 11 and the adhesives 14 and 16. Thereafter, as shown in FIG. 10, the separation progresses and a crack is generated in the through hole 12.

本発明は、上述のような課題を解決するためになされたもので、その目的は、剥離及びクラックの発生を防止することができる半導体装置を得るものである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device capable of preventing the occurrence of peeling and cracking.

本発明の一実施例に係る半導体装置は、ダイパッド上に第１の接着剤を介して搭載された第１の半導体チップと、ダイパッド上に第２の接着剤を介して搭載され、スルーホールを挟んで第１の半導体チップと互いの一側面が対向するように配置した第２の半導体チップと、第１の半導体チップと第２の半導体チップとを接続するワイヤと、トランスファーモールド樹脂とを有する。そして、第１，２の半導体チップ間の距離は１ｍｍ以下であり、第１，２の半導体チップの互いに対向する側面のエッジ直下に、それぞれ第１，２の接着剤が存在する。   A semiconductor device according to an embodiment of the present invention includes a first semiconductor chip mounted on a die pad via a first adhesive, and a second semiconductor chip mounted on the die pad via a first adhesive. A first semiconductor chip sandwiched between the second semiconductor chip disposed so that one side faces each other, a wire connecting the first semiconductor chip and the second semiconductor chip, and a transfer mold resin . The distance between the first and second semiconductor chips is 1 mm or less, and the first and second adhesives exist directly under the edges of the side surfaces of the first and second semiconductor chips that face each other.

この実施例によれば、剥離及びクラックの発生を防止することができる。   According to this embodiment, peeling and cracking can be prevented.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す上面図であり、図２は、図１のＡ−Ａ´における断面図である。図示のように、ダイパッド１１にスルーホール１２が設けられている。そして、半導体チップ１３（第１の半導体チップ）は、ダイパッド１１上に接着剤１４（第１の接着剤）を介して搭載されている。また、半導体チップ１５（第２の半導体チップ）は、ダイパッド１１上に接着剤１６（第２の接着剤）を介して搭載され、スルーホール１２を挟んで半導体チップ１３と互いの一側面が対向するように配置されている。そして、半導体チップ１３と半導体チップ１５は、金ワイヤ１７により接続されている。また、半導体チップ１３，１５は金ワイヤ１８，１９によりそれぞれリード２０，２１に接続されている。これらのダイパッド１１、半導体チップ１３，１５及び金ワイヤ１７〜１９は樹脂２２（トランスファーモールド樹脂）により封止されている。 Embodiment 1 FIG.
FIG. 1 is a top view showing a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. As shown, a through hole 12 is provided in the die pad 11. The semiconductor chip 13 (first semiconductor chip) is mounted on the die pad 11 via an adhesive 14 (first adhesive). Further, the semiconductor chip 15 (second semiconductor chip) is mounted on the die pad 11 via an adhesive 16 (second adhesive), and the semiconductor chip 13 and one side face each other with the through hole 12 interposed therebetween. Are arranged to be. The semiconductor chip 13 and the semiconductor chip 15 are connected by a gold wire 17. The semiconductor chips 13 and 15 are connected to leads 20 and 21 by gold wires 18 and 19, respectively. These die pad 11, semiconductor chips 13, 15 and gold wires 17-19 are sealed with resin 22 (transfer mold resin).

図３は、図２の点線で囲った要部を拡大した断面図である。図示のように、半導体チップ１３，１５間の距離は０．６６ｍｍ、即ち１ｍｍ以下である。また、スルーホール１２の幅は０．２ｍｍ、接着剤１４，１６の端からスルーホール１２までの距離は０．２ｍｍである。そして、半導体チップ１３，１５の厚みは０．３ｍｍ、接着剤１４，１６の厚みは０．０２５ｍｍ、ダイパッド１１の厚みは０．１２５ｍｍである。   FIG. 3 is an enlarged cross-sectional view of a main part surrounded by a dotted line in FIG. As shown in the figure, the distance between the semiconductor chips 13 and 15 is 0.66 mm, that is, 1 mm or less. The width of the through hole 12 is 0.2 mm, and the distance from the ends of the adhesives 14 and 16 to the through hole 12 is 0.2 mm. The semiconductor chips 13 and 15 have a thickness of 0.3 mm, the adhesives 14 and 16 have a thickness of 0.025 mm, and the die pad 11 has a thickness of 0.125 mm.

また、本実施の形態では、半導体チップ１３，１５の互いに対向する側面のエッジ直下に、それぞれ接着剤１４，１６が存在する。これにより、半導体チップ１３，１５とダイパッド１１との間に樹脂２２が注入され切れずに隙間ができることはない。ただし、半導体チップ１３，１５が接着剤１４，１６に対してオーバーハングしていなくても、半導体チップ１３，１５間の距離が１ｍｍ以下になることで、半導体チップ１３，１５間の空間への樹脂２２の注入圧力が落ちる。従って、この空間において、樹脂２２の密度が上がりずらく、吸湿率が上がり、接着力が落ちる。これに対して、本実施の形態では、接着剤１４，１６は、それぞれ半導体チップ１３，１５の互いに対向する側面のエッジ直下から０．０３５ｍｍだけはみ出している。これにより、半導体チップ１３，１５のエッジ近傍の応力集中点において接着力の低下を防ぐことができる。従って、剥離及びクラックの発生を防止することができる。   Further, in the present embodiment, the adhesives 14 and 16 are present immediately below the edges of the side surfaces of the semiconductor chips 13 and 15 facing each other. As a result, the resin 22 is not injected between the semiconductor chips 13 and 15 and the die pad 11, and no gap is formed. However, even if the semiconductor chips 13 and 15 are not overhanging the adhesives 14 and 16, the distance between the semiconductor chips 13 and 15 is 1 mm or less, so that the space between the semiconductor chips 13 and 15 is reduced. The injection pressure of the resin 22 drops. Therefore, in this space, the density of the resin 22 is difficult to increase, the moisture absorption rate is increased, and the adhesive force is decreased. On the other hand, in the present embodiment, the adhesives 14 and 16 protrude by 0.035 mm from directly below the edges of the side surfaces of the semiconductor chips 13 and 15 facing each other. Thereby, it is possible to prevent the adhesive force from being lowered at the stress concentration points near the edges of the semiconductor chips 13 and 15. Accordingly, peeling and cracking can be prevented.

また、金ワイヤ１７が半導体チップ１３，１５の互いに対向する側面のエッジの上方に存在する。これにより、半導体チップ１３，１５間の空間に上方から樹脂２２が入り難くなる。この場合、本実施の形態が更に有効となる。   Further, the gold wire 17 exists above the edges of the side surfaces of the semiconductor chips 13 and 15 that face each other. This makes it difficult for the resin 22 to enter the space between the semiconductor chips 13 and 15 from above. In this case, the present embodiment is further effective.

実施の形態２．
図４は、本発明の実施の形態２に係る半導体装置を示す上面図であり、図５は図４のＢ−Ｂ´における断面図である。また、図６は、図５の点線で囲った要部を拡大した断面図である。図示のように、スルーホール１２の幅は１．２ｍｍであり、半導体チップ１３，１５間の距離０．６６ｍｍよりも広い。ただし、半導体チップ１３，１５が接着剤１４，１６に対して０．２ｍｍだけオーバーハングしている。その他の構成は実施の形態１と同様である。 Embodiment 2. FIG.
4 is a top view showing a semiconductor device according to the second embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line BB ′ of FIG. FIG. 6 is an enlarged cross-sectional view of a main part surrounded by a dotted line in FIG. As shown in the drawing, the width of the through hole 12 is 1.2 mm, which is wider than the distance 0.66 mm between the semiconductor chips 13 and 15. However, the semiconductor chips 13 and 15 overhang by 0.2 mm with respect to the adhesives 14 and 16. Other configurations are the same as those of the first embodiment.

このようにスルーホール１２の幅を広くすることで、スルーホール１２を通して半導体チップ１３，１５間の空間へ樹脂２２が入り易くなる。また、当該空間へ下側から樹脂２２が入り易くなるため、金ワイヤ１７が半導体チップ１３，１５の互いに対向する側面のエッジの上方に存在する場合でも有効である。これにより、半導体チップ１３，１５とダイパッド１１との間に樹脂２２が注入され切れずに隙間ができるのを防ぐことができる。また、半導体チップ１３，１５間の空間において樹脂２２の密度が上昇するため、接着力を確保することができ、透湿率及び吸湿容量を低下させることができる。さらに、半導体チップ１３，１５とダイパッド１１との間の空間において、接着力が強いＳｉ−樹脂界面が、接着力が弱い金属―樹脂界面よりも広くなっている。従って、剥離及びクラックの発生を防止することができる。   By widening the through hole 12 in this way, the resin 22 can easily enter the space between the semiconductor chips 13 and 15 through the through hole 12. In addition, since the resin 22 can easily enter the space from below, it is effective even when the gold wire 17 exists above the edges of the side surfaces of the semiconductor chips 13 and 15 facing each other. As a result, it is possible to prevent the resin 22 from being injected between the semiconductor chips 13 and 15 and the die pad 11 without forming a gap. In addition, since the density of the resin 22 increases in the space between the semiconductor chips 13 and 15, it is possible to secure an adhesive force and to reduce the moisture permeability and the moisture absorption capacity. Further, in the space between the semiconductor chips 13 and 15 and the die pad 11, the Si-resin interface having a strong adhesive force is wider than the metal-resin interface having a weak adhesive force. Accordingly, peeling and cracking can be prevented.

本発明の実施の形態１に係る半導体装置を示す上面図である。It is a top view which shows the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 1 of this invention. 図２の点線で囲った要部を拡大した断面図である。It is sectional drawing to which the principal part enclosed with the dotted line of FIG. 2 was expanded. 本発明の実施の形態２に係る半導体装置を示す上面図である。It is a top view which shows the semiconductor device which concerns on Embodiment 2 of this invention. 本発明の実施の形態２に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 2 of this invention. 図５の点線で囲った要部を拡大した断面図である。It is sectional drawing to which the principal part enclosed with the dotted line of FIG. 5 was expanded. 従来の半導体装置を示す上面図である。It is a top view which shows the conventional semiconductor device. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device. 従来の半導体装置を示す断面図である。It is sectional drawing which shows the conventional semiconductor device.

符号の説明Explanation of symbols

１１ ダイパッド
１２ スルーホール
１３ 半導体チップ（第１の半導体チップ）
１４ 接着剤（第１の接着剤）
１５ 半導体チップ（第２の半導体チップ）
１６ 接着剤（第２の接着剤）
１７ 金ワイヤ（ワイヤ）
２２ 樹脂（トランスファーモールド樹脂） 11 Die pad 12 Through hole 13 Semiconductor chip (first semiconductor chip)
14 Adhesive (first adhesive)
15 Semiconductor chip (second semiconductor chip)
16 Adhesive (second adhesive)
17 Gold wire (wire)
22 Resin (transfer mold resin)

Claims (4)

スルーホールが設けられたダイパッドと、
前記ダイパッド上に第１の接着剤を介して搭載された第１の半導体チップと、
前記ダイパッド上に第２の接着剤を介して搭載され、前記スルーホールを挟んで前記第１の半導体チップと互いの一側面が対向するように配置した第２の半導体チップと、
前記第１の半導体チップと前記第２の半導体チップとを接続するワイヤと、
前記ダイパッド、前記第１，２の半導体チップ及び前記ワイヤを封止するトランスファーモールド樹脂とを有し、
前記第１，２の半導体チップ間の距離は１ｍｍ以下であり、
前記第１，２の半導体チップの互いに対向する側面のエッジ直下に、それぞれ前記第１，２の接着剤が存在することを特徴とする半導体装置。 A die pad with a through hole;
A first semiconductor chip mounted on the die pad via a first adhesive;
A second semiconductor chip mounted on the die pad via a second adhesive, and disposed so that one side surface of the first semiconductor chip faces each other across the through hole;
A wire connecting the first semiconductor chip and the second semiconductor chip;
A transfer mold resin for sealing the die pad, the first and second semiconductor chips, and the wire;
The distance between the first and second semiconductor chips is 1 mm or less,
2. The semiconductor device according to claim 1, wherein the first and second adhesives exist respectively immediately below the edges of the side surfaces facing each other of the first and second semiconductor chips. 前記第１，２の接着剤は、それぞれ前記第１，２の半導体チップの互いに対向する側面のエッジ直下からはみ出していることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the first and second adhesives protrude from directly under edges of side surfaces of the first and second semiconductor chips facing each other. スルーホールが設けられたダイパッドと、
前記ダイパッド上に第１の接着剤を介して搭載された第１の半導体チップと、
前記ダイパッド上に第２の接着剤を介して搭載され、前記スルーホールを挟んで前記第１の半導体チップと互いの一側面が対向するように配置した第２の半導体チップと、
前記第１の半導体チップと前記第２の半導体チップとを接続するワイヤと、
前記ダイパッド、前記第１，２の半導体チップ及び前記ワイヤを封止するトランスファーモールド樹脂とを有し、
前記第１，２の半導体チップ間の距離は１ｍｍ以下であり、
前記スルーホールの幅は、前記第１，２の半導体チップ間の距離よりも広いことを特徴とする半導体装置。 A die pad with a through hole;
A first semiconductor chip mounted on the die pad via a first adhesive;
A second semiconductor chip mounted on the die pad via a second adhesive, and disposed so that one side surface of the first semiconductor chip faces each other across the through hole;
A wire connecting the first semiconductor chip and the second semiconductor chip;
A transfer mold resin for sealing the die pad, the first and second semiconductor chips, and the wire;
The distance between the first and second semiconductor chips is 1 mm or less,
The width of the through hole is wider than the distance between the first and second semiconductor chips. 前記ワイヤは、前記第１，２の半導体チップの互いに対向する側面のエッジの上方に存在することを特徴とする請求項１〜３の何れか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the wire exists above edges of side surfaces of the first and second semiconductor chips facing each other. 5.
JP2006321323A 2006-11-29 2006-11-29 Semiconductor device Pending JP2008135606A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3343607A1 (en) * 2016-12-28 2018-07-04 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
JP2020013711A (en) * 2018-07-19 2020-01-23 トヨタ自動車株式会社 Manufacturing method of series-stacked all-solid-state battery

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3343607A1 (en) * 2016-12-28 2018-07-04 Renesas Electronics Corporation Semiconductor device and manufacturing method thereof
US10643930B2 (en) 2016-12-28 2020-05-05 Renesas Electronics Corporation Semiconductor device with semiconductor chips of different sizes and manufacturing method threreof
JP2020013711A (en) * 2018-07-19 2020-01-23 トヨタ自動車株式会社 Manufacturing method of series-stacked all-solid-state battery
JP7040331B2 (en) 2018-07-19 2022-03-23 トヨタ自動車株式会社 Manufacturing method of series-stacked all-solid-state battery

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