JP2008130761A - Semiconductor device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control the conductivity type and threshold value of a semiconductor device which uses a carbon nanotube in a channel portion. <P>SOLUTION: The semiconductor device comprises a carbon nanotube 6 which will serve for a channel, a source electrode 3 and a drain electrode 4 connected to both ends of the carbon nanotube 6, respectively, a gate insulation film 5 so disposed as to be in contact with a middle part of the carbon nanotube 6, and a gate electrode 7 disposed on the carbon nanotube 6 via the gate insulation film 5. In a region between the gate insulation film 5 and the source electrode 3 and in a region between the gate insulation film 5 and the drain electrode 4, the carbon nanotube 6 is in contact with an insulation film 11 consisting of a material different from that of the gate insulation film 5. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using a carbon nanotube or an organic semiconductor in a channel portion and a manufacturing method thereof.

  In a conventional semiconductor device, a film formed by using a semiconductor substrate, a CVD (Chemical Vapor Deposition) method, or a PVD (Physical Vapor Deposition) method has been used for a channel portion of a field effect transistor. On the other hand, a film formed by a method such as printing / coating is also being used in recent years.

  A manufacturing method of a transistor having a channel portion using a printing / coating method is performed in the following steps. For example, referring to FIG. 13, (1) an insulating film 102 is formed on the substrate 101. Note that in the case where the substrate 101 is insulative, the substrate 101 can be used as it is. (2) A channel material 106 to be a channel portion is printed and applied. (3) Electrodes 103 and 104 to be source / drain are formed. (4) A gate insulating film 105 is formed. (5) The gate electrode 107 is formed. As another method, one formed in the order of (1) → (5) → (4) → (2) → (3) is also possible (see FIG. 14). Thereafter, a protective film or the like is formed. The above is the most basic process configuration.

  Here, any channel material can be used as long as it can be modulated by a gate voltage. When manufacturing by printing / coating, fine semiconductor powders or organic substances dissolved in a solvent are used. When not limited to printing / coating methods, ordinary bulk semiconductors such as silicon and gallium arsenide are used. It is done. In recent years, a material using a carbon nanotube as a channel material has been disclosed (see, for example, Patent Documents 1 to 3).

  A general transistor using a carbon nanotube in the channel portion will be described. Referring to FIG. 13, an insulating film 102 is formed on a substrate 101, and carbon nanotubes 106 that become channel portions are formed in predetermined regions on the insulating film 102. The material of the substrate 101 is not so important, and it is sufficient that the source and drain are not short-circuited by the insulating film 102. Therefore, the substrate 101 is not limited to a silicon oxide film, and a plastic or the like can be used as long as it has a wide insulating property. A source electrode 103 and a drain electrode 104 are formed at both ends of the carbon nanotube 106. A gate insulating film 105 is formed on the central portion of the carbon nanotube 106, and a gate electrode 107 is formed on the gate insulating film 105. As the gate insulating film 105, a silicon oxide film or a silicon nitride film is generally used. The gate electrode 107 and the carbon nanotube 106 constitute a capacitor (capacitor) through the gate insulating film 105. The voltage (or potential or potential) of a part of the channel portion can be changed by the voltage of the gate electrode 107. By changing the potential of the channel portion, the charge concentration or the barrier in the channel can be changed. Thus, the amount of current in the channel is controlled by the gate voltage. In FIG. 13, there is an extension portion 110 that is not covered with the gate insulating film 105 on the channel and is not capacitively coupled to the gate electrode 107.

  By the way, many of the printing / coating-type field effect transistors are turned on without applying a gate voltage. This is because the conductivity types of the channel portion and the source / drain portions are not controlled.

  In a general field effect transistor using silicon or the like for the channel portion, the source-channel-drain is usually n-pn for the n-channel type and pnp for the p-channel type. It modulates by doping the conductivity type like this. By doing so, even when no gate voltage is applied, the channel portion has a conductivity type complementary to that of the source and drain, and this acts as a barrier and no current flows. For this reason, it is turned off when no gate voltage is applied.

  The above field effect transistors are generally called depletion type transistors. On the other hand, there is a so-called enhancement type, in which the barrier is intentionally reduced by doping the channel portion in the same type as the source / drain. Therefore, the enhancement type transistor is turned on even when no gate voltage is applied.

JP 2003-17508 A JP 2006-222279 A JP 2006-245127 A

  However, in the printing / coating type, the electrode is basically formed as it is after the channel material is applied. Even when the channel portion is doped, the entire channel portion is doped. Therefore, since the conductivity type is not controlled in the conventional field effect transistor, there is a problem that the gate voltage (threshold value) for turning on cannot be controlled even though the conductivity type of the entire channel can be controlled.

  The main subject of this invention is providing the semiconductor device which can control a conductivity type and a threshold value.

  In a first aspect of the present invention, in a semiconductor device, a channel, a source electrode and a drain electrode connected to both ends of the channel, and a gate insulating film disposed so as to contact an intermediate portion of the channel A gate electrode disposed above or below the channel via the gate insulating film, and the channel includes a region between the gate insulating film and the source electrode, and the gate insulating film And the first insulating film made of a material different from that of the gate insulating film in all or part of each region between the drain electrode and the drain electrode.

  In the semiconductor device of the present invention, the material used for the channel is preferably a carbon nanotube.

  In the semiconductor device of the present invention, it is preferable that the carbon nanotube is configured to connect the source electrode to the drain electrode in a single line.

  In the semiconductor device of the present invention, it is preferable that the carbon nanotubes are configured such that a plurality of carbon nanotubes shorter than the distance between the source electrode and the drain electrode are overlapped and connected.

  In the semiconductor device of the present invention, the material used for the channel is preferably an organic semiconductor.

  In the semiconductor device of the present invention, it is preferable that the gate insulating film is a silicon oxide film, and the first insulating film is a silicon nitride film.

  In the semiconductor device of the present invention, it is preferable that the gate insulating film is a silicon nitride film, and the first insulating film is a silicon oxide film.

  In the semiconductor device of the present invention, the entire outer peripheral surface of the region of the channel where the gate insulating film is disposed is covered with the gate insulating film and an insulating film made of the same material as the gate insulating film. It is preferable.

  In the semiconductor device of the present invention, the entire outer peripheral surface of the region of the channel in which the first insulating film is disposed is the first insulating film and an insulating film made of the same material as the first insulating film. It is preferable that it is covered with.

  In the semiconductor device of the present invention, it is preferable that the gate electrode is disposed under the channel via the gate insulating film and is made of the same material as the source electrode and the drain electrode.

  In the semiconductor device of the present invention, a second channel made of a material similar to that of the channel and a second source electrode made of a material different from the source electrode and the drain electrode are connected to both ends of the second channel. And a second drain electrode, a second gate insulating film made of the same material as the first insulating film, and disposed above or below the second channel. And a second gate electrode disposed via the second gate insulating film, wherein the second channel is a region between the second gate insulating film and the second source electrode, and The gate insulating film is disposed on all or a part of each region between the second gate insulating film and the second drain electrode, and is made of the same material as the gate insulating film, and is in contact with the second insulating film, in front The second source electrode, the drain electrode and is electrically connected, the second gate electrode is preferably electrically connected to the gate electrode.

  According to a second aspect of the present invention, in a method for manufacturing a semiconductor device, a step of forming a channel on a substrate, a step of forming a source electrode and a drain electrode at both ends of the channel, Forming a first insulating film in the vicinity of the source electrode and the drain electrode excluding the central portion; forming a gate insulating film on the channel and in the central portion; and a gate electrode on the gate insulating film Forming the step.

  In a third aspect of the present invention, in a method for manufacturing a semiconductor device, a step of forming a channel on a substrate, a step of forming a source electrode and a drain electrode at both ends of the channel, Forming a gate insulating film in a central portion; a first insulating film on the channel and in a region between the gate insulating film and the source electrode; and a region between the gate insulating film and the drain electrode And a step of forming a gate electrode on the gate insulating film.

  According to a fourth aspect of the present invention, in a method for manufacturing a semiconductor device, a step of forming a source electrode and a drain electrode on a substrate; and a region on the substrate between the source electrode and the drain electrode. Forming a channel connected to the source electrode and the drain electrode; forming a first insulating film on the channel and in a region between the source electrode and the drain electrode; and a center on the channel Selectively removing a portion of the first insulating film, forming a gate insulating film in a central portion on the channel, and forming a gate electrode on the gate insulating film. Features.

  According to a fifth aspect of the present invention, in a method for manufacturing a semiconductor device, a step of forming a source electrode and a drain electrode on a substrate, and a region on the substrate between the source electrode and the drain electrode are formed. Forming a channel connected to the source electrode and the drain electrode; forming a gate insulating film on the channel and in a region between the source electrode and the drain electrode; and the source electrode and the drain Selectively removing the gate insulating film in the vicinity of an electrode; forming a first insulating film in the vicinity of the source electrode and the drain electrode on the channel; and forming a gate electrode on the gate insulating film. And a step of forming.

  According to a sixth aspect of the present invention, in a method for manufacturing a semiconductor device, a step of forming a source electrode, a drain electrode, and a gate electrode on a substrate, a step of forming a gate insulating film covering the gate electrode, and the gate Forming a channel connected to the source electrode and the drain electrode in a region between the source electrode and the drain electrode on a substrate including the insulating film; and forming a first insulating film on the channel. And a process.

  In a seventh aspect of the present invention, in a method for manufacturing a semiconductor device, a step of forming a first channel and a second channel on a substrate, and a first source electrode and a first drain electrode at both ends of the first channel Forming a second source electrode and a second drain electrode on both ends of the second channel, the first source electrode on the first channel and excluding a central portion, and the first Forming a first insulating film in the vicinity of the drain electrode and simultaneously forming a second gate insulating film on the second channel and in the central portion; and a first gate insulating film on the first channel and in the central portion. Forming a second insulating film on the second channel and in the vicinity of the second source electrode and the second drain electrode, except for a central portion, and forming a film on the first gate insulating film at the same time as forming a film; 1 Forming a gate electrode, characterized in that it comprises a step of forming a second gate electrode over the second gate insulating film.

  According to the present invention, the following effects can be obtained.

  First, since the conductivity type of the channel portion is modulated by modulating the insulating film, the threshold value can be controlled. Therefore, since the transistor can be in an off state, that is, a current does not flow when no gate voltage is applied (the gate voltage is zero), power consumption in an integrated circuit manufactured by printing / coating can be reduced.

  Secondly, since it is possible to control the conductivity type at the same time as forming the protective film without introducing a separate doping process, the manufacturing process can be shortened and the manufacturing cost can be reduced.

(Embodiment 1)
A semiconductor device according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Embodiment 1 of the present invention.

  The semiconductor device according to the first embodiment is a semiconductor device using a carbon nanotube or an organic semiconductor in a channel portion, and is used for, for example, an arithmetic circuit and a memory circuit.

  In the semiconductor device, an insulating film 2 is formed on a substrate 1, and carbon nanotubes 6 serving as channel portions are formed in predetermined regions on the insulating film 2. A source electrode 3 and a drain electrode 4 are formed at both ends of the carbon nanotube 6. A gate insulating film 5 is formed on the central portion of the carbon nanotube 6, and a gate electrode 7 is formed on the gate insulating film 5. The gate electrode 7 and the carbon nanotube 6 constitute a capacitor (capacitor) through the gate insulating film 5. An insulating film 11 is formed on the extension portion 10 on the channel that is not covered with the gate insulating film 5 and is not capacitively coupled to the gate electrode 7.

  The substrate 1 may be made of any material as long as the source and drain are not short-circuited by the insulating film 2. If the insulating property is wide and good, a silicon oxide film, plastic, or the like can be used. As the substrate 1, for example, an insulating substrate such as silicon oxide, silicon nitride, aluminum oxide, titanium oxide, calcium fluoride, acrylic resin, epoxy resin, polyimide, Teflon (registered trademark), silicon, germanium, gallium arsenide, nitride A semiconductor substrate such as gallium, zinc oxide, indium phosphide, or silicon carbide can be used. The surface of the substrate 1 is preferably flat. In addition, the board | substrate 1 may be used individually by 1 type, and may use 2 or more types together by arbitrary combinations and a ratio.

  The insulating film 2 is an insulating film for preventing a short circuit between the source and the drain. The insulating film 2 can be omitted if the insulating property is secured in the substrate 1.

  The source electrode 3 and the drain electrode 4 are electrodes made of a conductor formed in contact with both end portions of the carbon nanotube 6 serving as a channel portion. The material of the source electrode 3 and the drain electrode 4 is selected according to the conductivity type of the channel. For example, gold (Au) can be used for a p-type channel, and aluminum is used for an n-type channel. be able to. The source electrode 3 and the drain electrode 4 need only be thick enough not to be disconnected. In general, if it is thicker than 10 nm, a continuous film is guaranteed. The width of the source electrode 3 and the drain electrode 4 (the width in the left-right direction in FIG. 1) is, for example, 0.6 μm (microns). A distance between the source electrode 3 and the drain electrode 4 (a distance referred to as a channel length) is, for example, 1 μm (micron).

  The gate insulating film 5 is an insulating film disposed on the central portion of the carbon nanotube 6 serving as a channel portion and immediately below the gate electrode 7. The gate insulating film 5 needs to have no leakage current and to have an effective field effect. As the insulating film with a small leakage current, for example, a silicon oxide film, a silicon nitride film, a parylene (exactly polyparaxylylene) film, a polyimide film, an HSQ (hydrogensilsesquioxane) film, an SOG (spin on glass) film, or the like is used. be able to. In order to make the field effect effective, it is necessary to make the thickness of the gate insulating film 5 smaller than the channel length. In general, a technique called a short channel effect that prevents a decrease can be used. At a minimum, the thickness of the gate insulating film 5 needs to be smaller than 1/10 of the channel length. For example, for a channel length of 1 μm, the film thickness of the gate insulating film 5 is desirably 100 nm or less. The gate insulating film 5 is desirably formed so as to cover the outer peripheral surface of the carbon nanotube 6.

  The carbon nanotube 6 is a channel material formed in the channel portion between the source and the drain, and is a portion where carriers (electrons or holes) of the transistor flow. As the carbon nanotubes 6, for example, those grown by the CVD method can be used. The carbon nanotubes 6 may be connected with a single source and drain. A plurality of carbon nanotubes 6 shorter than the distance between the source and the drain may be overlapped and connected. An organic material may be used in place of the carbon nanotube 6. The channel length is adjusted according to the form of the carbon nanotube 6. When the source and the drain are connected by a single carbon nanotube 6 grown from a catalyst by the CVD method, it is necessary to make it shorter than the length of the carbon nanotube 6. On the other hand, in the case where the source and the drain are connected through a plurality of carbon nanotubes 6 manufactured by printing or coating, it is desirable to make the length longer than the average length of the carbon nanotubes. The carbon nanotube 6 is covered with the gate insulating film 5 in the outer peripheral surface of the central portion except for the lower portion. In the carbon nanotube 6, a portion of the outer peripheral surface of the extension portion 10 excluding the lower portion is covered with an insulating film 11.

  The gate electrode 7 is a conductor formed on the central portion of the gate insulating film 5. As the gate electrode 7, for example, a layer in which gold of 50 nm (nanometers) is stacked on aluminum is used. The gate electrode 7 may be thick enough not to be disconnected. Generally, if it is thicker than 10 nm, a continuous film is guaranteed. The gate length is, for example, 0.8 μm (micron).

  The insulating film 11 is formed in both the region between the gate insulating film 5 and the source electrode 3 on the carbon nanotube 6 to be the channel portion and the region between the gate insulating film 5 and the drain electrode 4 (extension portion 10). It is the formed insulating film. As the insulating film 11, for example, a silicon oxide film is used. The thickness of the insulating film 11 is, for example, 8 nm (nanometer).

In the structure of the semiconductor device as described above, although there is a slight variation depending on the element, the current (drain current) flowing through the channel when the source-drain voltage is 0.1 V and the gate voltage is 0 V is 10 ^{−. 14} to 10 ⁻¹⁰ A. Further, when the gate voltage is set to −2 V, the drain current is 10 ⁻⁷ to 10 ⁻⁴ A. In the conventional element structure in which the gate insulating film 5 and the insulating film 11 are made of the same silicon oxide film, the drain current does not become 10 ⁻¹⁰ or less unless the gate voltage is set to + 2V. That is, the drain current when the gate voltage is 0V is the same digit as the drain current when the gate voltage is -2V.

  By the way, it is known that when a silicon oxide film is used as the gate insulating film 5, the carbon nanotube 6 operates as a p-type channel, and when a silicon nitride film is used as the gate insulating film 5, it operates as an n-type channel. . In consideration of this, the insulating film on the carbon nanotube 6 is divided into a gate insulating film 5 and an insulating film 11, and a silicon nitride film having an action of making the conductivity type of the carbon nanotube 6 n-type is formed on the gate insulating film 5. In addition, by using a silicon oxide film having the effect of making the conductivity type of the carbon nanotubes 6 p-type for the insulating film 11 of the extension portion 10, the gate voltage is 0V and the drain current is greatly increased as in the above example. Can be suppressed.

  Further, by using aluminum having a small work function as the gate electrode 7 and using gold, which is easy to inject holes (having a large work function) as the electrode, as the source electrode 3 and the drain electrode 4, The operation can be emphasized. That is, only the region under the gate electrode 7 in the channel is n-type, and the other region is p-type. This is because in a state where no gate voltage is applied, the conduction type only under the gate electrode 7 is inverted from the other conduction types, and a state in which a barrier for current exists is realized.

  As described above, in the first embodiment, it is important to cover the insulating film 11 of the extension portion 10 with an insulating film made of a material different from that of the gate insulating film 5. That is, the insulating film 11 is selected to have a conductivity type complementary to the conductivity type of the carbon nanotube 6 determined by the gate insulating film 5. For example, the gate insulating film 5 is a silicon nitride film and the insulating film 11 is a silicon oxide film. By doing so, it becomes a pnp-type conduction type. Thus, the conductivity type of the channel portion is controlled.

  For example, when manufacturing an n-type channel transistor, it is desirable to select a material for the source electrode 3 and the drain electrode 4 that can easily inject electrons into the carbon nanotubes 6 such as aluminum. Specifically, the source electrode 3 and the drain electrode 4 may be made of a material having a small work function such as calcium in addition to aluminum. In general, many metals having a low work function are unstable in the atmosphere. In that case, it is preferable to cover the metal with a metal that is stable in the atmosphere.

  Further, when manufacturing a p-type channel transistor, it is desirable to select a material for the source electrode 3 and the drain electrode 4 that can easily inject holes into the carbon nanotubes 6 like gold. Specifically, the source electrode 3 and the drain electrode 4 can be made of a material having a large work function such as palladium in addition to gold.

  Next, the operation of the semiconductor device according to Embodiment 1 of the present invention will be described. The voltage (or potential or potential) of a part of the channel is changed by the voltage of the gate electrode 7. By changing the potential of the channel portion, the charge concentration or barrier in the channel changes. Thus, the amount of current in the channel is controlled by the gate voltage.

  Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a process cross-sectional view schematically showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

  First, after the insulating film 2 is formed on the substrate 1, the carbon nanotubes 6 are formed in a predetermined region on the insulating film 2 (step A1; see FIG. 2A). Here, the carbon nanotube 6 can be formed by, for example, a CVD method. In the CVD method, a catalyst is disposed in a predetermined region on the insulating film 2 and then the carbon nanotubes 6 are grown under a methane gas atmosphere serving as a carbon material under a temperature of about 800 ° C. The growth time is about 10 minutes. As the catalyst, iron having a thickness of 0.6 nm formed on an aluminum film having a thickness of 8 nm is used. In FIG. 2, the structure of the catalyst is omitted. Further, the formation of the carbon nanotube 6 is preferably performed before the formation of the source electrode 3 and the drain electrode 4 because the CVD growth temperature is as high as 400 ° C. or higher.

  Next, the source electrode 3 and the drain electrode 4 are formed on both ends of the carbon nanotube 6 (step A2; see FIG. 2B). Here, the source electrode 3 and the drain electrode 4 are formed by, for example, forming a PMMA resist patterned by electron beam exposure, forming a metal such as gold by vapor deposition, and then removing unnecessary portions by lift-off. Can be formed. As another method of forming the source electrode 3 and the drain electrode 4, a technique generally used in a normal method for manufacturing a semiconductor device can be used. As an example, first, after forming a metal film on the entire surface of the insulating film 2 including the carbon nanotubes 6, a resist pattern is formed using lithography, and etching is performed using the resist pattern as a mask. Furthermore, as another method, it is possible to use a method in which a conductive organic substance or the like is converted into ink and printed.

  Next, an insulating film 11 is formed on the extension portion 10 of the carbon nanotube 6 (step A3; see FIG. 2C). Here, the insulating film 11 can be formed by, for example, an atmospheric pressure thermal CVD method using silane gas and oxygen gas. The carbon nanotubes 6 are preferably formed at a relatively low temperature of about 370 ° C. because defects are introduced or burnt at a high temperature and in an oxygen atmosphere. The film formation time is about 30 seconds. For film formation at a low temperature, temperature uniformity is important, and the reaction tube is sufficiently preheated. Thereafter, a pattern is formed at a place where the gate insulating film 5 is to be formed by electron beam exposure, and the portion is removed with buffered hydrofluoric acid. In addition to the above, the insulating film 11 may be formed by using a vapor deposition method, a thermal vapor deposition method, a method of heating and activating and depositing an organic insulating film, which are generally used as a manufacturing method. it can.

  Next, the gate insulating film 5 is formed on the central portion of the carbon nanotube 6 (step A4; see FIG. 2D). Here, the gate insulating film 5 can be, for example, a silicon nitride film formed by sputtering. In this case, silicon nitride is used for the target, and argon gas is used for the plasma gas. In order to improve the film quality, it is desirable to introduce nitrogen at a flow rate of 20 sccm at the same time. The pressure is about 2 Pa. In addition to the above, the gate insulating film 5 is formed by a vapor deposition method, a thermal vapor deposition method, a method of heating / activating and depositing an organic insulating film, which are generally used as a manufacturing method. Can do.

  Next, a gate electrode 7 is formed in a predetermined region on the gate insulating film 5 (step A5; see FIG. 2E). Here, the gate electrode 7 can be formed by a method similar to the formation of the source electrode 3 and the drain electrode 4. For example, first, aluminum is electron beam evaporated, and then gold is electron beam evaporated continuously. Thereafter, although not shown in the drawing, pad electrodes for connection are formed. The reason why the gold is deposited on the gate electrode 7 is that the surface is oxidized when the aluminum is exposed, and an unintended resistance component is prevented from entering when the pad electrode is connected.

  Thereafter, an interlayer insulating film, a via, and a wiring are formed.

  According to the first embodiment, the following effects can be obtained.

  First, since the threshold value is controlled and the transistor is in an off state, that is, a current does not flow when the gate voltage is not applied (the gate voltage is zero), the integration made by printing / coating is possible. Power consumption in the circuit can be reduced.

  Second, a protective film can be formed without introducing a doping process, and the channel conductivity type can be controlled, so that the manufacturing process can be shortened and the manufacturing cost can be reduced. .

  Although Embodiment 1 does not include a doping step only for changing the conductivity type of the channel material, doping is performed when the threshold value is finely adjusted. For example, when the insulating film 11 is formed so as to have a pnp conductivity type, fullerene (C60), p-chloranil (tetrachloro-p-benzoquinone; Tetrachloro-p- benzo quinine), TCNQ (7,7,8,8-tetriaquinodimethane; 7,7,8,8-Tetracyano quinodimethane), DDQ (2,3-Dichloro-5,6-dicyano-p-benzo quinine) ), F4TCNQ (Tetrafluorotetracyano-p-quinodimethane), C60F36 (Fluorofllerene), and the like are adsorbed on the surface. On the other hand, n-type parts include TTF (Tetrathiafulvalene), TMTSF (Tetramethyltetraselenafulvalene), TMPD (N, N, N ′, N′-Tetramethyl-p-phenylenediamine), TDAE (Tetrakis (dimethylamino) ethylene), decamethylnickelocene (Bis (pentamethylcyclopentadienyl) nickel) Adsorbs on the surface a material with high ionization potential such as potassium and cesium. The adsorption process is performed before the insulating film 11 and the gate insulating film 5 are formed. Adsorption is performed by immersing in a saturated solution of the doping material for several tens of seconds to one hour, or by depositing the doping material.

(Embodiment 2)
A semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 3 is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to Embodiment 2 of the present invention.

  The semiconductor device according to the second embodiment is different from the first embodiment in that an insulating film 5 a and an insulating film 11 a are also added between the carbon nanotube 6 and the insulating film 2. Other configurations are the same as those of the first embodiment.

  The carbon nanotube 6 is a channel material formed in the channel portion between the source and the drain, and is a portion where carriers (electrons or holes) of the transistor flow. As the carbon nanotubes 6, for example, those grown by the CVD method can be used. The carbon nanotubes 6 may be connected with a single source and drain. A plurality of carbon nanotubes 6 shorter than the distance between the source and the drain may be overlapped and connected. An organic material may be used in place of the carbon nanotube 6. The channel length is adjusted according to the form of the carbon nanotube 6. When the source and drain are connected by a single carbon nanotube 6 grown from a catalyst by the CVD method, the channel length needs to be shorter than the length of the carbon nanotube 6. On the other hand, when the source and the drain are connected via a plurality of carbon nanotubes 6 manufactured by printing or coating, the channel length is desirably longer than the average length of the carbon nanotubes.

  In the carbon nanotube 6, the lower part of the outer peripheral surface of the central part is covered with the insulating film 5a, and the other part is covered with the gate insulating film 5b. The insulating film 5a is made of the same material as the gate insulating film 5b (the same material as the gate insulating film 5 of the first embodiment; for example, a silicon nitride film). The carbon nanotube 6 has a lower portion covered with an insulating film 11a and an outer portion of the outer peripheral surface of the extension portion 10 covered with an insulating film 11b. The insulating film 11a is made of the same material as the insulating film 11b (the same material as the insulating film 11 of the first embodiment; for example, a silicon oxide film).

  According to the second embodiment, the central portion of the carbon nanotube 6 and the entire outer periphery of the extension portion 10 are covered with the same material, so that the channel conductivity type can be controlled more than in the first embodiment.

(Embodiment 3)
A semiconductor device according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 4 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Embodiment 3 of the present invention.

  In the semiconductor device according to the third embodiment, insulating films 11 a and 11 b are covered on a part of the extension portion 10 on the outer peripheral surface of the carbon nanotube 6. Other configurations are the same as those of the second embodiment. On the outer peripheral surface of the carbon nanotube 6 of FIG. 4, the portions of the extension portion 10 that are not covered with the insulating films 11a and 11b are made of a material different from the materials of the insulating film 5a, the gate insulating film 5b, and the insulating films 11a and 11b. The insulating films 12a and 12b are covered. Note that the insulating films 12a and 12b may not be formed depending on the structure of the element.

  Here, in FIG. 4, when a silicon nitride film is used for the insulating film 5a and the gate insulating film 5b, a silicon oxide film is used for the insulating films 11a and 11b, and aluminum is used for the source electrode 3 and the drain electrode 4, It is expected that the drain current will generally decrease. This is because the carbon nanotubes 6 of the extension portion 10 are p-type while the source electrode 3 is a material that easily injects electrons.

In FIG. 4, the materials of the insulating film 5a, the gate insulating film 5b, and the insulating films 11a and 11b are exchanged, that is, a silicon oxide film is used for the insulating film 5a and the gate insulating film 5b, and a silicon nitride film is used for the insulating films 11a and 11b. Is used, the source electrode 3 and the drain electrode 4 are made of aluminum and the gate electrode 7 is made of gold. A very thin titanium film (thickness 0.5 nm) for improving adhesion is interposed under the gold. Although there are slight variations in the elements depending on this structure, the current flowing through the channel (referred to as the drain current) with the source-drain voltage of 0.1 V and the gate voltage of 0 V applied is 10 ⁻¹⁴ to 10 ^−. Characteristics in the range of ¹¹ A are obtained. Further, when the gate voltage is swept to +2 V, the drain current becomes 10 ⁻⁸ to 10 ⁻⁶ .

  According to the third embodiment, the same effects as those of the second embodiment are obtained.

(Embodiment 4)
A semiconductor device according to Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 5 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Embodiment 4 of the present invention.

  The semiconductor device according to the fourth embodiment is an example in which carbon nanotubes 6 are applied, and the source electrode 3 and the drain electrode 4 are formed before the carbon nanotubes 6. Other configurations are the same as those of the first embodiment.

  In the semiconductor device, an insulating film 2 is formed on a substrate 1, and a source electrode 3 and a drain electrode 4 are formed in a predetermined region on the insulating film 2. A carbon nanotube 6 serving as a channel portion is formed in a region between the source electrode 3 and the drain electrode 4. Both end portions of the carbon nanotube 6 are also formed on part of the source electrode 3 and the drain electrode 4. The carbon nanotubes 6 are connected by overlapping a plurality of carbon nanotubes 6 shorter than the distance between the source and the drain. A gate insulating film 5 is formed at the center of the carbon nanotube 6, and a gate electrode 7 is formed on the gate insulating film 5. The gap between the carbon nanotubes 6 is filled with the gate insulating film 5. Only the gate insulating film 5 is disposed between the upper end portion of the carbon nanotube 6 and the bottom surface of the gate electrode 7. The gate electrode 7 and the carbon nanotube 6 constitute a capacitor (capacitor) through the gate insulating film 5. An insulating film 11 is formed on the extension portion 10 on the channel that is not covered with the gate insulating film 5 and is not capacitively coupled to the gate electrode 7. The gap between the carbon nanotubes 6 is filled with the insulating film 11. Only the insulating film 11 is disposed on the upper part from the upper end of the carbon nanotube 6.

  Next, the manufacturing method of the semiconductor device concerning Embodiment 4 of the present invention is explained using a drawing. 6 and 7 are process cross-sectional views schematically showing a method for manufacturing a semiconductor device according to Embodiment 4 of the present invention.

  First, after the insulating film 2 is formed on the substrate 1, the source electrode 3 and the drain electrode 4 are formed in predetermined regions on the insulating film 2 (step B1; see FIG. 6A). Here, the source electrode 3 and the drain electrode 4 are formed by, for example, forming a PMMA resist patterned by electron beam exposure, forming a metal such as gold by vapor deposition, and then removing unnecessary portions by lift-off. Can be formed. In this case, the thickness of the source electrode 3 and the drain electrode 4 is about 50 nm. In this case, in order to improve the adhesion between the source electrode 3 and the drain electrode 4 and the insulating film 2 as a base, it is preferable to insert a titanium film of about 1 nm. In this case, the channel length is 5 to 300 μm. Since the channel length is long and the element size is large, the metal thickness of the source electrode 3 and the drain electrode 4 is slightly increased in order to ensure that the wire is not disconnected over a long distance.

  Next, carbon nanotubes 6 serving as channel portions are disposed in a region including a part on the source electrode 3 and the drain electrode 4 and a region between the source electrode 3 and the drain electrode 4 (step B2; FIG. 6). (See (B)). Here, the carbon nanotubes 6 are disposed by spin-coating carbon nanotubes 6 which are synthesized by laser evaporation and dissolved in dichloroethane. If the spin coating is performed, the carbon nanotubes are also dispersed in unnecessary portions, causing an unintended short circuit, so that the unnecessary portions are removed. For this purpose, first, a LOR (lift off resist) layer and a PMMA (poly-methyl methacrylate) layer are laminated, a PMMA layer is patterned by an electron beam exposure method, and then the pattern is transferred to the LOR layer. The carbon nanotubes 6 are spin-coated thereon and dispersed. Thereafter, unnecessary carbon nanotubes are removed for each LOR with TMAH (Tetra-Methyl-Ammonium-Hydroxide). In addition to this method, a method using lithography and etching, a method using printing, and the like can be used as in the manufacturing method in (1) above.

  Next, the insulating film 11 is formed over the entire channel portion of the carbon nanotube 6 (step B3; see FIG. 6C). Here, the insulating film 11 is formed by sputtering using a silicon oxide film, for example. A film can be formed under the same conditions as the sputtering method used in step A4. The thickness of the insulating film 11 is about 100 nm. The insulating film 11 is thick because the carbon nanotubes 6 are dispersed by coating, and therefore the thickness of the carbon nanotubes 6 is several tens of nanometers and needs to be covered.

  Next, a window is formed in the central portion of the insulating film 11 (region where the gate insulating film (5 in FIG. 7B) is formed) while leaving the carbon nanotubes 6 (step B4; see FIG. 7A). ). Here, in the formation of this window, a mask pattern is formed by an electron beam exposure method, and a window for forming the gate insulating film 5 is opened with buffered hydrofluoric acid. In addition, etching can be performed using a liquid or a gas. It is necessary that the carbon nanotubes 6 are not damaged during the etching.

  Next, the gate insulating film 5 is formed in the window portion of the insulating film 11 (step B5; see FIG. 7B). Here, the gate insulating film 5 can be formed, for example, using a silicon nitride film by a sputtering method (same conditions as in step A4). The thickness of the gate insulating film 5 is about 10 nm.

  Next, a gate electrode 7 is formed in a predetermined region on the gate insulating film 5 (step B6; see FIG. 7C). Here, the gate electrode 7 can be formed by, for example, continuous electron beam evaporation of aluminum and gold. The thickness of aluminum and gold is 50 nm respectively.

  Thereafter, an interlayer insulating film, a via, and a wiring are formed.

  According to the fourth embodiment, the same effects as those of the first embodiment are obtained.

(Embodiment 5)
A semiconductor device according to Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 8 is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to Embodiment 5 of the present invention.

  The semiconductor device according to Embodiment 5 is an example in which the gate electrode 7 is below the carbon nanotube 6, and the source electrode 3, the drain electrode 4, and the gate electrode 7 are formed simultaneously. Other configurations are the same as those of the first embodiment.

  In the semiconductor device, an insulating film 2 is formed on a substrate 1, and a source electrode 3, a drain electrode 4, and a gate electrode 7 are formed in a predetermined region on the insulating film 2. The upper surface or side surface of the gate electrode 7 is covered with the gate insulating film 5. A carbon nanotube 6 serving as a channel portion is formed in a region between the source electrode 3 and the drain electrode 4. Both end portions of the carbon nanotube 6 are also formed on part of the source electrode 3 and the drain electrode 4. A central portion of the carbon nanotube 6 is formed on the gate insulating film 5. The carbon nanotubes 6 are connected by overlapping a plurality of carbon nanotubes 6 shorter than the distance between the source and the drain. An insulating film 11 is formed on the entire element portion. The gap between the carbon nanotubes 6 is filled with the insulating film 11, and the insulating film 11 is also formed in the extension portion 10. The gate electrode 7 and the carbon nanotube 6 constitute a capacitor (capacitor) through the gate insulating film 5. Only the insulating film 11 is disposed on the upper part from the upper end of the carbon nanotube 6.

  Next, the manufacturing method of the semiconductor device concerning Embodiment 5 of the present invention is explained using a drawing. FIG. 9 is a process cross-sectional view schematically showing the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.

  First, after the insulating film 2 is formed on the substrate 1, the gate electrode 7, the source electrode 3, and the drain electrode 4 are formed in predetermined regions on the insulating film 2 (step C1; see FIG. 9A). Here, the thickness of the gate electrode 7, the source electrode 3, and the drain electrode 4 is about 50 nm, and the material is all gold for simplicity. Although not shown in FIG. 9, the pad electrode is formed after this.

  Next, the gate insulating film 5 is formed on the upper surface or the side surface of the gate electrode 7 (step C2; see FIG. 9B). Here, the gate insulating film 5 can be formed, for example, by forming a silicon nitride film using a sputtering method. A laminated film of LOR (lift off resist) and PMMA (poly-methyl methacrylate) is previously formed by patterning using an electron beam exposure method, and the rest is removed by leaving only the vicinity of the gate electrode by lift-off. The thickness of the gate insulating film 5 is about 20 nm.

  Next, carbon nanotubes 6 serving as channel portions are disposed in a part on the source electrode 3 and the drain electrode 4, a region between the source electrode 3 and the drain electrode 4, and a region including the gate insulating film 5. (Step C3; see FIG. 9C). The carbon nanotubes 6 are applied and dispersed in the same manner as in Step B2. Excess carbon nanotubes are removed.

  Next, the insulating film 11 is formed over the entire element portion (step C4; see FIG. 9D). Here, the insulating film 11 can be formed by sputtering using a silicon oxide film, for example. The thickness of the insulating film 11 is about 100 nm.

  Thereafter, an interlayer insulating film, a via, and a wiring are formed.

  According to the fifth embodiment, the same effects as those of the first embodiment can be obtained, and the gate electrode 7 can be formed simultaneously with the source electrode 3 and the drain electrode 4, thereby reducing the number of steps.

(Embodiment 6)
A semiconductor device according to Embodiment 6 of the present invention will be described with reference to the drawings. FIG. 10 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Embodiment 6 of the present invention.

  The semiconductor device according to Embodiment 6 is an example in which field effect transistors X and Y using carbon nanotubes in the channel portion are manufactured in a complementary manner. Here, the insulating film 2, the insulating film 11 of the field effect transistor X, and the gate insulating film 15 of the field effect transistor Y are silicon oxide films, the gate insulating film 5 of the field effect transistor X, and the insulating film 21 of the field effect transistor Y. Is a silicon nitride film. In this example, the drain electrode 4 of the field effect transistor X and the source electrode 13 of the field effect transistor Y are electrically connected via the via 23c, the wiring 24c, and the via 23d, and both the field effect transistors X, Y The gate electrodes 7 and 17 are electrically connected through a via 23b, a wiring 24b, a via 26a, a wiring 27, a via 26b, a wiring 24d, and a via 23e, and are similar to a so-called CMOS NOT gate in a silicon semiconductor device. It is a configuration. Other configurations are the same as those of the first embodiment.

  Next, the manufacturing method of the semiconductor device concerning Embodiment 6 of the present invention is explained using a drawing. FIG. 11 is a process cross-sectional view schematically showing a method for manufacturing a semiconductor device according to Embodiment 6 of the present invention.

  First, an insulating film 2 made of a thermal oxide film is formed on the substrate 1, and then carbon nanotubes 6 and 16 are formed in a predetermined region on the insulating film 2 (step D1; see FIG. 11A). Here, the carbon nanotubes 6 and 16 can be formed by, for example, a CVD method. In the CVD method, after a catalyst is disposed in a predetermined region on the insulating film 2, the carbon nanotubes 6 and 16 are grown under a methane gas atmosphere serving as a carbon material at a temperature of about 800 ° C. The growth time is about 10 minutes. As the catalyst, iron having a thickness of 0.6 nm formed on an aluminum film having a thickness of 8 nm is used. As the substrate 1, a silicon wafer is used. The film thickness of the insulating film 2 is about 100 nm.

  Next, source electrodes 3 and 13 and drain electrodes 4 and 14 are formed on both ends of the carbon nanotubes 6 and 16 (step D2; see FIG. 11B). Here, gold is used for the source electrode 3 and the drain electrode 4 of the field effect transistor X, and aluminum is used for the source electrode 13 and the drain electrode 14 of the field effect transistor Y. Therefore, after depositing a film on the PMMA resist patterned by electron beam exposure, the step of removing unnecessary portions by lift-off is performed in two steps. As another technique, a technique generally used in a normal method for manufacturing a semiconductor device can be used. As an example, there may be mentioned a method in which a metal film is first formed on the entire surface of the insulating film 2 including the carbon nanotubes 6 and 16, a resist pattern is then formed using lithography, and etching is performed using the resist pattern as a mask. it can. In the case of aluminum, this method is more common in the manufacture of semiconductor devices such as silicon. Furthermore, as another method, it is possible to use a method in which a conductive organic substance or the like is converted into an ink and printed.

  Next, the insulating film 11 of the field effect transistor X and the gate insulating film 15 of the field effect transistor Y are formed (step D3; see FIG. 11C). Here, the insulating film 11 and the gate insulating film 15 are formed simultaneously. The insulating film 11 and the gate insulating film 15 can be formed by, for example, an atmospheric pressure thermal CVD method using silane gas and oxygen gas. The carbon nanotubes 6 and 16 are formed at a relatively low temperature of 370 ° C. because defects are introduced or burnt in an oxygen atmosphere at a high temperature. The film formation time is about 30 seconds. For film formation at a low temperature, temperature uniformity is important, and the reaction tube is sufficiently preheated. After that, a place where the gate insulating film 5 of the field effect transistor X and the insulating film 21 of the field effect transistor Y are to be formed is patterned by electron beam exposure, and the portions are removed with buffered hydrofluoric acid.

  Next, the gate insulating film 5 of the field effect transistor X and the insulating film 21 of the field effect transistor Y are formed (step D4; see FIG. 11D). Here, the gate insulating film 5 and the insulating film 21 are formed at the same time, and are sputtered silicon nitride films. The target is silicon nitride and the plasma gas is argon gas. In order to improve the film quality, 20 sccm of nitrogen is also introduced at the same time. The pressure is 2 Pa. In addition to the above, the gate insulating film 5 and the insulating film 21 may be formed by vapor deposition, thermal vapor deposition, and a method of heating and activating and depositing an organic insulating film, which are generally used as manufacturing methods. Can be used.

  Next, gate electrodes 7 and 17 are formed in predetermined regions on the gate insulating films 5 and 15 (step D5; see FIG. 11E). Here, the formation of the gate electrodes 7 and 17 is the same as the formation of the source electrodes 3 and 13 and the drain electrodes 4 and 14. A laminated film of aluminum and gold is used for the gate electrode 7 of the field effect transistor X, and thinly deposited titanium and gold are used for the gate electrode 17 of the field effect transistor Y. The thickness of the gate electrodes 7 and 17 is about 100 nm. In each field effect transistor, the metal used for the gate electrodes 7 and 17 is different, so that pattern formation and vapor deposition are performed in two steps. For example, in the gate electrode 7 of the field effect transistor X, after pattern formation by an electron beam exposure method, aluminum is electron beam evaporated, and gold is continuously electron beam evaporated. Thereafter, unnecessary portions are removed by lift-off. Through the same process, titanium and gold are successively deposited on the gate electrode 17 of the field effect transistor Y. Similarly, a lift-off is performed, and thereafter pad electrodes for connection are formed. The reason why the gate electrode 7 of the field effect transistor X is vapor-deposited is to prevent an unintended resistance component from entering when the surface is oxidized when the aluminum is exposed and the pad electrode is connected.

  Thereafter, interlayer insulating films 22 and 25, vias 23a to 23f, 26a to 26b, and wirings 24a to 24e and 27 are formed (see FIG. 10).

  According to the sixth embodiment, the same effect as that of the first embodiment can be obtained, and standby power can be significantly reduced.

(Embodiment 7)
A semiconductor device according to Embodiment 7 of the present invention will be described with reference to the drawings. FIG. 12 is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to the seventh embodiment of the present invention.

  The semiconductor device according to the seventh embodiment is an example in which another material is used for the insulating film 32 corresponding to the insulating film of the sixth embodiment (2 in FIG. 10). Further, the channel materials 36 and 46 of the semiconductor device according to the seventh embodiment are not limited to carbon nanotubes. Any organic semiconductor can be used for the channel materials 36 and 46 as long as the conductivity type can be changed in combination with the insulating film 32. For example, polythiophene can also be used for the channel materials 36 and 46. Pendant polymer materials having a low molecular skeleton in the side chain, for example, fullerenes such as pentacene, C60, and C70, phthalocyanine derivatives, and triphenylamine derivatives such as α-NPD can also be used. Note that the channel materials 36 and 46 are not limited to these semiconductor materials. Other configurations are the same as those of the sixth embodiment.

  According to the seventh embodiment, the same effects as in the sixth embodiment can be obtained, and the channel materials 36 and 46 can be selected according to the insulating film 32.

It is the fragmentary sectional view which showed typically the structure of the semiconductor device which concerns on Embodiment 1 of this invention. It is process sectional drawing which showed typically the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. It is the fragmentary sectional view which showed typically the structure of the semiconductor device which concerns on Embodiment 2 of this invention. It is the fragmentary sectional view which showed typically the structure of the semiconductor device which concerns on Embodiment 3 of this invention. It is the fragmentary sectional view which showed typically the structure of the semiconductor device which concerns on Embodiment 4 of this invention. It is the 1st process sectional view showing typically the manufacturing method of the semiconductor device concerning Embodiment 4 of the present invention. It is 2nd process sectional drawing which showed typically the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. It is the fragmentary sectional view which showed typically the structure of the semiconductor device which concerns on Embodiment 5 of this invention. It is process sectional drawing which showed typically the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention. It is the fragmentary sectional view which showed typically the structure of the semiconductor device which concerns on Embodiment 6 of this invention. It is process sectional drawing which showed typically the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention. It is the fragmentary sectional view which showed typically the structure of the semiconductor device which concerns on Embodiment 7 of this invention. 10 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Conventional Example 1. FIG. 10 is a partial cross-sectional view schematically showing a configuration of a semiconductor device according to Conventional Example 2. FIG.

Explanation of symbols

1, 101, 201 Substrate 2, 102, 202 Insulating film 3, 13, 103, 203 Source electrode 4, 14, 104, 204 Drain electrode 5, 15, 5b, 105, 205 Gate insulating film 5a Insulating film 6, 16 Carbon Nanotubes 7, 17, 107, 207 Gate electrodes 10, 110, 210 Extension portions 11, 11a, 11b, 21 Insulating films 12, 12a, 12b Insulating films 15 Gate insulating films 21 Insulating films 22 Interlayer insulating films 23a-23f Vias 24a- 24e wiring 25 interlayer insulating film 26a, 26b via 27 wiring 32 insulating film 36, 46 channel material 106, 206 channel material (carbon nanotube)

Claims (17)

Channel,
A source electrode and a drain electrode connected to both ends of the channel;
A gate insulating film disposed in contact with an intermediate portion of the channel;
A gate electrode disposed above or below the channel via the gate insulating film;
With
The channel is different from the gate insulating film in all or part of a region between the gate insulating film and the source electrode and a region between the gate insulating film and the drain electrode. A semiconductor device in contact with a first insulating film made of a material.   The semiconductor device according to claim 1, wherein a material used for the channel is a carbon nanotube.   The semiconductor device according to claim 2, wherein the carbon nanotube is configured so as to connect the source electrode and the drain electrode by a single line.   3. The semiconductor device according to claim 2, wherein the carbon nanotubes are configured such that a plurality of carbon nanotubes shorter than a distance between the source electrode and the drain electrode are overlapped and connected.   The semiconductor device according to claim 1, wherein a material used for the channel is an organic semiconductor. The gate insulating film is a silicon oxide film,
The semiconductor device according to claim 1, wherein the first insulating film is a silicon nitride film. The gate insulating film is a silicon nitride film,
The semiconductor device according to claim 1, wherein the first insulating film is a silicon oxide film.   The entire outer peripheral surface of the region of the channel where the gate insulating film is disposed is covered with the gate insulating film and an insulating film made of the same material as the gate insulating film. Item 8. The semiconductor device according to any one of Items 1 to 7.   The entire outer peripheral surface of the channel in which the first insulating film is disposed is covered with the first insulating film and an insulating film made of the same material as the first insulating film. A semiconductor device according to any one of claims 1 to 7.   2. The semiconductor device according to claim 1, wherein the gate electrode is disposed under the channel via the gate insulating film and is made of a material similar to that of the source electrode and the drain electrode. A second channel made of the same material as the channel;
A second source electrode connected to both ends of the second channel and made of a material different from the source electrode and the drain electrode; a second drain electrode;
A second gate insulating film made of a material similar to that of the first insulating film and disposed in contact with an intermediate portion of the second channel;
A second gate electrode disposed above or below the second channel via the second gate insulating film;
With
The second channel includes all or part of a region between the second gate insulating film and the second source electrode and a region between the second gate insulating film and the second drain electrode. And made of the same material as the gate insulating film, in contact with the second insulating film,
The second source electrode is electrically connected to the drain electrode;
The semiconductor device according to claim 1, wherein the second gate electrode is electrically connected to the gate electrode. Forming a channel on the substrate;
Forming a source electrode and a drain electrode at both ends of the channel;
Forming a first insulating film on the channel and in the vicinity of the source electrode and the drain electrode excluding a central portion;
Forming a gate insulating film on a central portion of the channel;
Forming a gate electrode on the gate insulating film;
A method for manufacturing a semiconductor device, comprising: Forming a channel on the substrate;
Forming a source electrode and a drain electrode at both ends of the channel;
Forming a gate insulating film on a central portion of the channel;
Forming a first insulating film on the channel and in a region between the gate insulating film and the source electrode and a region between the gate insulating film and the drain electrode;
Forming a gate electrode on the gate insulating film;
A method for manufacturing a semiconductor device, comprising: Forming a source electrode and a drain electrode on a substrate;
Forming a channel connected to the source electrode and the drain electrode in a region on the substrate and between the source electrode and the drain electrode;
Forming a first insulating film on the channel and in a region between the source electrode and the drain electrode;
Selectively removing the first insulating film in a central portion on the channel;
Forming a gate insulating film in a central portion on the channel;
Forming a gate electrode on the gate insulating film;
A method for manufacturing a semiconductor device, comprising: Forming a source electrode and a drain electrode on a substrate;
Forming a channel connected to the source electrode and the drain electrode in a region on the substrate and between the source electrode and the drain electrode;
Forming a gate insulating film on the channel and in a region between the source electrode and the drain electrode;
Selectively removing the gate insulating film in the vicinity of the source electrode and the drain electrode;
Forming a first insulating film in the vicinity of the source electrode and the drain electrode on the channel;
Forming a gate electrode on the gate insulating film;
A method for manufacturing a semiconductor device, comprising: Forming a source electrode, a drain electrode, and a gate electrode on a substrate;
Forming a gate insulating film covering the gate electrode;
Forming a channel connected to the source electrode and the drain electrode in a region between the source electrode and the drain electrode on the substrate including the gate insulating film;
Forming a first insulating film on the channel;
A method for manufacturing a semiconductor device, comprising: Forming a first channel and a second channel on a substrate;
Forming a first source electrode and a first drain electrode at both ends of the first channel;
Forming a second source electrode and a second drain electrode at both ends of the second channel;
A first insulating film is formed on the first channel and in the vicinity of the first source electrode and the first drain electrode excluding the central portion, and at the same time, a second gate insulating film is formed on the second channel and in the central portion. Forming a step;
A first gate insulating film is formed on the first channel and in a central portion, and at the same time, a second insulating film is formed on the second channel and in the vicinity of the second source electrode and the second drain electrode excluding the central portion. Forming a step;
Forming a first gate electrode on the first gate insulating film;
Forming a second gate electrode on the second gate insulating film;
A method for manufacturing a semiconductor device, comprising:

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