JP2008117110A - Function verification method and device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a function verification technique that is more effective in dispensing with test patterns and capable of more effectively reducing the time and cost required to verify functions regarding the design data of a semiconductor device. <P>SOLUTION: Function verification, which is carried out using a plurality of test patterns on the design data of a semiconductor device having a plurality of storage areas and a logic circuit, executes a classification process for comparing partial test patterns except writing process patterns and classifying them into predetermined groups of test patterns; an internal state storage process for specifying reading process patterns included in reference test patterns in each group of test patterns, and storing an internal state corresponding to each of the reading process patterns; an execution procedure setting process for setting, for each group of test patterns, the order of executing the test patterns based on the storage area where the process of reading the test patterns is carried out and on the content stored therein, and for selecting the internal state for use with each test pattern; and a function verification process for performing function verification using the internal state selected. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a function verification technique for design data of a semiconductor device having a plurality of storage areas and a logic circuit.

  Normally, semiconductor device design data (including circuit design data logically synthesized from the hardware description language) designed in a hardware description language such as HDL (Hardware Description Language) is designed according to specifications. Functional verification for confirming this is performed by simulation on a computer. For example, a test pattern is input to semiconductor device design data, a simulation is executed, and an output from the semiconductor device design data obtained as an execution result is compared with an expected value that is a correct output result of a semiconductor device prepared in advance. Then, when the output from the semiconductor device matches the expected value, it is confirmed that the design data of the semiconductor device is designed according to the specification. In recent years, items to be verified have increased along with the increase in the scale of the circuit of a semiconductor device to be designed. As a result, the test pattern length and the number of test patterns have increased. On the other hand, since the simulation is performed by a huge amount of computation on a computer, it is characterized in that it takes much time compared to actually operating the semiconductor device. That is, an increase in circuit scale, an increase in test pattern length, and the number of test patterns greatly increase the time required for the simulation, and the cost for verifying the function for the design data of the semiconductor device is a problem.

  As a technique for reducing such a simulation time, for example, for a plurality of test patterns, a common pattern is extracted by verifying a match / mismatch in order from the first cycle of the test pattern, and the simulation of the common pattern portion is appropriately omitted. Thus, there is a function verification technique for performing function verification on design data of a semiconductor device (see, for example, Patent Document 1). More specifically, this functional verification technology performs a simulation with one test pattern selected from a plurality of test patterns after extracting a common pattern, and the internal state of the semiconductor device in the final cycle of the common pattern in the simulation Remember. The internal state is, for example, the storage content of a storage unit such as a register constituting the semiconductor device, the storage content of a storage element such as a latch circuit used in a logic circuit constituting the semiconductor device, or the like. Then, at the time of executing a simulation using another test pattern, the stored internal state is used to set registers and memory elements that constitute the semiconductor device, and the simulation is started from the end time of the common pattern. That is, in the function verification technique described in Patent Document 1, in the simulation using a plurality of test patterns, the simulation time is reduced for the plurality of test patterns as a whole by omitting the simulation of the common pattern portion. Yes.

  Hereinafter, the function verification technique of Patent Document 1 will be described in detail with reference to FIGS. 19 and 20. Here, FIG. 19 shows a configuration example of a semiconductor device to which the function verification technique of Patent Document 1 is applied, and FIG. 20 shows a test pattern group (test pattern) for functional verification of the semiconductor device shown in FIG. TA, TB and TC) are schematically shown.

  Specifically, as illustrated in FIG. 19, the semiconductor device 300 includes a core block 301 including a logic circuit that realizes the main operation of the semiconductor device 300, and a plurality of registers that temporarily store various parameters of the circuit operation. And a ROM (Read Only Member) 303 that stores initial setting values and operation programs of the semiconductor device 300, and these are connected via a bus line 304. The core block 301 includes functional blocks FA to FC, and is configured to appropriately execute an access operation to the register block 302 and the ROM 303. Further, as shown in FIG. 20, the test pattern TA includes an “initialization pattern” for initializing the semiconductor device 300, a “ROM read pattern” for reading various values for initial setting, and an initial setting for each register. The register setting pattern α ”and the“ functional test pattern PA ”for verifying the functional block FA included in the semiconductor device are provided in this order. The test pattern TB includes “initialization pattern”, “ROM read pattern”, “register setting pattern α”, and “functional test pattern PB” for verifying the functional block FB included in the semiconductor device in this order. . The test pattern TC verifies the “initialization pattern”, “ROM read pattern”, “register setting pattern β” for initial setting different from the register setting pattern α for each register, and the functional block FC included in the semiconductor device. “Function test pattern PC” is provided in this order.

  In the function verification technique described in Patent Document 1, when performing function verification using the test pattern group, an “initialization pattern” and a “ROM read pattern” at times T1 to T4 between the test pattern TA and the test pattern TB. And “register setting pattern α” are common, and between the test pattern TA and the test pattern TC, the “initialization pattern” and the “ROM read pattern” at times T1 to T3 are common. At the time of simulation, the internal state of the semiconductor device 300 is stored at times T3 and T4. In the simulation using the test pattern TB, the internal state of the semiconductor device 300 at the time T4 stored during the simulation using the test pattern TA is read out, the internal state is set in the design data of the semiconductor device 300, and the simulation is restarted from the time T4. Similarly, in the simulation using the test pattern TC, the internal state of the semiconductor device 300 at the time T3 stored during the simulation using the test pattern TA is read, and this internal state is set in the design data of the semiconductor device 300, and the simulation is started from the time T3. Resume. That is, for the simulation by the test pattern TB, the simulation of the portion overlapping the test pattern TA from the time T1 to T3 can be omitted for the simulation by the times T1 to T4 and for the test pattern TC. It is possible to increase the efficiency of the used function verification.

JP 2006-155083 A

  However, since the function verification technique described in Patent Document 1 considers only the commonality from the beginning of the test pattern, in particular, for example, a test pattern is prepared for each function for a plurality of register settings, and the function verification is performed. When there is a difference between test patterns at a relatively early stage, for example, the test pattern cannot be omitted sufficiently, and the time and cost required for functional verification can be sufficiently reduced. There was a problem that I could not.

  Here, FIG. 21 shows a schematic configuration of 20 test patterns TA1 to TA10 and TB1 to TB10 for functional verification of the design data of the semiconductor device 300 shown in FIG. Specifically, the test patterns TA1 to TA10 are test patterns for performing functional verification on the functional block A constituting the core block 301, and are created for each register setting α, β, γ to σ. As shown in FIG. 21, in the test patterns TA1 to TA10, the “initialization pattern” at times T1 to T2, the “reading pattern of setting values from the ROM 303” at times T2 to T3, and the “function block FA at times T4 to T1000”. "Verification pattern for" is common. Test patterns TB1 to TB10 are test patterns for performing functional verification on the functional block B constituting the core block 301, and are created for each register setting α, δ, and ε to φ. As shown in FIG. 21, in the test patterns TB1 to TB10, the “initialization pattern” at the time T1 to T2, the “reading pattern of the set value from the ROM 303” at the time T2 to T3, and the “functional block FB at the time T4 to T1000”. "Verification pattern for" is common.

  When performing functional verification on the semiconductor device 300 using the test pattern group shown in FIG. 21, the functional verification technique described in Patent Document 1 omits simulation considering only the commonality from the beginning of each test pattern. Therefore, for example, in the test patterns TA2 to TA10, the register setting pattern at times T3 to T4 is different from that of the test pattern TA1, so that the simulation can be omitted for the common patterns from time T1 to T3. Similarly, the simulation from time T1 to time T4 can be omitted in the test pattern TB1, and the simulation from time T1 to time T3 can be omitted in the test patterns TB2 to TB10. However, the time from the beginning of the test pattern to the time T3 or T4 is slightly shorter than the length of the verification pattern for each functional block, that is, the time between time T4 and time T1000 (pattern end), and is omitted. The effect is considered to be small.

  Furthermore, in a semiconductor device provided with a plurality of storage areas and logic circuits, it is necessary to perform functional verification for each function and for each register setting. Therefore, due to the increase in circuit scale and circuit complexity in recent years, As the number of combinations of register settings increases, the number of test patterns increases dramatically. However, in the function verification technique described in Patent Document 1, as shown in FIG. 21, when a plurality of register settings are prepared for each function and the function verification is performed, the effect of omitting the simulation is small and the efficiency of the function verification is sufficient. Therefore, a function verification technique having a more effective omission effect for such a test pattern group is desired.

  The present invention has been made in view of the above-mentioned problems, and the object thereof is more effective in omitting test patterns, particularly in the case of using a plurality of test patterns in which differences occur only at a relatively early setting stage. Therefore, it is an object of the present invention to provide a function verification method that can effectively reduce the time and cost required for function verification of design data of a semiconductor device. Also, especially when using a plurality of test patterns that differ only at a relatively early setting stage, the test pattern omission effect is higher, and the time and cost required for functional verification of the design data of the semiconductor device are reduced. Provided is a function verification device that can be more effectively reduced.

  In order to achieve the above object, a function verification method according to the present invention includes a test pattern including a read processing pattern related to a read process for a storage area for design data of a semiconductor device including a plurality of storage areas and a logic circuit. A plurality of test patterns, each of the test patterns being used for a test pattern including a write process pattern related to a write process to the storage area using a comparison test pattern excluding the write process pattern. In comparison, a classification step of classifying each of the test patterns into a predetermined test pattern group, and for each test pattern group, a reference test pattern is selected from the test patterns included in the test pattern group, and the reference test pattern The read processing pattern included in For each of the read processing patterns, an internal state including the execution time of the read processing, the storage area in which the read processing is executed, and the storage contents of each storage element constituting the logic circuit in the execution time of the read processing. An internal state storing step for storing, and for each test pattern group, the storage area for executing the reading process for the reference test pattern, its storage contents, and the reading process for each of the test patterns excluding the reference test pattern An execution procedure setting step of setting the execution order of each of the test patterns based on the storage area for executing the storage and the stored contents, and selecting the internal state to be used for each of the test patterns other than the reference test pattern; For each test pattern group, the reference test pattern For the test pattern, respectively, the first feature to run and a functional verification step of performing the function verification using the internal state chosen.

  In order to achieve the above object, a function verification apparatus according to the present invention includes a test pattern including a read processing pattern for a read process for a storage area with respect to design data of a semiconductor device including a plurality of storage areas and a logic circuit A function verification apparatus that performs functional verification using a plurality of test patterns, wherein each of the test patterns is a test pattern for comparison excluding the write process pattern for the test pattern including a write process pattern related to a write process to the storage area. Classifying means for classifying each of the test patterns into a test pattern group, and selecting a reference test pattern from the test patterns included in the test pattern group for each test pattern group, and the reference test Specialize the read processing pattern included in the pattern. In addition, for each of the read processing patterns, the execution time of the read processing, the storage area in which the read processing is executed, and the storage contents of each storage element constituting the logic circuit in the execution time of the read processing are included. An internal state storage means for storing a state; and for each of the test pattern groups, the storage area for executing the reading process in the reference test pattern and the storage content thereof, and the test pattern in each of the test patterns excluding the reference test pattern Execution procedure setting for setting the execution order of each of the test patterns based on the storage area for executing the reading process and the stored contents, and selecting the internal state to be used for each of the test patterns other than the reference test pattern And a reference test pattern for each test pattern group. For people said test pattern each other than to the first, characterized in that and a function verification means for performing the function verification using the internal state chosen.

  According to the function verification method and the function verification apparatus having the above characteristics, each test pattern is compared by using a test pattern for comparison excluding the write processing pattern for each test pattern including the write processing pattern. The data is classified into pattern groups, and for each test pattern group, a read processing pattern is specified, the internal state at the execution stage of each read processing is stored, and function verification is performed using this internal state. For this reason, when using a plurality of test patterns in which a difference occurs only at a relatively early setting stage, the internal state in the reading process in the verification stage executed later than the relatively early setting stage is stored and reused. It becomes possible. In other words, since the internal state in the read process that is executed later than the relatively initial setting stage can be reused, each test pattern can be simulated from a later stage. The reusability of simulation can be improved. In other words, the test pattern omission effect can be increased more effectively, and the time and cost required for functional verification of design data of a semiconductor device having a plurality of storage areas and logic circuits can be effectively reduced. Become.

  In the function verification method according to the first aspect of the present invention, the classifying step classifies the test patterns whose test patterns or the test patterns for comparison completely match as the same test pattern group. Two features.

  In the function verification apparatus according to the first aspect of the present invention, the classifying unit classifies the test patterns that completely match the test patterns or the comparison test patterns as the same test pattern group. Two features.

  According to the function verification method and function verification apparatus having the above characteristics, the test pattern or the test pattern for comparison completely matches, that is, there is a difference in the setting of the storage area, but the operation in the verification stage is completely the same. The test patterns are classified as test pattern groups, so that each test pattern can use the internal state at the verification stage of other test patterns belonging to the same test pattern group, making it easy to classify into test pattern groups become.

  In the function verification method according to the first or second feature of the present invention, each of the storage areas in the test pattern in which the execution procedure setting step is executed first for each test pattern other than the reference test pattern. The function using the reference test pattern by specifying the storage area in which the storage content needs to be reset based on the stored content and the execution time of the reading process for the storage area in which the resetting is necessary A third feature is that a reuse index indicating the reusability of the internal state in verification is obtained, and the execution order is set in order from the test pattern having the higher reusability based on the reuse index.

  In the function verification apparatus according to the first or second feature of the present invention, each of the storage areas in the test pattern that is executed first by the execution procedure setting unit for each test pattern other than the reference test pattern. The function using the reference test pattern by specifying the storage area in which the storage content needs to be reset based on the stored content and the execution time of the reading process for the storage area in which the resetting is necessary A third feature is that a reuse index indicating the reusability of the internal state in verification is obtained, and the execution order is set in order from the test pattern having the higher reusability based on the reuse index.

  According to the function verification method and the function verification apparatus having the above characteristics, the execution order is set in order from the test pattern having the highest reusability. Therefore, the reusability of the entire test pattern, that is, the test pattern compression rate can be increased. it can.

  In the function verification method according to the third aspect of the present invention, the execution procedure setting step is the earliest among the storage areas that need to be reset for each of the test patterns except the reference test pattern. The internal state to be used is selected based on the execution time of the read process of the storage area where the read process is executed in a stage, and based on the storage area that needs to be reset in the test pattern executed later Determining the read process for storing the internal state, and the function verification step stores the internal state determined in the execution procedure setting step in the function verification for each test pattern. The fourth feature is to store the internal state.

  In the function verification apparatus according to the third aspect of the present invention, the execution procedure setting means is the earliest of the storage areas that need to be reset for each of the test patterns other than the reference test pattern. The internal state to be used is selected based on the execution time of the read process of the storage area where the read process is executed in a stage, and based on the storage area that needs to be reset in the test pattern executed later Determining the read process for storing the internal state, and the function verification unit stores the internal state determined by the execution procedure setting unit in the function verification for each test pattern. The fourth feature is to store the internal state.

  According to the function verification method and the function verification apparatus having the above characteristics, when an internal state that can be used in a test pattern to be executed later can be set for each test pattern other than the reference test pattern, the internal state is set during function verification. Since it is configured to be stored and used in a test pattern to be executed later, the reusability and compression rate of the entire test pattern can be further improved.

  In the function verification method according to the first to fourth features of the present invention, the function verification step acquires the internal state selected in the execution procedure setting step in the function verification for each of the test patterns, Resetting the storage contents of the storage area based on the storage contents of the storage area of the test pattern for executing the function verification after setting the internal state in the storage area and the storage element; Features.

  In the function verification apparatus according to the first to fourth features of the present invention, the function verification unit acquires the internal state selected by the execution procedure setting unit in the function verification for each of the test patterns, and Resetting the storage contents of the storage area based on the storage contents of the storage area of the test pattern for executing the function verification after setting the internal state in the storage area and the storage element; Features.

  According to the function verification method and function verification device of the above feature, since the internal state is set in the storage area and the storage element, and the storage contents in the storage area are reset, the test patterns other than the reference test pattern can be set. It becomes possible to execute accurately, and a specific execution procedure of the simulation using the internal state can be obtained.

  DESCRIPTION OF EMBODIMENTS Embodiments of a function verification method and a function verification apparatus (hereinafter referred to as “the method of the present invention” and “the apparatus of the present invention” as appropriate) according to the present invention will be described below based on the drawings.

<First Embodiment>
1st Embodiment of this invention method and this invention apparatus is described based on FIGS. The device of the present embodiment of the present embodiment is configured by software with a function verification program that executes each step of the method of the present invention by executing it on a computer.

  First, the configuration of the device of the present invention will be described with reference to FIGS. 1 and 2. Here, FIG. 1 is a schematic block diagram showing a schematic configuration of a computer that constructs the apparatus of the present invention, and FIG. 2 is a schematic block diagram showing a schematic configuration of each means constituting the apparatus of the present invention.

  The device 1 of the present invention is a test including a read processing pattern related to a read process for a register with respect to design data of a semiconductor device having a plurality of registers (corresponding to storage areas) and a core block (corresponding to a logic circuit) described later A function verification apparatus 1 that performs function verification using a plurality of patterns, and is configured on a computer 10 shown in FIG. As shown in FIG. 1, a computer 10 equipped with the device 1 of the present invention performs predetermined calculations such as an auxiliary storage device 11 composed of a hard disk or the like for storing information used in the device 1 of the present invention, and execution of a simulation. CPU (Central Processing Unit) 12 to be performed, ROM (Read Only Memory) 13 storing a function verification program for executing the method of the present invention, and RAM (Random Access Memory) 14 used as a working storage area used by the CPU 12 during calculation And an input device 15 for receiving information such as design data and test patterns of the semiconductor device, and a display device 16 for displaying simulation results and the like. The CPU 12, the auxiliary storage device 11, the ROM 13, and the RAM 14 are provided. Input device 15 and display device 16 are connected to each other by respective bus lines 17 a - 17 e.

  As shown in FIG. 2, the device 1 of the present invention uses each test pattern as a comparison test pattern excluding the register setting pattern for a test pattern including a register setting pattern (corresponding to a writing process pattern) related to a writing process to a register. And classifying means 2 for classifying each test pattern into a test pattern group, selecting a reference test pattern from the test patterns included in the test pattern group for each test pattern group, and reading out included in the reference test pattern Specify the processing pattern, and for each read processing pattern, the internal state including the storage time of the read process, the storage area that executed the read process, and the storage contents of each storage element that constitutes the core block at the read process execution time. Internal state storage means 3 for storing, test pattern For each group, the execution order of each test pattern based on the register that executes the reading process in the reference test pattern and its stored contents, and the register that executes the reading process in each test pattern excluding the reference test pattern and its stored contents And the execution procedure setting means 4 for selecting an internal state to be used for each test pattern other than the reference test pattern, and the selected internal state for each test pattern other than the reference test pattern for each test pattern group. A function verification unit 5 is used to perform function verification.

  Next, the method of the present invention of this embodiment will be described with reference to FIGS. Here, FIG. 3 is a flowchart showing each step of the method of the present invention.

  First, as shown in FIG. 3, the inventive device 1 acquires design data of a semiconductor device and a test pattern for functional verification of the design data (step # 101). Here, FIG. 4 shows a configuration example of the semiconductor device 100 that performs functional verification by the device 1 of the present invention and the method of the present invention. 5 shows an example of the configuration of test patterns TP1 to TP20 used in the present embodiment, and FIG. 6 shows test patterns TP1 to TP1 shown in FIG. The input waveform set by TP20 is partially shown. Specifically, as shown in FIG. 4, the semiconductor device 100 includes a core block 101 composed of a logic circuit that realizes main operations of the semiconductor device 100, and five registers that temporarily store various parameters of circuit operations. A register block 102 composed of RA to RE and a ROM 103 that stores initial setting values and operation programs of the semiconductor device 100 are provided, and these are connected via a bus line 104. The core block 101 includes a functional block FA and a functional block FB, and is configured to appropriately execute an access operation to the register block 102 and the ROM 103. 4 does not illustrate the signal lines illustrated in FIG. 6, the signal lines illustrated in FIG. 6 are input to the core block 101 of the semiconductor device 100 in the present embodiment.

  In this embodiment, as shown in FIGS. 5 and 6, test patterns TP <b> 1 to TP <b> 20 are created as test patterns for functional verification of design data of the semiconductor device 100. As shown in FIGS. 5 and 6, the test patterns TP1 to TP20 set the values of the registers RA to RE of the semiconductor device 100 using any of the register settings r1 to r18, and function blocks FA or FB. Specifically, each test pattern includes “initialization pattern” at times T1 to T3, “reading pattern of set values from ROM 103” at times T3 to T100, It consists of a “register setting pattern” from time T100 to T150 and a “verification pattern for functional blocks of the semiconductor device 100” from time T150 to T10000.

  Subsequently, as shown in FIG. 3, the device 1 of the present invention uses the classification unit 2 to compare the test patterns TP1 to TP20, and the test pattern including the register setting patterns for the registers RA to RE, excluding the register setting pattern. The test patterns TP1 to TP20 are classified into a predetermined test pattern group (step # 110, classification process).

  Specifically, the classifying unit 2 first searches the register setting pattern for the test patterns TP1 to TP20, and if the register setting pattern is included, extracts the test pattern for comparison excluding the register setting pattern (step #). 111). For a test pattern that does not include a register setting pattern, the test pattern is used as it is as a comparison test pattern. In this embodiment, the “register setting pattern” at times T100 to T150 is removed from the test patterns TP1 to TP20 to obtain a test pattern for comparison.

  Furthermore, the classification unit 2 stores the write-processed register and its storage contents in the auxiliary storage device 11 each time a register setting pattern is searched in step # 111. Here, FIG. 7 shows an example of a register setting pattern. More specifically, for example, in FIG. 7, when the write_en signal for instructing execution of the write process becomes “1”, the value of the addr [15: 0] signal that specifies the address of the register that performs the write process is determined. By doing so, it is possible to determine the register that executes the writing process. Here, the address of the register RA is set to 0x0100, the address of the register RB is set to 0x0101, the address of the register RC is set to 0x0102, the address of the register RD is set to 0x0103, and the address of the register RE is set to 0x0104. When the write_en signal becomes ‘1’, the value of the data [15: 0] signal is written to the register specified by the addr [15: 0] signal. FIG. 8 shows values written in the registers RA to RE by the register setting patterns of the test patterns TP1 to TP20 shown in FIG. More specifically, as shown in FIGS. 5 and 8, in the test pattern TP1, the register RA is set to “0”, the register RB is set to “0”, and the register RC is set to the register RC according to the register setting pattern r1 from time T100 to T150. “0”, “0” in the register RD, “0” in the register RE, and in the test pattern TP2, “1” in the register RA, “0” in the register RB, and “1” in the register RC according to the register setting pattern r2. “0” is written to the register RD, and “0” is written to the register RE.

  Subsequently, as shown in FIG. 3, the classification unit 2 compares the comparison test patterns of the test patterns TP1 to TP20 (step # 112), and groups the test patterns corresponding to the comparison test patterns that completely match each other. Into test pattern groups (step # 113). In the present embodiment, comparison is performed using a test pattern for comparison excluding the “register setting pattern” from time T100 to T150 in all the test patterns TP1 to TP20. As shown in FIG. 5, the test patterns TP1 to TP20 of the present embodiment are “initialization patterns” at times T1 to T3 and “reading patterns of set values from the ROM 103” at times T3 to T100. Therefore, the test pattern group to be classified is determined by the “verification pattern for the functional block of the semiconductor device 100” from time T150 to T10000. For this reason, in this embodiment, as shown in FIG. 8, the test patterns TP1 to TP20 include a group GA (corresponding to a test pattern group) composed of test patterns TP1 to TP10 for verifying the functional block FA, and a functional block FB. Are grouped into two groups of groups GB (corresponding to test pattern groups) composed of test patterns TP11 to TP20.

  Subsequently, as shown in FIG. 3, the device 1 of the present invention selects a reference test pattern from the test patterns included in the test pattern group for each test pattern group by the internal state storage means 3, and is included in the reference test pattern. A read processing pattern is specified, and for each read processing pattern, the internal state including the storage time of the read processing, the register that executed the read processing, and the storage contents of each storage element that constitutes the logic circuit at the read processing execution time. Store (step # 120, internal state storage step).

  Specifically, the internal state storage means 3 first selects a reference test pattern from each of the group GA and group GB (step # 121). In the present embodiment, the test pattern TP1 from the group GA and the test pattern TP11 from the group GB are selected as reference test patterns. The selection of the reference test pattern is arbitrary, and another test pattern may be selected as the reference test pattern. Subsequently, the device 1 of the present invention executes a simulation using the design data and the reference test pattern acquired in Step # 101 (Step # 122).

  Further, when a read operation is performed on any one of the registers RA to RE constituting the register block 102 in the simulation using the reference test pattern, the internal state storage unit 3 reads the register that has undergone the read process and its value. In addition, the internal state such as the storage contents of each storage element constituting the core block 101 of the semiconductor device 100 is stored in the auxiliary storage device 11. In the present embodiment, the read processing for storing the internal state is targeted for the read processing for the registers RA to RE performed during the function verification for the functional blocks from time T150 to T10000. The reading process for is not included.

  Here, FIG. 9 shows an example of the read processing pattern and the timing for storing the internal state. Specifically, in FIG. 9, when the read_en signal becomes “1”, the semiconductor device 100 refers to the value of the addr [15: 0] signal, identifies a register that performs read processing, and sets the value of the register. Read and output as data [15: 0] signal. The internal state storage unit 3 stores the register specified by the addr [15: 0] signal, the value of the data [15: 0] signal, and each memory constituting the core block 101 at the timing indicated by the broken line X in FIG. The memory content of the element is stored. Here, FIG. 10 shows the reference time that is the execution time of the read processing in each of the group GA and group GB, the reference register that executed the read processing, and the storage contents of each storage element constituting the core block 101 in this embodiment. The relationship of storage time is shown. 4 does not illustrate each signal line illustrated in FIG. 9, in the present embodiment, each signal line illustrated in FIG. 9 is a core block of the semiconductor device 100, similarly to each signal line illustrated in FIG. 6. 101 is input. As shown in FIG. 10, in this embodiment, in the simulation using the test pattern TP1 that is the reference test pattern of the group GA, the read process for the register RA at time T3000 and the read process for the register RB at time T4000 A read process for the register RC is executed at T7000, and a read process for the register RE is executed at time T9000. Similarly, in the simulation using the test pattern TP11 which is the reference test pattern of the group GB, the read process for the register RB at time T4000, the read process for the register RE at time T5000, and the read process for the register RD at time T9000, respectively. It is running.

  Subsequently, as shown in FIG. 3, the apparatus 1 of the present invention uses the execution procedure setting unit 4 to execute a read process in the reference test pattern for each of the group GA and the group GB, the storage contents thereof, and the reference test pattern. The execution order of each test pattern is set on the basis of the register for executing the reading process in each test pattern except the test pattern and the stored contents, and the internal state to be used is selected for each test pattern other than the reference test pattern (step #) 130, execution procedure setting step).

  Specifically, the execution procedure setting unit 4 first performs a reference test pattern and other test patterns, here, a reference test pattern for comparison obtained by removing the write processing pattern from the reference test pattern, and tests other than the reference test pattern. Compare each test pattern excluding the write processing pattern from each pattern, obtain a reusability index indicating reusability for each test pattern other than the reference test pattern, and highly reusable pattern based on the reusable index The simulation order is preferentially assigned from (Step # 131). In the present embodiment, first, for each test pattern other than the reference test pattern, based on the storage contents of the registers RA to RE in the test pattern executed first, the registers that need to be reset, The execution time of the read process for the register that needs to be set is specified, and a reuse index indicating the reusability of the internal state stored in the simulation using the reference test pattern is obtained. Then, based on the reuse index, the execution order is set in order from the test pattern having the highest reusability. In the present embodiment, for each test pattern other than the reference test pattern, a register to be set differently from the register setting of the reference test pattern is specified as a register that needs to be reset. Then, for each test pattern other than the reference test pattern, the execution time of the read process executed at the earliest stage among the read processes for the registers that need to be reset is set as the reference reuse end time of the simulation. The time until the reference reuse end time is obtained as the reusable time. In this embodiment, the reusable time of each test pattern is defined as a reuse index for each test pattern, and the execution order is set preferentially from the test pattern having a large value of the reuse index.

  More specifically, for example, when comparing the reference test pattern TP1 and the test pattern TP2 in the group GA, referring to FIG. 8, since the setting values of the registers RA and RC are different, the registers RA and RC are reset. It is determined that the register is necessary. Furthermore, as shown in FIG. 10, since the read process for the register RA is executed at time T3000 and the read process for the register RC is executed at time T7000, the read process is performed before the register RC in the test pattern TP2. The time T3000 of the read process for the register RA is the reference reuse end time. Therefore, in the test pattern TP2, the time from the simulation start time T1 to the time T3000 can be obtained as a reusable time during which the simulation of the reference test pattern TP1 can be reused. Similarly, test patterns TP3 to TP6 are from simulation start time T1 to time T3000, test patterns TP7 and TP9 are from simulation start time T1 to time T7000, test pattern TP8 is from simulation start time T1 to time T4000, test pattern TP10. Can obtain the time between the simulation start time T1 and the time T9000 as the reusable time. From the above, the reuse index value of each test pattern is TP10> TP7 = TP9> TP8> TP2 = TP3 = TP4 = TP5 = TP6. The simulation execution order is set in this order. Similarly, the value of the reuse index of the test patterns TP12 to TP20 of the group GB is obtained as TP20> TP16 = TP19> TP12 = TP13 = TP14 = TP17 = TP18.

  Subsequently, as shown in FIG. 3, the execution procedure setting unit 4 uses an internal state that is read at the start of simulation for each test pattern other than the reference test pattern and an internal that can be used in another test pattern to be executed later. If there is a state, a time for storing the internal state is set (step # 132). Specifically, in the present embodiment, the execution procedure setting unit 4 first obtains a reusable time as a reuse index for each test pattern to be executed first for a test pattern for obtaining an internal state to be read at the start of simulation. The test pattern having the largest reuse index value is specified as the reuse test pattern. The execution time of the read process for the register in which the read process is executed at the earliest stage among the registers having different settings between the test pattern for obtaining the internal state to be read at the start of the simulation and the reuse test pattern is referred to as the reuse end time. To do. Further, the internal state of the reuse test pattern at the reuse end time is set as a reuse internal state that is read at the start of simulation. In this way, the reuse test pattern and the reuse internal state are set for each test pattern other than all the reference test patterns. Furthermore, in this embodiment, when there is a read process executed after the reuse end time for each test pattern other than the reference test pattern, the internal state is set to be stored for each read process. By selecting the reuse internal state in this way, the reusability of the simulation of each test pattern can be maximized.

  More specifically, here, for example, in the case of the test pattern TP10 having the largest reuse index value for the reference test pattern TP1 in the group GA, the only register that needs to be reset is the register RE. The execution time T9000 of the reading process is set as the reuse end time, and the internal state at the time T9000 in the simulation of the reference test pattern TP1 is selected as the reuse internal state used in the test pattern TP10. In the case of the test pattern TP10, since there is no read process for a register executed after the time T9000, the time for storing the internal state is not set. Similarly, for the test pattern TP7 having the next largest reuse index value for the reference test pattern TP1, the internal state at the time T7000 of the reference test pattern TP1 is selected as the reuse internal state used by the test pattern TP7. Further, in the test pattern TP7, since the read process is executed at time T9000 after the reuse end time T7000, the internal state at time T9000 is set to be stored. Further, for the test pattern TP9 in which the value of the reuse index for the reference test pattern TP1 is the same as that of the test pattern TP7, the value of the reuse index for the test pattern TP7 is larger than the value of the reuse index for the reference test pattern TP1. Therefore, the test pattern TP7 is used as a reuse test pattern, and the internal state of the test pattern TP7 is used. Since the test pattern TP9 differs from the setting of the register RE in the test pattern TP7, the read time T9000 of the register RE is set as the reuse end time, and the internal state at the time T9000 in the simulation of the test pattern TP7 is set as the reuse internal state. To do. In the case of the test pattern TP7, since there is no read process for a register executed after the time T9000, the time for storing the internal state is not set. Similarly, for each test pattern of the groups GA and GB, a reuse internal state that is read at the start of simulation and an internal state that is stored for use in another test pattern that is executed later are set.

  Subsequently, as shown in FIG. 3, the execution procedure setting unit 4 extracts registers and values that need to be reset for test patterns other than the reference test pattern (step # 133). Specifically, the execution procedure setting unit 4 refers to a register that is referred to in any one of a read process at a reuse end time and a read process executed after the reuse end time for a test pattern for obtaining a register that needs to be reset. Among the specified registers, a register having a setting value different from the register setting of the reuse test pattern obtained in step # 132 is specified as a register that needs to be reset, and is stored in the auxiliary storage device 11. . Similarly, a register that needs to be reset for each test pattern other than the reference test pattern is specified and stored in the auxiliary storage device 11. More specifically, for example, the test pattern TP2 is set so as to read the internal state of the reference test pattern TP1 at time T3000, and after time T3000, read processing for the registers RA, RB, RC, RE is executed. The Further, as shown in FIG. 8, among the registers RA, RB, RC, and RE, the settings of the registers RA and RC are different from the set values of the reference test pattern TP1, which is the reuse test pattern. Identifies the register that needs to be reset. Then, information specifying the register RA and its set value “1”, and information specifying the register RC and its set value “1” are stored in the auxiliary storage device 11.

  8 and 10, for the test patterns TP13 and TP17 of the group GB, register values different from those of the test pattern 12 are not read until the end of the test, and for the test pattern TP15, the reference test pattern and the test pattern TP15 are not read. Since different register values are not referred to, there is no register that needs to be reset, so that it is determined that the execution of the simulation is unnecessary.

  Here, FIG. 11 shows, as the execution result of the execution procedure setting step in step # 130, for each test pattern of the groups GA and GB, the execution order of simulation within the group, the internal state of reuse read out at the start of simulation execution, An internal state to be stored for use in another test pattern to be executed later, a register that needs to be reset at the start of simulation execution, and its reset value are shown.

  Subsequently, as shown in FIG. 3, the device 1 of the present invention performs functional verification using the selected internal state for each test pattern other than the reference test pattern for each of the groups GA and GB by the function verification unit 5. (Step # 140, function verification process). Specifically, the function verification unit 5 selects a test pattern for executing the simulation based on the execution order of the simulation shown in FIG. For the selected selection test pattern, the function verification means 5 first acquires the reuse internal state from the execution result of the execution procedure setting step of step # 130 shown in FIG. 11, and based on the acquired reuse internal state, The internal state of the semiconductor device 100 is set. Further, based on the execution result of the execution procedure setting step of step # 130 shown in FIG. 11, the registers that need to be reset and their values are acquired, and the values that have been acquired for the registers that need to be reset of the semiconductor device 100 are re- Set. Then, the simulation of the selected test pattern is started from the reuse end time. In the test pattern during simulation execution, when the time for storing the internal state is set, the internal state at that time is stored. Similarly, the function verification means 5 determines that all test patterns other than the reference test pattern (in this case, further, simulation execution is unnecessary in step # 133) according to the simulation execution order shown in FIG. Execute simulation for (except test pattern). More specifically, for the group GA, the function verification unit 5 first executes a simulation of the test pattern TP10. In the simulation of the test pattern TP10, the function verification unit 5 reads the internal state of the reference test pattern TP1 at time T9000 and sets the internal state in the design data of the semiconductor device 100. Furthermore, after resetting “1” to the register RE of the register block 102, the simulation is started from time T9000. In this embodiment, the resetting of the register RE is performed by directly overwriting the register value by using the function of the simulator, but other means such as writing by a normal register writing procedure may be taken. Similarly, the simulation is executed for the remaining test patterns of the group GA and the group GB.

  As described above, in the present embodiment, by executing the method of the present invention by the device 1 of the present invention, the test pattern TP4 is changed between the time T1 to the time T3000 of the test pattern TP2, the time T1 to the time T4000 of the test pattern TP3. Between time T1 and time T7000, between time T1 and time T7000 of test pattern TP5, between time T1 and time T9000 of test pattern TP6, between time T1 and time T7000 of test pattern TP7, time T1 of test pattern TP8 For time T4000, for time T1 to time T9000 for test pattern TP9, for time T1 to time T9000 for test pattern TP10, for time T1 to time T4000 for test pattern TP12, for time T1 to time for test pattern TP14 During T9000, test pattern T The simulation and test between 16 times T1 to T5000, between time T1 and time T5000 of the test pattern TP18, between time T1 and time T9000 of the test pattern TP19, and between time T1 and time T9000 of the test pattern TP20 The simulation for the patterns TP13, TP15, and TP17 can be omitted, and the test is greatly compared with the conventional technique that can omit the "initialization pattern" and the "reading pattern of the set value from the ROM 103" from time T1 to time T3. The pattern omission effect can be enhanced.

Second Embodiment
A second embodiment of the method and the device of the present invention will be described with reference to FIGS. In the present embodiment, the case where the configuration of the semiconductor device and the test pattern used in the method and the device of the present invention is different from that of the first embodiment will be described. The configuration of the inventive device 1 of the present embodiment is the same as that of the first embodiment shown in FIGS. 1 and 2.

  First, in the present embodiment, a semiconductor device that performs function verification by the method and apparatus of the present invention and a test pattern used for function verification will be described with reference to FIGS. Here, FIG. 12 shows one configuration example of the semiconductor device 200 that performs functional verification by the device 1 of the present invention and the method of the present invention shown in FIG. 2, and FIG. 13 shows test patterns TP21 to TP25 used in the present embodiment. An example of the configuration is shown. Specifically, as shown in FIG. 12, the semiconductor device 200 includes a core block 201 composed of a logic circuit that realizes the main operation of the semiconductor device 200, and three registers that temporarily store various parameters of the circuit operation. A register block 202 composed of RA to RC, and a ROM 203 that stores initial setting values, operation programs, and the like of the semiconductor device 200 are provided, and these are connected via a bus line 204. The core block 201 includes a functional block FA, and is configured to appropriately execute an access operation to the register block 202 and the ROM 203. In the present embodiment, “1” is set as an initial value for each of the three registers RA to RC of the register block 202.

  In this embodiment, as shown in FIG. 13, test patterns TP21 to TP25 are used as test patterns for functional verification of design data of the semiconductor device 200. As shown in FIG. 13, the test patterns TP21 and TP23 to TP25 of the present embodiment set the registers RA to RC of the semiconductor device 200 using the register settings r21 to r24, and perform the function verification for the function block FA. The test pattern TP22 is configured to perform functional verification in an initial setting state without performing register setting. Specifically, the test patterns TP21, TP23, and TP24 are “initialization pattern” from time T1 to T3, “reading pattern of setting value from ROM 203” from time T3 to T100, and “register setting pattern from time T100 to T130. ”,“ Verification pattern for functional block of semiconductor device 200 ”of time T130 to T10000. The test pattern TP22 includes an “initialization pattern” from time T1 to T3, a “reading pattern of a set value from the ROM 203” from time T3 to T100, and a “verification pattern for the functional block of the semiconductor device 200” from time T100 to T9970. The test pattern TP25 includes an “initialization pattern” at times T1 to T3, a “reading pattern for setting values from the ROM 203” at times T3 to T100, a “register setting pattern” at times T100 to T120, and a time T120 to T9990 “Verification pattern for functional block of semiconductor device 200”. In the present embodiment, for simplicity, the test patterns TP21 to TP25 are all test patterns for performing functional verification on the functional block A of the core block 201 of the semiconductor device 200. When the block 201 includes other functional blocks, test patterns for performing functional verification for the functional block are prepared, and these are classified into groups for each functional block for performing functional verification.

  The method of the present invention according to this embodiment will be described with reference to FIGS. 3 and 12 to 18. The basic configuration of the processing procedure of the method of the present invention is the same as the processing procedure of the first embodiment shown in FIG.

  First, as shown in FIG. 3, the inventive device 1 acquires design data of a semiconductor device and a test pattern for functional verification of the design data (step # 101). In the present embodiment, the design data of the semiconductor device 200 shown in FIG. 12 and the test pattern data shown in FIG. 13 are acquired.

  Subsequently, as shown in FIG. 3, the device 1 of the present invention uses the classification unit 2 to compare the test patterns TP21 to TP25, and the test pattern including the register setting patterns for the registers RA to RC, excluding the register setting pattern. The test patterns TP21 to TP25 are classified into a predetermined test pattern group (step # 110, classification process).

  Specifically, the classification means 2 first searches for the register setting pattern for the test patterns TP21 to TP25, and for the test patterns TP21 and TP23 to TP25 including the register setting pattern, the comparison test pattern excluding the register setting pattern. Is extracted (step # 111). For the test pattern TP22 that does not include the register setting pattern, the test pattern is used as it is as a comparison test pattern. In the present embodiment, based on FIG. 13, the “register setting pattern” from the test patterns TPTP21, TP23, and TP24 to the time T100 to T130 and the “register setting pattern” from the test pattern TP25 to the time T100 to T120 are excluded. The test pattern.

  Further, as in the first embodiment, the classification unit 2 stores the write-processed register and its storage contents in the auxiliary storage device 11 each time a register setting pattern is searched in step # 111. Here, FIG. 14 shows an example of a register setting pattern. In FIG. 14, when the write_en signal for instructing the execution of the write process becomes “1”, the write process is determined by determining the value of the addr [15: 0] signal that specifies the address of the register that performs the write process. The register to be executed can be determined. Here, the address of the register RA is set to 0x0100, the address of the register RB is set to 0x0101, and the address of the register RC is set to 0x0102. Then, when the write_en signal becomes “1”, the value of the data [15: 0] signal is written to the register specified by the addr [15: 0] signal. FIG. 15 shows values written in the registers RA to RC by the register setting patterns r21 to r24 of the test patterns TP21 to TP25 shown in FIG. More specifically, as shown in FIG. 13, in the test pattern TP1, '0' is written in the registers RA to RC by the register setting pattern r21 from time T100 to T130, respectively, and the initial setting is performed in the test pattern TP2. Write processing to the registers RA to RC is not executed while the registers RA to RC are all “1”. Similarly, in the test pattern TP5, “0” is written to the register RA and “1” is written to the register RB by the register setting pattern r24 from time T100 to T120, but the writing process to the register RC is not executed, and the register RC The value of remains the initial value “1”. In FIG. 12, each signal line shown in FIG. 14 is not shown, but in this embodiment, each signal line shown in FIG. 14 is connected to the core block 201 of the semiconductor device 200 as in the first embodiment. It is configured to be input.

  Subsequently, as shown in FIG. 3, the classification unit 2 compares the test patterns TP21 and TP23 to TP25 for comparison and the test pattern TP22 (step # 112), and groups those that completely match each other. (Step # 113). In the present embodiment, for the test patterns TP21, TP23, and TP24, a comparison test pattern excluding the “register setting pattern” from time T100 to T130 is used. For the test pattern TP25, “register setting from time T100 to T120 is used. Using the test pattern for comparison excluding the “pattern”, the test pattern or the completely matched pattern for comparison is compared. In the present embodiment, as shown in FIG. 13, the test patterns TP21 and TP23 to TP25 are all compared with the comparison pattern and the test pattern TP22 as “initialization pattern”, “set value read pattern from ROM 203” and Since it is composed of “verification pattern for the functional block FA of the semiconductor device 200”, it can be classified into one group GC as shown in FIG.

  Subsequently, as shown in FIG. 3, the device 1 of the present invention selects a reference test pattern from the test patterns TP21 to TP25 by the internal state storage means 3, specifies a read processing pattern included in the reference test pattern, and performs a read process. The internal state is stored for each pattern (step # 120, internal state storage step).

  Specifically, the internal state storage unit 3 of the present embodiment first selects a reference test pattern from the test patterns TP21 to TP25 (step # 121). In the present embodiment, a test pattern TP22 that does not include a register setting pattern and is considered to easily specify the correspondence relationship of the read processing patterns is selected as a reference test pattern. As in the first embodiment, the selection of the reference test pattern is arbitrary, and another test pattern may be selected as the reference test pattern. Subsequently, the device 1 of the present invention executes a simulation using the design data acquired in step # 101 and the reference test pattern TP22 (step # 122).

  Further, as in the first embodiment, the internal state storage unit 3 performs a read operation on any of the registers RA to RC constituting the register block 202 in the simulation using the reference test pattern TP22. The internal state of the semiconductor device 200 at that time is stored in the auxiliary storage device 11. In the present embodiment, the read process for storing the internal state is intended for the read process for the registers RA to RC performed during the function verification for the functional block FA, and includes the read process for the ROM 203 of the semiconductor device 200. Absent.

  Here, FIG. 16 shows an example of the read processing pattern and the timing for storing the internal state. Specifically, in FIG. 16, when the RA_read_en signal becomes “1”, the semiconductor device 200 reads the value of the register RA and outputs it as a data [15: 0] signal. Similarly, although not illustrated, when the RB_read_en signal becomes “1”, the semiconductor device 200 reads the value of the register RB and outputs it as the data [15: 0] signal, and when the RC_read_en signal becomes “1”, The RC value is read and output as a data [15: 0] signal. The internal state storage unit 3 configures the register specified by the addr [15: 0] signal, the value of the data [15: 0] signal, and the core block 201 at the timing indicated by the broken line X in FIG. The storage contents of each storage element are stored. In FIG. 12, each signal line shown in FIG. 16 is not shown, but in this embodiment, each signal line shown in FIG. 16 is a core block of the semiconductor device 200, similarly to each signal line shown in FIG. 201 is input. Here, FIG. 17 shows the relationship between the reference time that is the execution time of the read process, the reference register that executed the read process, and the storage time for storing the storage contents of each storage element constituting the core block 201 in this embodiment. Show. As shown in FIG. 17, in this embodiment, in the reference test pattern TP22, a read process for the register RA is performed at time T2970, a read process for the register RB is performed at time T4970, and a read process for the register RC is performed at time T6970. ing.

  Subsequently, as shown in FIG. 3, the apparatus 1 of the present invention uses the execution procedure setting unit 4 to read out the register for executing the reading process in the reference test pattern TP22 and the storage contents thereof, and the reading in each of the test patterns TP21 and TP23 to TP25. The execution order of the test patterns TP21 and TP23 to TP25 is set based on the register for executing the process and the stored contents, and the internal state to be used is selected for the test patterns TP21 and TP23 to TP25 other than the reference test pattern TP22 ( Step # 130, execution procedure setting step).

  Specifically, the execution procedure setting unit 4 first compares the reference test pattern TP22 with each of the comparison test patterns obtained by removing the register setting patterns from the test patterns TP21 and TP23 to TP25, and the test patterns TP21 and TP23. A reuse index indicating reusability is obtained for each of TP25, and a simulation order is preferentially assigned from a pattern with high reusability based on the reuse index (step # 131). First, as in the first embodiment, for each test pattern other than the reference test pattern, a register that requires resetting of the storage content based on the storage content of each of the registers RA to RC in the previously executed test pattern, Then, the execution time of the read process for the register that needs to be reset is specified, and a reuse index indicating the reusability of the internal state stored in the simulation using the reference test pattern is obtained. Then, based on the reuse index, the execution order is set in order from the test pattern having the highest reusability. In the present embodiment, for each of the test patterns TP21 and TP23 to TP25, a register whose value is changed from the initial setting value is specified as a register that needs to be reset. Then, for each of the test patterns TP21, TP23 to TP25, the execution time of the read process executed at the earliest stage among the read processes for the registers that need to be reset is set as the simulation reference reuse end time, and from the start of the simulation The time until the reference reuse end time is obtained as the reusable time. In the present embodiment, similar to the first embodiment, the reusable time of each test pattern is defined as a reuse index for each test pattern, and the execution order is preferentially set from the test pattern having a large reuse index value. Set.

  More specifically, for example, when comparing the reference test pattern TP22 and the test pattern TP21, referring to FIG. 15, all the setting values of the registers RA to RC are different, so that all the registers RA to RC need to be reset. Judged to be a register. Here, in the reference test pattern TP22, as shown in FIG. 17, the read process for the register RA is executed at time T2970, the read process for the register RB is executed at time T4970, and the read process for the register RC is executed at time T6970. Correspondingly, in the test pattern TP21, the time T30 (T130-T100) related to the register setting pattern is added to the execution time T2970 of the read process for the register RA in the reference test pattern TP22, and the read process for the register RA is performed. Is executed. Similarly, in the test pattern TP21, a read process for the register RB is executed at time T5000, and a read process for the register RC is executed at time T7000. In the test pattern TP21, the time T3000 of the read process for the register RA in which the read process is performed at the earliest stage is the reference reuse end time. Therefore, in the test pattern TP21, the time between the simulation start time T1 and the time T3000 can be obtained as the reusable time. Similarly, test pattern TP23 is from simulation start time T1 to time T5000 (T4970 + T30), test pattern TP24 is from simulation start time T1 to time T7000 (T6970 + T30), and test pattern TP25 is from simulation start time T1 to time T2990. The time until (T2970 + T20) can be obtained as the reusable time. As described above, the value of the reuse index for each test pattern is TP24> TP23> TP21> TP25. The simulation execution order is set in this order.

  Subsequently, as in the first embodiment, as shown in FIG. 3, the execution procedure setting unit 4 reads the internal state read at the start of the simulation for each test pattern other than the reference test pattern, and executes it later. If there is an internal state that can be used in the test pattern, a time for storing the internal state is set (step # 132).

  Specifically, here, for example, in the case of the test pattern TP24 having the largest reuse index value for the reference test pattern TP22, the register that needs to be reset is only the register RC, and the execution time of the read process for this register RC T7000 is set as the reuse end time, and the internal state at the execution time T6970 of the read process for the register RC in the simulation of the reference test pattern TP22 is selected as the reuse internal state used in the test pattern TP24. The simulation of the test pattern TP24 is set to be executed from time T7000. In the case of the test pattern TP24, since there is no read process for the register executed after the time T7000, the time for storing the internal state is not set. Similarly, for the test pattern TP23 having the next largest reuse index value, the internal state at the time T4970 of the reference test pattern TP22 is selected as the reuse internal state used in the test pattern TP23. The simulation of the test pattern TP23 is set to be executed from time T5000. In the test pattern TP23, since the read process is executed at time T7000 after the reuse end time T5000, the internal state at time T7000 is set to be stored. Similarly, for the test pattern TP21, the internal state at the time T2970 of the reference test pattern TP22 is selected as the reuse internal state used in the test pattern TP21. The simulation of the test pattern TP21 is set to be executed from time T3000. In the test pattern TP21, since the read process is executed at the time T5000 and the time T7000 after the reuse end time T3000, the internal state at the time T5000 and the time T7000 is set to be stored. Finally, for the test pattern TP25, since the value of the reuse index for the test pattern TP21 is the largest, the test pattern TP21 is used as the reuse test pattern, and the internal state of the test pattern TP21 is used. Since the test pattern TP25 is different from the test pattern TP21 in the settings of the registers RB and RC, the read time T4990 of the register RB in which the read process is executed first is set as the reuse end time, and the test pattern TP25 is time T5000 in the simulation of the test pattern TP21. The internal state of is set as the reuse internal state.

  Subsequently, as in the first embodiment, the execution procedure setting unit 4 extracts registers that need to be reset and their values for test patterns other than the reference test pattern, as shown in FIG. 3 (step # 133). ). More specifically, for example, the test pattern TP21 is set so as to read the internal state of the reference test pattern TP22 at time T2970, and after time T2970, read processing for the registers RA to RC is executed. Further, as shown in FIG. 15, since all of the registers RA to RC are different from the set value of the reference test pattern TP22 that is a reuse test pattern, all of the registers RA to RC are specified as registers that need to be reset. . Then, information for specifying the register RA and its set value '0', information for specifying the register RB and its set value '0', information for specifying the register RC and its set value '0' are stored in the auxiliary storage device 11. To do.

  Here, FIG. 18 shows the execution order of the test pattern TP21 to TP25 of the group GC, the reuse internal state read at the start of the simulation execution, and the start of the simulation as the execution result of the execution procedure setting step of the above step # 130. It shows the time, the internal state to be stored for use in other test patterns to be executed later, the registers that need to be reset at the start of simulation execution, and their reset values.

  Subsequently, as in the first embodiment, the device 1 of the present invention uses the function verification means 5 to select the selected internal test patterns TP21 and TP23 to TP25 other than the reference test pattern TP22 as shown in FIG. Function verification is executed using the state (step # 140, function verification process).

  As described above, in the present embodiment, by executing the method of the present invention by the device 1 of the present invention, the test pattern TP24 is changed between the time T1 to the time T3000 of the test pattern TP21, the time T1 to the time T5000 of the test pattern TP23. The simulation between the time T1 and the time T4990 of the test pattern TP5 can be omitted between the time T1 and the time T7000, and the “initialization pattern” and the “reading pattern of the set value from the ROM 203” from the time T1 to the time T3. Compared with the prior art that can omit the above, the effect of omitting the test pattern can be greatly enhanced.

<Another embodiment>
<1> In each of the embodiments described above, a register is assumed as a storage area. However, the present invention is not limited to this. For example, it may be a partial area in a predetermined storage device such as an auxiliary storage device such as a hard disk.

  <2> In each of the above embodiments, for simplicity, the case where the core blocks 101 and 201 of the semiconductor devices 100 and 200 are configured to include one or a plurality of independent functional blocks has been described. It is not limited. For example, the core blocks 101 and 201 of the semiconductor devices 100 and 200 may be configured such that each functional block includes one or a plurality of common blocks that are used in common among the functional blocks.

  <3> In each of the above embodiments, in the internal state storing step of step # 120, the specification of the read processing pattern is performed sequentially during the execution of the simulation using the reference test pattern, but this is not restrictive. For example, the read processing pattern may be extracted in advance on the test pattern from the transition of the read_en signal shown in FIG.

  <4> In each of the above embodiments, in the execution procedure setting step of Step # 130, the reuse index for the reference test pattern is the reusable time obtained as the time between the start of the simulation and the reference reuse end time. Although defined, this is not restrictive. For example, in particular, when the lengths of the test patterns are the same as in the first embodiment, the test pattern for obtaining the reuse index is defined by the ratio of the reusable time to the total simulation time (reuse rate). You may do it.

  In each of the above embodiments, in the execution procedure setting step of Step # 130, the calculation of the reuse index is calculated using the simulation time. However, the present invention is not limited to this, for example, using the number of simulation cycles. It may be calculated. The reuse index in this case is defined by the number of reuse cycles.

  <5> In the above embodiments, in the execution procedure setting step of step # 130, the execution order is set in the order of input for the test patterns having the same reuse index value with respect to the reference test pattern. is not. For example, when there are three or more test patterns having the same reuse index value with respect to the reference test pattern, the value of the reuse index of another test pattern with respect to the test pattern to be executed first is further obtained. The simulation execution order may be set in descending order of the value.

  <6> In each of the embodiments described above, in the execution procedure setting step of step # 130, all the reading processes of the reference test pattern and all the reading processes executed after the reuse end time of the test pattern other than the reference test pattern However, the internal state that is not used in a test pattern to be executed later may be excluded from the storage target.

1 is a schematic block diagram showing a schematic configuration of a computer equipped with a function verification device according to the present invention. 1 is a schematic block diagram showing a schematic configuration in a first embodiment of a function verification device according to the present invention. The flowchart which shows each process of the function verification method which concerns on this invention 1 is a schematic block diagram showing a configuration example of design data of a semiconductor device used in a first embodiment of a function verification apparatus and a function verification method according to the present invention. Schematic diagram showing an example of a configuration of a test pattern used in the first embodiment of the function verification apparatus and the function verification method according to the present invention. Partial waveform diagram showing a part of a test pattern used in the first embodiment of the function verification apparatus and function verification method according to the present invention FIG. 2 is a partial waveform diagram showing an example of a test pattern write processing pattern used in the first embodiment of the function verification apparatus and function verification method according to the present invention. Schematic diagram showing an example of register setting and classification by test patterns used in the first embodiment of the function verification apparatus and function verification method according to the present invention FIG. 4 is a partial waveform diagram showing an example of a test pattern read processing pattern used in the first embodiment of the function verification apparatus and function verification method according to the present invention. A table showing the relationship between the execution time of test pattern reading processing and internal information used in the first embodiment of the function verification apparatus and function verification method according to the present invention The table | surface which shows an example of the execution result of the execution procedure setting process in 1st Embodiment of the function verification apparatus and function verification method which concern on this invention Schematic block diagram showing one configuration example of design data of a semiconductor device used in the second embodiment of the function verification apparatus and function verification method according to the present invention The schematic diagram which shows one structural example of the test pattern used in 2nd Embodiment of the function verification apparatus and function verification method which concern on this invention Partial waveform diagram showing an example of a test pattern write processing pattern used in the second embodiment of the function verification apparatus and function verification method according to the present invention The schematic diagram which shows an example of the register setting and classification by the test pattern used in 2nd Embodiment of the function verification apparatus and function verification method which concern on this invention Partial waveform diagram showing an example of a test pattern read processing pattern used in the second embodiment of the function verification apparatus and function verification method according to the present invention A table showing the relationship between the execution time of test pattern read processing and internal information used in the second embodiment of the function verification apparatus and function verification method according to the present invention The table | surface which shows an example of the execution result of the execution procedure setting process in 2nd Embodiment of the function verification apparatus and function verification method which concern on this invention Schematic block diagram showing one configuration example of design data of a semiconductor device having a plurality of storage areas and a logic circuit Schematic diagram showing one configuration example of test patterns used in the function verification technology according to the prior art Schematic diagram showing one configuration example of test patterns used in the function verification technology according to the prior art

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Function verification apparatus 2 according to the present invention Classification means 3 Internal state storage means 4 Execution procedure setting means 5 Function verification means 10 Computer 11 equipped with the function verification apparatus according to the present invention Auxiliary storage device 12 CPU
13 ROM
14 RAM
15 Input device 16 Display device 17 Bus line 100, 200, 300 Semiconductor device 101, 201, 301 Core block 102, 202, 302 Register block 103, 203, 303 ROM
104, 204, 304 Bus line FA, FB, FC Function block TA, TB, TC Test pattern

Claims (10)

A function verification method that uses a plurality of test patterns including a read processing pattern related to a read process for a storage area for design data of a semiconductor device including a plurality of storage areas and a logic circuit,
Each of the test patterns is compared using a test pattern for comparison excluding the write processing pattern for the test pattern including the write processing pattern related to the write processing for the storage area, and the test pattern is compared with a predetermined test pattern. A classification process for classifying into pattern groups;
For each test pattern group, a reference test pattern is selected from the test patterns included in the test pattern group, the read process pattern included in the reference test pattern is specified, and the read process is performed for each read process pattern. An internal state storage step of storing an internal state including the storage contents of each storage element constituting the logic circuit at the execution time of the storage circuit, the storage area where the read process is executed, and the execution time of the read process;
For each test pattern group, the storage area for executing the reading process in the reference test pattern and its storage contents, and the storage area for executing the reading process in each of the test patterns excluding the reference test pattern, and An execution procedure setting step of setting the execution order of each of the test patterns based on the stored contents, and selecting the internal state to be used for each of the test patterns other than the reference test pattern;
A function verification step of executing, for each test pattern group, the function verification using the selected internal state for each of the test patterns other than the reference test pattern.   The function verification method according to claim 1, wherein the classifying step classifies the test patterns whose test patterns or the test patterns for comparison completely match as the same test pattern group.   In the execution procedure setting step, for each test pattern other than the reference test pattern, the storage area in which the storage content needs to be reset based on the storage content of each of the storage areas in the test pattern executed first And, specifying the execution time of the read processing for the storage area that needs to be reset, obtaining a reuse index indicating the reusability of the internal state in the function verification using the reference test pattern, The function verification method according to claim 1, wherein an execution order is set in order from the test pattern having the high reusability based on a reuse index. In the execution procedure setting step, the reading of the storage area in which the reading process is executed at the earliest stage among the identified storage areas that need to be reset for each of the test patterns excluding the reference test pattern. Based on the execution time of the process, select the internal state to use, determine the read process to store the internal state based on the storage area that needs to be reset in the test pattern to be executed later,
The function verification step stores the internal state of the read process for storing the internal state determined in the execution procedure setting step in the function verification for each test pattern. Function verification method.   In the function verification for each of the test patterns, the function verification step acquires the internal state selected in the execution procedure setting step, sets the internal state in the storage area and the storage element, and then performs the function verification. 5. The function verification method according to claim 1, wherein the storage contents of the storage area are reset based on the storage contents of the storage area of the test pattern for executing the test. A functional verification device that performs functional verification using a plurality of test patterns including a read processing pattern related to a read process for the storage area for design data of a semiconductor device including a plurality of storage areas and a logic circuit,
Each of the test patterns is compared by using a test pattern for comparison excluding the write processing pattern for the test pattern including the write processing pattern related to the write processing to the storage area, and the test pattern group is compared with each other. Classification means for classifying into,
For each test pattern group, a reference test pattern is selected from the test patterns included in the test pattern group, the read process pattern included in the reference test pattern is specified, and the read process is performed for each read process pattern. An internal state storage means for storing an internal state including a storage content of each storage element constituting the logic circuit at the execution time of the storage circuit, the storage area where the read process is executed, and the execution time of the read process;
For each test pattern group, the storage area for executing the reading process in the reference test pattern and its storage contents, and the storage area for executing the reading process in each of the test patterns excluding the reference test pattern, and An execution procedure setting means for setting the execution order of each of the test patterns based on the stored content, and selecting the internal state to be used for each of the test patterns other than the reference test pattern;
A function verification apparatus comprising: function verification means for executing the function verification using the selected internal state for each of the test patterns other than the reference test pattern for each test pattern group.   The function verification apparatus according to claim 6, wherein the classifying unit classifies the test patterns whose test patterns or the test patterns for comparison completely match as the same test pattern group.   The execution procedure setting means includes the storage area in which the storage content needs to be reset based on the storage contents of each of the storage areas in the test pattern executed first for each of the test patterns other than the reference test pattern. And, specifying the execution time of the read processing for the storage area that needs to be reset, obtaining a reuse index indicating the reusability of the internal state in the function verification using the reference test pattern, 8. The function verification apparatus according to claim 6, wherein an execution order is set in order from the test pattern having the high reusability based on a reuse index. The execution procedure setting means reads the storage area where the read process is executed at the earliest stage among the specified storage areas that need to be reset for each of the test patterns except the reference test pattern. Based on the execution time of the process, select the internal state to use, determine the read process to store the internal state based on the storage area that needs to be reset in the test pattern to be executed later,
The function verification unit stores the internal state of the read process for storing the internal state determined by the execution procedure setting unit in the function verification for each test pattern. Functional verification device.   The function verification unit acquires the internal state selected by the execution procedure setting unit in the function verification for each of the test patterns, sets the internal state in the storage area and the storage element, and then performs the function verification. 10. The function verification device according to claim 6, wherein the storage contents of the storage area are reset based on the storage contents of the storage area of the test pattern for executing the test.

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