JP2008113382A - Method for manufacturing piezoelectric vibrator, piezoelectric vibrator, and electronic component - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress breakage of a vibrator formation region of a wafer when piezoelectric vibrators such as crystal vibrators are made of the wafer. <P>SOLUTION: A method for manufacturing piezoelectric vibrators in which many piezoelectric vibrators are formed on the wafer as a piezoelectric substrate by using photolithography and those piezoelectric are parted includes: forming through holes for prevention against cracking propagation in a peripheral edge part of the piezoelectric substrate while enclosing vibrator formation regions for forming the piezoelectric vibrators; forming an etching mask for piezoelectric vibrator formation after forming the through holes; and forming the piezoelectric vibrators in the vibrator formation regions. Even if the wafer cracks from a peripheral end to the center, a spread of the cracking can be suppressed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a piezoelectric vibrator, a piezoelectric vibrator manufactured by the manufacturing method, and an electronic component including the piezoelectric vibrator.

  The quartz resonator is, for example, an element having a quartz piece (quartz blank) that is a piezoelectric vibrating piece, and a pair of excitation electrodes (excitation electrodes) provided on the front and back surfaces of the quartz piece, When a voltage is applied to the excitation electrode, it utilizes the characteristic that crystal vibration is excited by the piezoelectric inverse effect of quartz, and is widely used in electronic components such as oscillators as a reference source for frequency and time.

  An example of a manufacturing process of a conventional crystal unit will be described. First, in the crystal piece forming region in the center of the wafer W made of crystal, for example, a mask is formed on the front and back surfaces thereof. Subsequently, a large number of mask patterns are formed along the outer shape of the crystal piece and overlapping each other in the formation regions of the front and back masks, and the crystal on the surface of the wafer W is exposed to these mask patterns. These overlapping mask patterns are formed by aligning the position of the wafer W with high accuracy using an alignment mark M described later.

Thereafter, wet etching is performed, and the exposed quartz is etched along the mask patterns on the front and back surfaces, and the outer shapes of a large number of crystal pieces are formed simultaneously. After the etching, a metal film is formed on the front and back surfaces of each crystal piece attached to the wafer W by sputtering or the like, and the metal films on the front and back surfaces are etched to electrically connect the pair of excitation electrodes described above and the excitation electrodes. And a lead-out electrode having a shape drawn out from the excitation electrode to the outside of the crystal piece, and after the electrodes are formed, the connecting portion is cut and each crystal piece is separated from the wafer W. .

The crystal piece formed as a crystal resonator in such a manner is sealed with a package, for example, and the lead electrode is electrically connected to an electrode provided in the package, so that an electronic component product is obtained. Will be shipped as.

  By the way, in recent years, in order to increase the oscillation frequency of the crystal resonator, the thickness of the crystal piece has been reduced, and the thickness of the wafer W has been reduced by the thickness reduction. For example, a wafer having a thickness of about 100 μm may be used. is there. Normally, the wafer W is manufactured by, for example, polishing a rod-shaped crystal crystal so as to have a predetermined standard size, and cutting the crystal to have a predetermined thickness. Therefore, chipping (chips) may occur on the side peripheral surface of the wafer W.

  In particular, a part of the side peripheral surface of the wafer W is a plane called an orientation flat (orientation flat) OF so that each apparatus used when performing the above-described processes on the wafer W determines the direction of the wafer W. This orientation flat OF is likely to be chipped by being sharpened more than other parts.

  The impact resistance of the wafer W is reduced due to the thinning of the wafer W. For example, when the wafer W is subjected to each process as described above or when being transferred between apparatuses for performing each process, There is a possibility that a crack (crack) C may occur from the chipping of the side peripheral surface toward the center portion. And as shown to Fig.16 (a), when the crack C spreads in the crystal piece formation area | region 11 shown with a chain line in a figure, a crystal piece cannot be formed around the crack C in the formation area 11, or? Or there is a possibility that a defect may occur in the formed crystal piece.

In addition, alignment marks M serving as a reference for positioning of the wafer W are obtained by slightly shaving the surface of the surface of the wafer W, for example, two places on both sides of the crystal piece forming region 11 or by embedding a metal piece. In addition to being used for alignment when forming the mask pattern on the front and back surfaces for forming the outer shape of the crystal piece as described above, alignment is performed in each process such as etching for forming the excitation electrode, for example. The wafer W is aligned with respect to the mark M.

Accordingly, as shown in FIG. 16B, when the alignment mark M is damaged by the crack C, the wafer W is not properly aligned during each processing, and the processing steps after the damage are normal. Thus, the above-described mask pattern and electrodes cannot be formed at normal positions. As a result, the yield of the crystal piece and the crystal unit may be reduced.

  An object of the present invention is to provide a technique for suppressing a decrease in the yield of piezoelectric vibrators by manufacturing a piezoelectric vibrator such as a crystal vibrator from a wafer by suppressing breakage of a vibrator forming region of the wafer. .

The piezoelectric vibrator manufacturing method of the present invention is a piezoelectric vibrator manufacturing method in which a large number of piezoelectric vibrators are formed on a wafer which is a piezoelectric substrate using photolithography, and the piezoelectric vibrators are divided.
Forming a through hole for preventing crack propagation so as to surround a vibrator forming region for forming a piezoelectric vibrator at a peripheral portion of the piezoelectric substrate;
Forming the piezoelectric vibrator forming etching mask after forming the through hole;
And a step of forming a piezoelectric vibrator in the vibrator forming region.

The wafer includes an alignment mark for aligning the wafer during exposure. For example, the through hole is formed outside the alignment mark. A plurality of the through holes may be provided at intervals in the circumferential direction. In this case, for example, in the plurality of through holes, some of the through holes adjacent to each other overlap in the diameter direction of the wafer. Further, for example, the outer shape of the wafer is previously made larger than the standard value, and the wafer outside this standard value is subjected to wet etching or laser processing to be molded to the size of the standard value. The step of forming the non-standard wafer to the standard value and the step of forming the through hole are simultaneously performed by wet etching or laser processing. The thickness of the wafer is, for example, 150 μm or less.

The piezoelectric vibrator of the present invention is manufactured by the method described above, and the electronic component of the present invention includes the piezoelectric vibrator.

According to the present invention, a through hole for preventing crack propagation is formed so as to surround a vibrator forming region for forming a piezoelectric vibrator on a wafer which is a piezoelectric substrate. Therefore, in the subsequent piezoelectric vibrator forming process, even if an impact is applied to the wafer and a crack occurs from the peripheral edge to the center of the wafer, there is no need to transmit the impact by forming the through hole. The progress of cracks to the inner side is prevented, and the spread of the cracks is suppressed. As a result, the crack reaches the device formation region, and the region is not damaged and the formation of the piezoelectric vibrating piece is not hindered. Accordingly, it is possible to suppress a decrease in the yield of the piezoelectric vibrating piece.

  Subsequently, an embodiment of the present invention will be described. In this embodiment, the piezoelectric substrate is made of, for example, an AT-cut quartz as shown in FIG. 1, and the diameter shown in FIG. A procedure for forming a wafer W having a diameter of 3 inches and manufacturing the crystal resonator 3 as the piezoelectric vibrator shown in FIG. 3 from the wafer W will be described. FIG. 1 shows the surface of the non-standard value wafer 2, and a region 21 surrounded by a chain line in the drawing shows a device formation region. The non-standard value wafer 2 is formed, for example, by first cutting a part of the side wall of the quartz raw stone as the orientation flat OF, then cutting the side wall other than the orientation flat OF, and forming it into a substantially cylindrical shape. Is formed by slicing to a predetermined thickness. Further, as will be described later, a large number of crystal pieces 31 that are piezoelectric vibrating pieces are formed in the device forming region 21. The left and right two portions of the surface across the device formation region 21 are configured as alignment marks M by being slightly cut in advance. The dotted line in the figure shows the outer shape of the wafer W. In addition, the thickness of the nonstandard wafer 2 and the wafer W is, for example, 150 μm or less, for example, 20 μm to 150 μm. The thickness is set in this way because the occurrence of cracks is often a problem when the thickness of the wafer is less than 50 times the number of inches of the size (μm). This is because the wafer becomes difficult to handle when the thickness of the wafer is smaller than 20 μm. Therefore, when the size of the wafer W is 2 inches, the thickness is set to 20 μm to 100 μm, for example, and when the size is 4 inches, the thickness is set to 20 μm to 200 μm, for example.

FIG. 2 shows the surface of the wafer W. As will be described later, the entire periphery of the nonstandard wafer 2 is etched to form its outer shape, and the orientation flat OF described in the background art section. Is formed. The wafer W is formed with eight groove-shaped through holes 22 penetrating the wafer W in the thickness direction outside the device formation region 21 and the alignment mark M, and each through hole 22 is formed as shown in the figure. One ring surrounding the device formation region 21 and the alignment mark M has a shape divided into eight in the circumferential direction.

  A region surrounded by a dotted line in the drawing in the device forming region 21 indicates regions 101 to 104 where the crystal resonator 2 is formed, and one crystal piece is formed from each region. Actually, the crystal resonator 2 is not limited to four regions 101 to 104, but is set at intervals over the entire device formation region 21 surrounded by a chain line in FIG. Each process performed when the crystal resonator 3 is formed is performed on the entire device forming region 21.

3A and 3B show the front and back surfaces of the crystal unit 3, respectively, and the front and back surfaces of the crystal unit 3 are configured to have the same layout. In the figure, reference numeral 31 denotes a rectangular crystal piece, and reference numerals 32 and 33 denote a pair of excitation electrodes provided at the center of the front surface and the center of the back surface of the crystal unit 3, respectively. In the figure, reference numerals 34 and 35 denote extraction electrodes, which are integrally formed with the excitation electrodes 32 and 33 on the front and back surfaces of the crystal piece 31, respectively. The extraction electrode 34 (35) is formed to extend outward from the excitation piece 32 (33) to the outside of the crystal piece 31, and to straddle the back surface (front surface) of the crystal piece 32 through the side surface of the crystal piece 31. Yes.

  Next, a process of forming the wafer W of FIG. 2 from the nonstandard wafer 2 of FIG. 1 will be described with reference to FIG. FIG. 4 shows how the vertical cross section indicated by the arrow A-A ′ in FIG. 1 changes as each process is performed on the non-standard value wafer 2. First, as shown in FIGS. 4 (a) and 4 (b), metal films 41 and 42 are formed on the front and back surfaces of the nonstandard wafer 2 by sputtering, respectively, and subsequently, as shown in FIG. 4 (c). Resist films 43 and 44 are formed on 41 and 42, respectively. Although the metal films 41 and 42 are shown as one layer in the figure, they are actually configured as a laminated film in which a film made of Au (gold) is laminated on a base film made of Cr (chromium). Metal films 51 and 52 to be described later are similarly configured.

  Subsequently, although not shown in the figure, for example, after irradiating a laser to remove the resist film 43 and the metal film 41 near the alignment mark M to expose the alignment mark M, the alignment mark M is exposed. Based on the above, the nonstandard wafer 2 is aligned, and the resist films 43 and 44 on the front and back surfaces are exposed in accordance with the shape of the wafer W. Thereafter, the nonstandard wafer 2 is developed, and the resist films 43 and 44 corresponding to the exposed portions are removed (FIG. 4D). The removed portions are outside regions 45 and 46 which are external reports than the outer region of the wafer W, and through-hole forming regions 47 and 48 which are regions where the through-holes 22 should be formed.

  After the development processing, the metal films 41 and 42 are etched using the resist films 43 and 44 that remain without being removed as a mask (FIG. 4E), a mask pattern is formed on the metal films 41 and 42, and steps 45 and 46 are formed. In addition, the surface (crystal surface) of the wafer W is exposed to the resist patterns 47 and 48. FIG. 5 shows the surface of the nonstandard wafer 2 on which the mask pattern is thus formed.

Thereafter, the nonstandard wafer 2 is immersed in a solution containing hydrofluoric acid as an etching solution, and the peripheral portions of the nonstandard wafer 2 are etched using the metal films 41 and 42 that remain without being removed as a mask. At the same time as forming the outer shape of the wafer W, etching is performed along the patterns 47 and 48 to form the through holes 22 (FIG. 4F). Thereafter, the metal films 41 and 42 and the resist films 43 and 44 on the front and back surfaces are removed (FIG. 4G).

  Subsequently, a process of forming the crystal resonator 3 from the wafer W formed as described above will be sequentially described with reference to FIGS. 6 to 7, the vertical cross sections of the vibrator formation regions 101 and 102 in which the crystal vibrator 2 is formed, which are indicated by arrows BB ′ in FIG. 2, change as each process is performed on the wafer W. It shows a state. First, after the metal films 51 and 52 made of Cr (chrome) and Au (gold) are formed on the front and back surfaces of the wafer W by sputtering, respectively, the resist films 53 and 54 are formed on the metal films 51 and 52, respectively. Be filmed.

  Subsequently, for example, a laser is irradiated to remove the resist film 53 and the metal film 51 in the vicinity where the alignment mark M is covered to expose the alignment mark M, and then align the wafer W with reference to the alignment mark M. I do. Thereafter, the wafer W is exposed using a pattern mask corresponding to the shape of the regions 101 to 104 and then developed, and the resist film 53 on the surface side in each of the regions 101 to 104 is removed, and is not subsequently removed. The metal film 51 in each of the regions 101 to 104 is removed by etching using the remaining resist film 53 as a mask (FIG. 6A). FIG. 8 shows the surfaces of the regions 101 to 104 at this time.

Thereafter, the surface of the wafer W in the regions 101 to 104 is slightly etched using the metal film 51 as a mask so that the crystal piece 21 to be formed has a desired frequency characteristic, and the thickness thereof is adjusted. The resist film 53 on the side, the metal film 52 on the back side, and the resist film 54 on the back side are peeled off.

  Thereafter, a metal film 61 and a metal film 62 made of Cr and Au are formed on the front and back surfaces of the wafer W by sputtering, for example, to form an etching mask for forming the outer shape of the crystal piece 31. Subsequently, resist films 63 and 64 are formed on the metal films 61 and 62, respectively (FIG. 6B).

After forming each film, the alignment mark M is exposed as described above, the wafer W is aligned based on the alignment mark M, and then the resist films 63 and 64 are exposed and developed, and each resist Resist patterns 65 and 66 are formed on the films 63 and 64 (FIG. 6C). FIG. 9 shows the surface of the wafer W on which the resist pattern 65 is formed. As shown in the figure, the resist pattern 65 extends along the periphery of each region 101 to 104 and is a crystal piece to be formed. A rectangular frame is formed along the outer periphery of 31. Further, the resist pattern 66 on the back surface side of the wafer W is formed to have the same shape as the resist pattern 65 on the front surface side and to overlap the resist pattern 65 in order to cut out the outer shape of the crystal piece 31 by etching using a mask pattern described later. Is done. The resist patterns 65 and 66 are not hung on a part of the periphery of the regions 101 to 104 so that the crystal piece is supported by the wafer W even after the outer shape of the crystal piece 31 is formed after etching.

Returning to FIG. 6, after the resist patterns 65 and 66 are formed, the metal films 61 and 62 are etched along the resist patterns 65 and 66 so that the surface of the wafer W (crystal surface) is exposed on the metal films 61 and 62. After the mask pattern is formed on the wafer W, the wafer W is immersed in a solution containing hydrofluoric acid, which is an etching solution, and etched from the front and back surfaces along the mask pattern to form a groove portion 67 penetrating the front and back surfaces of the wafer W. Thus, the outer shape of the crystal piece 31 is formed (FIG. 7D).

  After the outer shape of the crystal piece 31 is formed, the resist films 63 and 64 and the metal films 51, 61 and 62 are removed from the front and back surfaces of the wafer W, and then the wafer W is formed to form electrodes on each crystal piece 21. The front and back surfaces are cleaned. Subsequently, the metal films 71 and 72 constituting the excitation electrodes 32 and 33 and the extraction electrodes 34 and 35 shown in FIG. Subsequently, resist films 73 and 74 are formed on the metal films 71 and 72, respectively (FIG. 7A). After the wafer W is aligned based on the alignment mark M, the resist film 73 is formed. , 74 are exposed and developed so as to correspond to the shapes of the excitation electrodes 32, 33 and the extraction electrodes 34, 35 of the crystal piece 31 as shown in FIG. 10 (FIG. 7B). ). The metal films 71 and 72 are etched using the formed resist films 73 and 74 as a mask to form excitation electrodes 32 and 33 and extraction electrodes 34 and 35. After these electrodes are formed, the resist films 83 and 84 are formed. Removed. Thereafter, the crystal piece 3 is formed by separating the crystal piece 31 from the wafer W (FIG. 7C).

  During each process from the formation of the wafer W to the separation of the crystal unit 3 from the wafer W, the wafer W is transferred to the apparatus for performing these processes and placed on a predetermined part of the apparatus. At this time, an impact is applied to the wafer W, a crack C is generated from the side peripheral edge toward the central portion, and the crack C spreads toward the central portion of the wafer W as shown in FIG. However, when the crack C reaches the through-hole 22 as shown in FIG. 11B, the impact applied to the wafer W is alleviated and the spread of the crack C is suppressed.

The crystal resonator 3 is manufactured as an electronic component by being enclosed in a package 8 as shown in FIGS. 12 (a) and 12 (b), for example. In the figure, reference numeral 81 denotes a pair of electrodes provided in the package 8 (only one is shown in the figure), which is electrically connected to the extraction electrodes 34 and 35 via a conductive adhesive 82. In the figure, reference numeral 83 denotes an electrode provided at the lower portion of the package 8, and is electrically connected to the electrode 81 via a wiring in the package 8. For example, the package 8 is mounted on a wiring board (not shown) on which circuit components of an oscillation circuit are mounted.

In the present embodiment, the device formation region 21 and the alignment mark M are surrounded at the peripheral edge of the wafer W, and a through hole 22 is formed so as to penetrate the wafer W in the thickness direction. Forming. Therefore, even if an impact is applied to the wafer W after the through-hole 22 is formed and a crack C is generated from the peripheral edge of the wafer W toward the center, the through-hole 22 is formed so that there is nothing to transmit the impact. The progress of the crack C to the inner side is prevented, and the spread of the crack C is suppressed. As a result, the crack C reaches the device formation region 21, and the formation region 21 is damaged to prevent the crystal resonator 3 from being formed. Further, the crack C reaches the alignment mark M, and the subsequent processing using the alignment mark, such as formation of a mask pattern for forming the outer shape of the crystal piece, is affected by the misalignment of the wafer W, so that the normal crystal piece 31 is formed. Can be prevented from being hindered. Accordingly, it is possible to suppress the yield of the crystal piece 31 and the crystal resonator 3 formed using the crystal piece 31 from being lowered.

In the above embodiment, the outer periphery of the wafer 2 outside the standard value is wet etched to form the outer shape of the wafer W. Compared with the case where the outer shape of the wafer W is formed by polishing, chipping is performed at the peripheral edge of the wafer W. Occurrence can be suppressed. Therefore, the generation of the crack C is suppressed, and the damage of the device formation region 21 and the alignment mark M can be more reliably suppressed. Further, since the through hole 22 is formed at the same time as the outer shape of the wafer W is formed, it is possible to suppress a decrease in throughput as compared with the case where these are formed separately.

In forming the through-hole 22, instead of performing wet etching, the formation may be performed by irradiating the wafer W with a laser or by so-called sand blasting by blowing an abrasive such as sand.

  In order to prevent the crack C from spreading, the through hole may be formed as shown in FIG. As shown in the drawing, a groove-like through hole 91 is formed in the wafer W so as to surround the alignment mark M and the device formation region 21 and penetrates the front and back of the wafer W. The through hole 91 is formed as described above. Similar to the through-hole 22 in the form, the ring has a shape divided into a plurality of parts in the circumferential direction. A through hole 92 penetrating the front and back of the wafer W is formed outside the through hole 91. The through hole 92 also has a shape in which the ring is divided in the circumferential direction, and is formed so as to cover the cut of the through hole 91, and the alignment mark M and the entire device formation region 21 are formed by the through hole 91 and the through hole 92. The circumference is surrounded. As a result, it is possible to more reliably prevent the crack C from reaching the alignment mark M and the device formation region 21 and damaging them.

In addition, as a through-hole for preventing crack propagation, a large number of circular holes 93 may be arranged in the circumferential direction of the wafer W as shown in FIG. Further, as shown in FIG. 14B, a large number of arc-shaped slits 94 penetrating the front and back may be formed along the circumferential direction of the wafer W. A part of the adjacent slits 94 overlaps in the diameter direction of the wafer W, and the propagation of the crack C from the entire circumference of the wafer W can be suppressed more reliably by forming in this way. As shown in FIG. 15, the plurality of through holes are not limited to being formed, and one through hole 95 may be formed in a slit shape along the circumferential direction of the wafer W.

  In the above embodiment, the outer shape of the wafer W is formed and the through hole 22 is simultaneously formed. However, before forming the outer shape of the wafer W, for example, a mask pattern corresponding to the through hole 22 is formed and the mask pattern is formed. After forming the through-holes 22, a mask having a mask pattern for outer shape formation corresponding to the outer shape of the wafer W may be formed, and the outer shape of the wafer W may be formed by etching. Further, the through hole 22 may be formed after the outer shape of the wafer W is formed.

It is the figure which showed the board | substrate used for embodiment of this invention. It is the figure which showed the wafer formed from the said board | substrate by the manufacturing process of embodiment of this invention. It is the figure which showed the crystal oscillator formed from the said wafer by the manufacturing process of embodiment of this invention. It is process drawing which showed the manufacturing process of the said wafer. It is the figure which showed the board | substrate in the said manufacturing process. It is process drawing which showed the manufacturing process of the said crystal oscillator. It is process drawing which showed the manufacturing process of the said crystal oscillator. It is explanatory drawing which showed the pattern formed in a wafer in the said manufacturing process. It is explanatory drawing which showed the pattern formed in a wafer in the said manufacturing process. It is explanatory drawing which showed the crystal piece formed in a wafer in the said manufacturing process. It is explanatory drawing which showed a mode that the spreading of the crack was suppressed in the said manufacturing process. It is explanatory drawing which showed the said crystal oscillator of the state enclosed with the package. It is the figure which showed the structure of the other wafer. It is the figure which showed the structure of the other wafer. It is the figure which showed the structure of the other wafer. It is explanatory drawing which shows the crack which generate | occur | produced in the wafer in the manufacturing process of the conventional crystal oscillator.

Explanation of symbols

C Crack M Alignment mark W Wafers 101, 102, 103, 104 Crystal oscillator formation region 2 Non-standard value wafer 21 Device formation region 3 Crystal resonator 31 Crystal piece

Claims (9)

In a method for manufacturing a piezoelectric vibrator in which a large number of piezoelectric vibrators are formed by using photolithography on a wafer which is a piezoelectric substrate, and the piezoelectric vibrators are divided.
Forming a through hole for preventing crack propagation so as to surround a vibrator forming region for forming a piezoelectric vibrator at a peripheral portion of the piezoelectric substrate;
Forming the piezoelectric vibrator forming etching mask after forming the through hole;
Next, forming a piezoelectric vibrator in the vibrator forming region;
A method for manufacturing a piezoelectric vibrator, comprising: The wafer includes an alignment mark for aligning the wafer during exposure,
The method for manufacturing a piezoelectric vibrator according to claim 1, wherein the through hole is formed outside the alignment mark. 3. The method of manufacturing a piezoelectric vibrator according to claim 1, wherein a plurality of the through holes are provided at intervals in the circumferential direction. 4. The method of manufacturing a piezoelectric vibrator according to claim 3, wherein in the plurality of through holes, a part of the through holes adjacent to each other overlap each other in the diameter direction of the wafer. The outer shape of the wafer is previously made larger than the standard value, and includes a step of performing wet etching or laser processing on the non-standard value wafer to form the standard value. A method for manufacturing the piezoelectric vibrator according to claim 1. 6. The piezoelectric vibrator according to claim 5, wherein the step of forming the non-standard value wafer into a standard value size and the step of forming the through hole are simultaneously performed by wet etching or laser processing. Production method. The method for manufacturing a piezoelectric vibrator according to claim 1, wherein the wafer has a thickness of 150 μm or less. A piezoelectric vibrator manufactured by the method according to claim 1.   An electronic component comprising the piezoelectric vibrator according to claim 8.

Images