JP2008112759A - Ceramic electronic component and its manufacturing process - Google Patents

Ceramic electronic component and its manufacturing process Download PDF

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JP2008112759A
JP2008112759A JP2006293198A JP2006293198A JP2008112759A JP 2008112759 A JP2008112759 A JP 2008112759A JP 2006293198 A JP2006293198 A JP 2006293198A JP 2006293198 A JP2006293198 A JP 2006293198A JP 2008112759 A JP2008112759 A JP 2008112759A
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thickness
ceramic
electronic component
ceramic electronic
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JP4868145B2 (en
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Yasutaka Amaya
Osamu Hirose
Shintaro Kin
Kazuhiro Nakamura
和浩 中村
康孝 天谷
修 廣瀬
慎太郎 金
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Tdk Corp
Tdk株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/228Terminals
    • H01G4/232Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals

Abstract

Disclosed is a ceramic electronic component capable of preventing IR deterioration due to penetration of a plating solution, making a terminal electrode film thickness constant, keeping an outer shape within a standard, and preventing occurrence of a tombstone phenomenon.
A ceramic substrate is a hexahedron, and internal electrode layers and are embedded in the ceramic substrate, and at least one end is led out to a side surface of the ceramic substrate. The terminal electrodes 21 and 22 are continuously formed on the side surfaces 11 and 12 from which one ends of the internal electrode layers 31 and 32 are led out and the four surfaces 13 to 16 adjacent to the side surfaces 11 and 12. The minimum thickness R of the corner where the side surfaces 11 and 12 and the surfaces 13 to 16 intersect, the length B from the corner to the tip on the surfaces 13 to 16, and the length in the longitudinal direction of the element body including the terminal electrodes L satisfies 20.5 × 10 −2 ≦ B / L ≦ 28.5 × 10 −2 and 0.61 × 10 −2 ≦ R / L ≦ 0.98 × 10 −2 .
[Selection] Figure 2

Description

  The present invention relates to a ceramic electronic component having an internal electrode layer embedded in a ceramic substrate and a method for manufacturing the same. More specifically, the present invention relates to a multilayer ceramic capacitor, a chip inductor, a chip resistor, or a composite ceramic electronic component thereof, and a manufacturing method thereof.

  This type of ceramic electronic component is used as a so-called chip component, and terminal electrodes are provided on opposite ends of a hexahedral ceramic base. These terminal electrodes are connected to an internal electrode layer embedded in the ceramic substrate, and are used to derive the electrical characteristics acquired by the internal electrode layer to the outside. The terminal electrode is usually formed by applying a conductive paste on the side surface of the ceramic substrate and then performing electroplating thereon.

  The problem with this type of ceramic electronic component is that the conductive paste is applied to the side surfaces of a square hexahedral ceramic base, and the thickness of the conductive paste applied to the corners of the ceramic base is therefore large. In the subsequent plating process, the plating solution enters the inside of the ceramic substrate from the thin corners of the film thickness, and causes IR deterioration (increase in DC resistance).

  Increasing the coating thickness of the conductive paste can eliminate the above-mentioned problems, but this type of ceramic electronic component has limitations on the outer shape (horizontal, vertical, and thickness dimensions) that can be taken. Therefore, there is a limit to the coating thickness allowed for the conductive paste. In particular, recent ceramic electronic components of this type have been reduced in size and thickness, for example, 1.0 × 0.5 × 0.5 mm, so that the conductive paste can be applied to a coating thickness. There will be severe limits.

  In addition, increasing the coating thickness of the conductive paste tends to cause thickness fluctuations, resulting in problems in appearance. In addition, chip-type electronic components are mounted on a substrate by reflow soldering. The so-called chip standing (tombstone phenomenon) in which the component stands upright with respect to the substrate is likely to occur.

  Various proposals have heretofore been made regarding the method of forming terminal electrodes, but the above-mentioned problems have not yet been completely solved. For example, a method in which a ceramic electronic component is pushed into an elastic body in which a conductive paste is previously infiltrated, and the conductive paste is applied so as to be 10 nm to 2 μm after firing (see Patent Document 1), or an end portion of a ceramic electronic component in advance. A method of forming a conductive paste film having a uniform thickness after applying a conductive paste having a thickness greater than the required thickness to the substrate and transferring the excess conductive paste to a support having an uneven surface formed thereon (see Patent Document 2). And a method of forming a conductive paste film having a uniform thickness (see Patent Document 3), after removing a surplus by transferring to a nylon mesh after applying a conductive paste of a necessary thickness or more, After the conductive paste is applied to the end of the ceramic electronic component, the end of the ceramic electronic component to which the conductive paste is applied is pressed against the elastic body having open pores. And then removing the excess conductive paste adhering to the end portion of the ceramic electronic component by absorbing the open pores of the elastic body (see Patent Document 4). is doing.

  However, in the method proposed by Patent Document 1, the paste content varies depending on the position of the elastic body, or the elastic body is not easily deformed when the ceramic electronic component is pushed in. Tends to fluctuate. Due to the change in dimensions, the outer dimensions change and the yield decreases, and in addition, a chip standing phenomenon tends to occur.

  Further, in the methods proposed by Patent Documents 2 and 3, since the ratio of the conductive paste applied to the side surface portion to the jigs used for scraping is small, the conductive paste on the side surface portion is efficiently used. Therefore, the conductive paste film on the side surface portion becomes thick. As a result, in addition to the appearance problems, the amount of shrinkage of the conductive paste film is increased in the firing process, so that stress due to the shrinkage is applied to the ceramic electronic component, and external electric power is applied. Cracks are likely to occur in the outer peripheral portion of the chip-type electronic component starting from the extreme portion. The occurrence of cracks allows penetration of the plating solution and causes IR deterioration (DC resistance increase).

Furthermore, in the method described in Patent Document 4, the absorption action of the conductive paste by the open pores of the elastic body cannot always be made constant, and thus cannot be a complete measure. In particular, in a ceramic electronic component that has been miniaturized, the intended effect cannot be obtained with only a slight fluctuation in the amount of absorption.
Japanese Patent Laid-Open No. 10-32460 JP-A-8-130170 Japanese Patent No. 2873345 JP-A-2005-123407

  The subject of this invention is providing the ceramic electronic component which has a terminal electrode structure which can avoid IR degradation by plating solution penetration | invasion.

  Another object of the present invention is to provide a ceramic electronic component in which the film thickness of the terminal electrode is made constant, the outer shape is kept within the standard, and the occurrence of the tombstone phenomenon can be prevented.

In order to achieve the above-described problems, a ceramic electronic component according to the present invention includes a ceramic substrate, an internal electrode layer, and a terminal electrode. The ceramic base is a hexahedron, the internal electrode layer is embedded in the ceramic base, and at least one end is led out to a side surface of the ceramic base. The terminal electrode is continuously formed on the side surface from which one end of the internal electrode layer is led out and four surfaces adjacent to the side surface, and the side surface and the four surfaces intersect each other. When the minimum thickness of the corner is R, the length from the corner to the tip on the four surfaces is B, and the length in the longitudinal direction of the element body including the terminal electrode is L, 20.5 × 10 −2 ≦ B / L ≦ 28.5 × 10 −2 and 0.61 × 10 −2 ≦ R / L ≦ 0.98 × 10 −2 are satisfied.

  In the ceramic electronic component according to the present invention, terminal electrodes are provided on opposite ends of a ceramic base configured as a hexahedron. These terminal electrodes are connected to an internal electrode layer embedded in the ceramic substrate, and are used to derive the electrical characteristics acquired by the internal electrode layer to the outside. The terminal electrode is usually formed by applying a conductive paste on the side surface of the ceramic substrate and then performing electroplating thereon.

  In the above-described ceramic electronic component, since the conductive paste is applied to the side surface of a square hexahedral ceramic base, the thickness of the conductive paste applied to the corners of the ceramic base without any treatment. In the subsequent plating process, the plating solution enters the inside of the ceramic substrate from the thin corners of the film thickness and causes IR deterioration. This has already been described.

  As a means for solving this problem, in the present invention, in the structure in which the terminal electrode is formed continuously on the side surface of the hexahedral ceramic substrate and the four surfaces adjacent to the side surface, the side surface and the four surfaces are provided. When the minimum thickness of the intersecting corner is R, the length from the corner to the tip on the four surfaces is B, and the length in the longitudinal direction of the element body including the terminal electrode is L, the thickness R, the length The length B and the length L in the longitudinal direction of the element body including the terminal electrodes are set to satisfy the two conditional expressions described above. By satisfying the two conditional expressions described above, it is possible to prevent the plating solution from entering in the plating step.

  In addition, when the two conditional expressions described above are satisfied, the range of the amount of the conductive paste attached is indirectly limited in the dipping process, so that the conductive paste can be prevented from being excessively attached. The thickness of the terminal electrode finally obtained by plating is made constant, the outer shape is kept within the standard, and the occurrence of the tombstone phenomenon can be prevented.

  The two conditional expressions described above are composed of a thickness R, a length B, and a length L in the longitudinal direction of the element body including the terminal electrodes. The values of thickness R and length B are preferably in a range satisfying 4.0 μm ≦ R ≦ 10 μm and 180 μm ≦ B ≦ 260 μm.

  When the conductive paste is applied by the dipping process, the above-described conditional expressions of thickness R and length B (4.0 μm ≦ R ≦ 10 μm and 180 μm ≦ B ≦ 260 μm) are the thicknesses seen on the side surface of the terminal electrode. T affected. It is confirmed that the conditional expressions (4.0 μm ≦ R ≦ 10 μm and 180 μm ≦ B ≦ 260 μm) regarding the thickness R and the length B can be satisfied by setting the thickness T in the range of 43 μm ≦ T ≦ 60 μm. ing.

  As another preferred mode, the thickness R and the length B are in a range satisfying 12.4 μm ≦ R ≦ 20.0 μm and 398 μm ≦ B ≦ 572 μm. The range of the thickness T that can satisfy the conditional expressions (12.4 μm ≦ R ≦ 20.0 μm and 398 μm ≦ B ≦ 572 μm) of the thickness R and the length B described above is 88 μm ≦ T ≦ 124 μm. It has been confirmed.

  Details of the values of the thickness R, the length B, and the length L in the longitudinal direction of the element body including the terminal electrodes will be described later using data.

  In manufacturing the ceramic electronic component according to the present invention, the side surface of the ceramic substrate having the internal electrode layer is dipped in the electrode paste and pulled up. At that time, the thickness R and the length B are controlled by controlling the immersion depth. Thereafter, a plating process is performed to form a terminal electrode.

  The present invention is widely applicable to ceramic electronic components having terminal electrodes on a hexahedral ceramic base. In particular, it is useful for multilayer ceramic capacitors whose shape has been reduced in size and thickness.

As described above, according to the present invention, the following effects can be obtained.
(A) It is possible to provide a ceramic electronic component having a terminal electrode structure capable of avoiding IR deterioration due to penetration of a plating solution.
(B) It is possible to provide a ceramic electronic component in which the thickness of the terminal electrode is made constant, the outer shape is kept within the standard, and the occurrence of the tombstone phenomenon can be prevented.

  Other features of the present invention and the operational effects thereof will be described in more detail by way of examples with reference to the accompanying drawings.

  FIG. 1 is an external perspective view of a ceramic electronic component according to the present invention, FIG. 2 is an enlarged sectional view schematically showing the structure of a multilayer ceramic capacitor as a representative example of the ceramic electronic component according to the present invention, and FIG. FIG. 3 is an enlarged sectional view of an end of the multilayer ceramic capacitor shown in FIG. 2.

  Referring to the drawing, the ceramic electronic component according to the present invention includes a ceramic substrate 1, internal electrode layers 31 and 32, and terminal electrodes 21 and 22. The ceramic substrate 1 is a hexahedron having surfaces 11 to 16, and the internal electrode layers 31 and 322 are embedded in the ceramic substrate 1, and at least one end is led out to the side surfaces 11 and 12 of the ceramic substrate 1. The illustrated ceramic electronic component is a multilayer ceramic capacitor, and has a structure in which a large number of internal electrode layers 31 and 32 are embedded in the thickness direction of a ceramic substrate 1 made of a dielectric via the ceramic dielectric layer. . The composition of the ceramic substrate 1 is well known, and the shape, thickness, composition, and the like of the internal electrode layers 31 and 32 are well known.

  The terminal electrodes 21 and 22 are continuously formed on the side surfaces 11 and 12 from which one ends of the internal electrode layers 31 and 322 are led out, and the four surfaces 13 to 16 adjacent to the side surfaces 11 and 12. In the case of a multilayer ceramic capacitor, as is well known, the terminal electrodes 21 and 22 are provided symmetrically on the opposite side surfaces 11 and 12, and opposite ends of the adjacent internal electrode layers 31 and 32. Are respectively led to the side surfaces 11 and 12 of the ceramic substrate 1 and connected to the different terminal electrodes 21 and 22, respectively.

  The terminal electrodes 21 and 22 have a structure in which a second layer 212 and a third layer 213 are stacked on the first layer 211 as shown in an enlarged view in FIG. The first layer 211 is a portion to be a plating base layer for the second layer 212 and the third layer 213 that are normally formed as plating layers, and is configured by baking a conductive paste applied by an immersion method. It is a thing. The composition of the conductive paste belongs to a well-known technique.

  The second layer 212 and the third layer 213 are typically formed by a wet barrel plating method. Among these, the 2nd layer 212 has Ni as a main component, for example, and functions as a protective layer. The third layer 213 ensures solderability and contains, for example, Sn as a main component.

  In manufacturing the ceramic electronic component described above, first, as shown in FIG. 4, the side surface 11 or 12 of the ceramic substrate 1 is immersed in the electrode paste 6 supported by the support 5 so as to have an immersion depth X. And is pulled up in the direction of arrow F as shown in FIG. Thereafter, the electrode paste is dried and baked, followed by wet barrel plating. The ceramic electronic component shown in FIGS. 1 to 3 is obtained through such a process. In FIG. 2, reference symbol L indicates the total length of the ceramic electronic component, and reference symbol H indicates the maximum value of the terminal electrode thickness viewed on the surfaces 13 to 16.

  In the steps shown in FIGS. 4 and 5, the conductive paste is applied to the side surface of the square hexahedral ceramic substrate 1 and the like, so that no electrical treatment is performed at the corners of the ceramic substrate 1 if no treatment is performed. As described above, the coating thickness of the conductive paste is reduced, and in the subsequent plating process, the plating solution enters the inside of the ceramic substrate 1 from the thin corners of the film thickness and causes IR deterioration. .

As a means for solving this problem, in the present invention, the terminal electrodes 21 and 22 are continuous with the side surfaces 11 and 12 of the hexagonal ceramic substrate 1 and the four surfaces 13 to 16 adjacent to the side surfaces 11 and 12. In the structure in which the side surfaces 11 and 12 and the four surfaces 13 to 16 intersect, R is the minimum thickness of the corners, and B is the length from the corners to the tips on the four surfaces 13 to 16. When the total length of the ceramic electronic component is L, 20.5 × 10 −2 ≦ B / L ≦ 28.5 × 10 −2 and 0.61 × 10 −2 ≦ R / L ≦ 0.98 × It was made to satisfy 10-2 . By satisfying these two conditional expressions, it is possible to prevent the plating solution from entering in the plating step. And when satisfy | filling the two conditional expressions mentioned above, since the range of the adhesion amount of an electrically conductive paste is also indirectly limited in an immersion process, it can avoid that an electrically conductive paste adheres excessively. For this reason, the film thickness of the terminal electrodes 21 and 22 finally obtained by plating on them can be made constant, the outer shape can be kept within the standard, and the occurrence of chip standing can be prevented.

  Next, the effect of the embodiment of the ceramic electronic component according to the present invention will be described in comparison with that of the comparative example. Tables 1 and 2 show the immersion depth X, T / L (thickness / length in the longitudinal direction of the body including the terminal electrode), R / L (thickness / thickness) for Examples 1 to 13 and Comparative Examples 1 to 9. Length of element body including terminal electrode), B / L (length / length of element body including terminal electrode), H / L (thickness / length of element body including terminal electrode) ) Is a diagram showing data on a defect rate, chip standing, and a capacity reduction rate.

  The immersion depth X indicates the depth of immersion in the electrode paste 6 shown in FIG. The defect rate indicates the proportion of chips with reduced IR after the high temperature load test. The defect rate is due to the deterioration of the IR life due to the penetration of the plating solution. In order to determine the IR life, that is, a defective product, a voltage of 10 V was applied under the condition of a temperature of 85 ° C., and this was continued for 2 hours, and then the resistance value of the ceramic substrate 1 was measured. Things were considered defective. Chip standing was determined by simulation. The multilayer ceramic capacitors subjected to the measurement have an outer dimension (nominal) of 1.0 × 0.5 × 0.5 mm in Table 1, and an outer dimension (nominal) of 2.0 × 1. 35 x 1.35 mm. For each of Comparative Examples 1 to 9 and Examples 1 to 12, 100 multilayer ceramic capacitors were prepared and subjected to measurement.

  In the table, W blot (double blot) is a step of flattening the terminal electrode by forming the terminal electrode by dipping and then pressing it twice against a flat plate (blot process).

From Table 1 and Table 2, 20.5 × 10 −2 ≦ B / L ≦ 28.5 × 10 −2 and 0.61 × 10 −2 ≦ R / L ≦ 0.98 × 10 −2 In Examples 1 to 12 that satisfy the conditional expression, the defect rate was 0% in all Examples. Furthermore, also about the capacity | capacitance fall rate, in Examples 1-12, the favorable numerical value of 10% or less was shown. In Examples 1 to 8, no chip standing was observed.

On the other hand, the conditional expressions of 20.5 × 10 −2 ≦ B / L ≦ 28.5 × 10 −2 and 0.61 × 10 −2 ≦ R / L ≦ 0.98 × 10 −2 are obtained. In Comparative Examples 1 to 3 and 5 to 8 which are not satisfied, a low numerical value of 0 to 5% is shown only by looking at the capacity reduction rate, so it seems to be a good result at first glance. However, since the defect rate shows a high value of 10 to 100%, it can be seen that the ceramic part is in a poorly used state. Further, Comparative Examples 4 and 9 having a defect rate of 0% also showed a high value of 11% for the capacity reduction rate, so that it was confirmed that the ceramic parts were similarly poorly used. Furthermore, it was found that Comparative Example 4 cannot prevent the occurrence of chip standing.

From the above, implementation satisfying the conditional expressions of 0.5 × 10 −2 ≦ B / L ≦ 28.5 × 10 −2 and 0.61 × 10 −2 ≦ R / L ≦ 0.98 × 10 −2 The ceramic electronic parts of Examples 1 to 12 have desirable results for both the defect rate and the capacity reduction rate, and it is possible to avoid IR deterioration due to penetration of the plating solution and to prevent the occurrence of the tombstone phenomenon. There was found.

  Tables 1 and 2 show the same results in the same region of B / L and R / L, although they were performed using ceramic electronic parts having different external dimensions. From this, it is considered that the avoidance of IR degradation and the prevention of the occurrence of the tombstone phenomenon occur depending on the values of B / L and R / L regardless of the substrate dimensions of the ceramic electronic component to be used.

  Tables 3 and 4 show the data of Tables 1 and 2 for the immersion depth X, the immersion depth X, the thickness T, the thickness R, the length B, and the thickness H, respectively. The defect rate, chip standing, and capacity reduction rate are displayed in duplicate with Tables 1 and 2.

Referring to Table 3, the minimum thickness R at the corner is in the range of 1.3 μm to 3.8 μm,
In Comparative Examples 1 to 3, in which the length B from the corners to the tips on the four surfaces 13 to 16 is in the range of 100 μm to 179 μm and does not satisfy the conditional expression of the present invention, the defect rate is 5 at the minimum. % (Comparative Example 3), reaching 100% (Comparative Example 1) at the maximum.

  Further, the thickness R at the corner is 11.1 μm, the length B from the corner to the tip on the four surfaces 13 to 16 is 283 μm, and Comparative Example 4 that does not satisfy the conditional expression of the present invention is Will occur.

  On the other hand, in Examples 1 to 8 in which the thickness R and the length B are within the scope of the present invention, the defect rate is zero and no chip standing occurs. The capacity reduction rate is also within the range of 2 to 10%. This is presumed that the gathering R and the length B are appropriately selected, so that the penetration of the plating solution is prevented in the wet barrel plating process, and the defect rate and the capacity reduction rate are improved. Further, since the thickness R, the length B, and the thickness T are appropriate, it is presumed that the occurrence of chip standing is prevented.

  Looking at Table 3, the increase / decrease in the thickness R and the length B and the increase / decrease in the thickness T have a correlation, and within a range where the thickness R and the length B satisfy the above-described conditional expression, the thickness T is 43 μm ≦ T ≦ 60 μm is satisfied.

  The thickness R and the length B change corresponding to the immersion depth X. This means that the immersion depth X may be controlled in FIG. 4 to ensure appropriate values for the thickness R and the length B.

Referring to Table 4, the minimum thickness R at the corner is in the range of 3.0 μm to 9.5 μm,
In Comparative Examples 5 to 8, in which the length B from the corners to the tips on the four surfaces 13 to 16 is in the range of 99 μm to 348 μm and does not satisfy the conditional expression of the present invention, the defect rate is at least 10 % (Comparative Example 8), up to 100% (Comparative Example 5).

  On the other hand, in Examples 9 to 13 in which the thickness R and the length B are within the scope of the present invention, the defect rate is zero and no chip standing occurs. The capacity reduction rate also falls within the range of 6 to 10%. This is presumed that since the gathering R and the length B are appropriately selected, infiltration of the plating solution is prevented in the wet barrel plating process, and the defect rate and the capacity reduction rate are improved. Further, since the thickness R, the length B, and the thickness T are appropriate, it is presumed that the occurrence of chip standing is prevented.

  As shown in Table 4, the increase / decrease in the thickness R and the length B and the increase / decrease in the thickness T are in a correlation, and within a range where the thickness R and the length B satisfy the above-described conditional expression, the thickness T is 88 μm ≦ T ≦ It satisfies 124 μm.

  The thickness R and the length B change corresponding to the immersion depth X. This means that the immersion depth X may be controlled in FIG. 4 to ensure appropriate values for the thickness R and the length B.

  Although the contents of the present invention have been specifically described above with reference to the preferred embodiments, it is obvious that those skilled in the art can take various modifications based on the basic technical idea and teachings of the present invention. It is.

1 is an external perspective view schematically showing the structure of a multilayer ceramic capacitor according to the present invention. FIG. 2 is a partially enlarged cross-sectional view of the multilayer ceramic capacitor shown in FIG. 1. FIG. 3 is a cross-sectional view showing a further enlarged end portion of the multilayer ceramic capacitor shown in FIG. 2. It is a figure explaining the terminal electrode formation method of the ceramic electronic component which concerns on this invention. It is a figure explaining the process after the process shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Ceramic base | substrate 21 Terminal electrode 22 Terminal electrode 31 Internal electrode layer 32 Internal electrode layer

Claims (7)

  1. A ceramic electronic component including a ceramic substrate, an internal electrode layer, and a terminal electrode,
    The ceramic substrate is a hexahedron,
    The internal electrode layer is embedded in the ceramic base, and at least one end is led out to a side surface of the ceramic base,
    The terminal electrode is continuously formed on the side surface from which one end of the internal electrode layer is led out and four surfaces adjacent to the side surface, and the side surface and the four surfaces intersect each other. The minimum thickness of the corner portion is R, the length from the corner portion to the tip on the four surfaces is B, and the length L in the element body longitudinal direction including the terminal electrode is:
    20.5 × 10 −2 ≦ B / L ≦ 28.5 × 10 −2 , and
    0.61 × 10 −2 ≦ R / L ≦ 0.98 × 10 −2
    Meet ceramic electronic components.
  2. The ceramic electronic component according to claim 1,
    4.0 μm ≦ R ≦ 10 μm, and
    180μm ≦ B ≦ 260μm
    Meet the ceramic electronic parts.
  3.   3. The ceramic electronic component according to claim 2, wherein the terminal electrode has a thickness T as viewed on the side surface of 43 μm ≦ T ≦ 60 μm.
  4. The ceramic electronic component according to claim 1,
    12.4 μm ≦ R ≦ 20.0 μm, and
    398 μm ≦ B ≦ 572 μm
    Meet the ceramic electronic parts.
  5.   5. The ceramic electronic component according to claim 4, wherein the terminal electrode has a thickness T as viewed on the side surface of 88 μm ≦ T ≦ 124 μm.
  6.   6. The ceramic electronic component according to claim 1, wherein the ceramic electronic component is a multilayer ceramic capacitor.
  7. A method of manufacturing a ceramic electronic component according to any one of claims 1 to 6,
    The side surface side of the ceramic substrate having the internal electrode layer is dipped in an electrode paste and pulled up, and at that time, the thickness R is controlled by controlling the immersion depth,
    Thereafter, plating is performed to form the terminal electrode.
    A manufacturing method including a process.
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109238A (en) * 2008-10-31 2010-05-13 Murata Mfg Co Ltd Ceramic electronic component
JP2013149939A (en) * 2012-01-18 2013-08-01 Samsung Electro-Mechanics Co Ltd Multilayer ceramic electronic component and fabrication method thereof
JP2014183186A (en) * 2013-03-19 2014-09-29 Taiyo Yuden Co Ltd Low height multilayer ceramic capacitor
US9087644B2 (en) 2012-01-18 2015-07-21 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component and fabrication method thereof
US9190207B2 (en) 2013-02-20 2015-11-17 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component having external electrodes which include a metal layer and conductive resin layer
JP2016032091A (en) * 2014-07-25 2016-03-07 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component
US20160240316A1 (en) * 2015-02-13 2016-08-18 Tdk Corporation Multilayer capacitor

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0837136A (en) * 1994-07-25 1996-02-06 Matsushita Electric Ind Co Ltd Method for forming electrode of electronic part
JP2000058374A (en) * 1998-08-13 2000-02-25 Murata Mfg Co Ltd Electronic component and manufacture thereof
JP2001155962A (en) * 1999-11-29 2001-06-08 Kyocera Corp Feed-through capacitor
JP2001210545A (en) * 2000-01-26 2001-08-03 Murata Mfg Co Ltd Chip electrical component and chip capacitor
JP2001267132A (en) * 2000-03-14 2001-09-28 Matsushita Electric Ind Co Ltd Electronic component and radio terminal device
JP2002208516A (en) * 2001-01-11 2002-07-26 Nec Tokin Corp Laminated impedance device
JP2002298649A (en) * 2001-03-29 2002-10-11 Kyocera Corp Conductive paste and chip type electronic component using the same
JP2003347153A (en) * 2002-05-22 2003-12-05 Murata Mfg Co Ltd Method for manufacturing electronic component
JP2004259990A (en) * 2003-02-26 2004-09-16 Kyocera Corp Method for manufacturing ceramic capacitor of stacked structure
JP2005019921A (en) * 2003-06-30 2005-01-20 Tdk Corp Method for forming external electrode, and electronic component
JP2005123407A (en) * 2003-10-16 2005-05-12 Murata Mfg Co Ltd Method for fabricating chip-type electronic component external electrode

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0837136A (en) * 1994-07-25 1996-02-06 Matsushita Electric Ind Co Ltd Method for forming electrode of electronic part
JP2000058374A (en) * 1998-08-13 2000-02-25 Murata Mfg Co Ltd Electronic component and manufacture thereof
JP2001155962A (en) * 1999-11-29 2001-06-08 Kyocera Corp Feed-through capacitor
JP2001210545A (en) * 2000-01-26 2001-08-03 Murata Mfg Co Ltd Chip electrical component and chip capacitor
JP2001267132A (en) * 2000-03-14 2001-09-28 Matsushita Electric Ind Co Ltd Electronic component and radio terminal device
JP2002208516A (en) * 2001-01-11 2002-07-26 Nec Tokin Corp Laminated impedance device
JP2002298649A (en) * 2001-03-29 2002-10-11 Kyocera Corp Conductive paste and chip type electronic component using the same
JP2003347153A (en) * 2002-05-22 2003-12-05 Murata Mfg Co Ltd Method for manufacturing electronic component
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US9190207B2 (en) 2013-02-20 2015-11-17 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component having external electrodes which include a metal layer and conductive resin layer
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JP2016032091A (en) * 2014-07-25 2016-03-07 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component
US9412520B2 (en) 2014-07-25 2016-08-09 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic electronic component
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