JP2008085392A - High-frequency power amplifier circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-frequency power amplifier circuit which has an economically advantageous constitution. <P>SOLUTION: When a high-frequency power MOS-FET 11 enters a fault mode of a gate-drain short circuit and a high voltage that exceeds a set voltage is applied to a voltage-limiting varistor 13, the voltage-limiting varistor 13 discharges an applied excessive voltage. With the discharge current thereof, an overcurrent protecting fuse 14 disconnects the current path between a gate electrode (G) and a gate pulse input terminal (Tgb). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a high-frequency power amplifier circuit using a high-frequency power MOS-FET.

  In a high frequency power amplifier circuit using a high frequency power MOS • FET, when the output pulse width is increased, the idle current (ΔID) flowing through the drain increases due to the characteristics (transient thermal resistance) of the power MOS • FET. As the self-heating increases, the drain current (ID) continues to rise and eventually exceeds the SOA region (Safe Operating Area), leading to destruction of the power MOS FET. For this reason, conventionally, when configuring a high-frequency high-frequency power amplifier circuit for obtaining a high-frequency power amplification output of several kilowatts to several tens of kilowatts, it is selected according to the required output power value, for example, about several tens of kilowatts. A large number of high-frequency power MOS • FETs are connected in parallel, and each of these power MOS • FETs is operated in the SOA region.

  The high-frequency power MOS-FET used in this type of circuit has an insulating portion made of ceramic, and an insulating material such as resin is not interposed in the die portion, so the failure mode is open between the gate and the drain. The high-frequency power MOS-FET using ceramic for the insulating part has a very high product cost compared to the low-frequency power MOS-FET using a mold resin for the insulating part. In an apparatus that requires a high-power type high-frequency power amplifier circuit using several tens of devices, there is a problem that the economic burden is large.

  In recent years, instead of high-frequency power MOS-FETs using ceramics for insulating parts, high-frequency power MOS-FETs using molded resin for insulating parts have been provided at low cost.

  However, this type of high-frequency power MOS-FET using a mold resin molding includes a gate-drain short circuit in the failure mode, and when the gate-drain short circuit occurs, the hundreds to several tens applied to the drain electrode are applied. A power supply voltage for operation of 100 volts (= drain voltage; hereinafter referred to as VDD) spills into the gate electrode, and the return current due to this sneak flows into the gate bias circuit that handles a minute current of about several volts, and includes the gate bias circuit. It will destroy the circuit.

With regard to this type of overcurrent protection, an overcurrent protection circuit is known in which when a current value of a predetermined current path exceeds a threshold value, the current path is interrupted by a fuse.
JP 2001-145339 A JP-A-6-245502

  As described above, in a high frequency power amplifier circuit using a high frequency power MOS • FET, depending on the type of the power MOS • FET, the high voltage VDD applied to the drain electrode wraps around the gate electrode, and the return due to this wraparound There is a problem that current flows to a gate bias circuit that handles low voltage and low current, and peripheral circuits including the gate bias circuit are destroyed.

  The present invention solves the above-described problems, and an object thereof is to provide a high-frequency power amplifier circuit having an economically advantageous configuration.

  The present invention is a high frequency power amplifier circuit using a power MOS • FET, wherein a gate bias protection circuit for suppressing a return current flowing from the drain to the gate bias circuit is provided in the gate bias circuit of the power MOS • FET. And

  Furthermore, the present invention is characterized in that an overcurrent protection circuit is provided in a VDD supply circuit that supplies an operating power supply voltage (VDD) of hundreds to hundreds of volts to the drain electrode of the power MOS FET.

  By incorporating the above-described circuit, peripheral circuits including a gate bias circuit can be protected even when a short circuit occurs between the gate and drain depending on the type of power MOS FET used. This makes it possible to minimize the damage to other circuits against various failure modes of the power MOS • FET, and at the same time economically advantageous high-frequency high-frequency power amplification using inexpensive power MOS • FETs A circuit can be realized.

  Furthermore, the present invention is characterized in that, in addition to the protection circuit, a gate bias circuit for supplying a gate pulse having a waveform with a potential gradually decreasing to the gate electrode of the power MOS • FET is provided.

  This enables and implements efficient power amplification with a wide pulse width in a high-power high-frequency power amplifier circuit using a plurality of power MOS-FETs that intermittently perform high-frequency power amplification by pulse operation. By reducing the number of power MOS / FETs, it is possible to realize a high-power, high-frequency, high-frequency power amplifier circuit that is more economical, while minimizing damage to other circuits against various failure modes of the power MOS / FET. it can.

  According to the present invention, a high power type high frequency power amplifier circuit having an economically advantageous configuration can be easily realized.

  Embodiments of the present invention will be described below with reference to the drawings.

  A configuration of a high-frequency power amplifier circuit according to an embodiment of the present invention is shown in FIG.

  The high frequency power amplifier circuit according to the embodiment of the present invention includes a plurality of high frequency power MOSFETs 11, 11,... And overcurrent protection provided corresponding to each of the high frequency power MOSFETs 11, 11,. The fuses 12 and 14, a voltage limiting varistor 13, a voltage / current limiting resistor 15, and a photocoupler 16 are provided.

  Among the above components, the voltage limiting varistor 13, the overcurrent protection fuse 14, and the voltage / current limiting resistor 15 constitute a gate bias protection circuit for the high frequency power MOS • FET 11. The overcurrent protection fuse 12 constitutes an overcurrent protection circuit (hereinafter referred to as an ID overcurrent protection circuit) against the drain current (ID) of the high-frequency power MOS • FET 11. The photocoupler 16 constitutes an overcurrent detection circuit for the drain current (ID) of the high-frequency power MOS • FET 11.

  The high-frequency power MOS • FET 11 is a main component of the high-frequency power amplifier, and the gate pulse (GP) input to the gate pulse input terminal (Tgb) is biased to the gate terminal (G) via the gate bias output buffer 20. A high-frequency signal (for example, as shown in FIG. 2, intermittently pulse-width modulated) is supplied to the gate terminal (G) by supplying VDD as an operation power supply voltage to the drain electrode (D). A sinusoidal high-frequency signal RF (in)) is amplified, for example, by class A power and output from the drain electrode (D).

  At this time, when the high-frequency power MOS FET 11 is in a normal operation state, a drain current (ID) accompanying VDD applied to the drain electrode (D) flows to the source electrode (S).

  When the high-frequency power MOS FET 11 is in a failure mode in which a gate-drain short circuit occurs, VDD applied to the drain electrode (D) generates a gate pulse (GP) via the gate electrode (G). Go around the circuit and destroy the gate bias circuit and its peripheral circuits. In the embodiment of the present invention, a gate having a voltage limiting varistor 13, an overcurrent protection fuse 14, and a voltage / current limiting resistor 15 between the gate electrode (G) and the gate pulse input terminal (Tgb). A bias protection circuit is interposed. This gate bias protection circuit avoids the above circuit breakdown. When a high voltage exceeding a set voltage (several volts) is applied to the voltage limiting varistor 13, the voltage limiting varistor 13 discharges the applied excess voltage to the ground (ground), and this discharge current causes an overcurrent. The protective fuse 14 interrupts the current path between the gate electrode (G) and the gate pulse input terminal (Tgb). As a result, the gate bias circuit that supplies the gate pulse (GP) to the gate pulse input terminal (Tgb) is reliably protected against the failure mode of the short circuit between the gate and the drain of the high-frequency power MOS • FET 11. Further, when the high-frequency power MOS • FET 11 falls into a failure mode of a short circuit between the gate and the drain, the drain current (D) becomes an overcurrent, and the overcurrent protection fuse 12 is connected between the VDD supply terminal and the drain electrode (D). The VDD supply path is cut off, and the supply of VDD to the drain electrode (D) is cut off. Further, along with this, the output number of the photocoupler 16 constituting the overcurrent detection circuit changes from the Low level to the High level, and the fact that the overcurrent has occurred is notified to the outside.

  By incorporating the gate bias protection circuit and the ID overcurrent detection circuit as described above in the high frequency power amplifier, the gate bias circuit can be used even when a short circuit occurs between the gate and the drain depending on the type of power MOS FET used. It is possible to protect peripheral circuits including As a result, it is possible to minimize the spread of other power MOS / FET failure modes to other circuits, and a high-power high-frequency power amplifier circuit with an economically advantageous configuration using inexpensive power MOS / FETs. Can be realized.

  FIG. 2 shows various configuration examples of the high-frequency power amplifier according to the embodiment of the present invention. In the configuration shown in FIG. 1, the high-frequency power amplifier is realized by a class A single power amplifier circuit. On the other hand, in the configuration shown in FIG. 2, the high frequency power amplifier is realized by a class AB push-pull power amplifier circuit.

  In the configuration shown in FIG. 2, the high-frequency power amplifier 10 includes a high-frequency signal input terminal Tin, a pair of high-frequency power amplification power MOS FETs 11a and 11b constituting a class AB push-pull amplifier circuit, and a high-frequency signal output. A terminal Tout, a circuit for supplying a high-frequency signal RF (in) input to the high-frequency signal input terminal Tin to the gate electrodes (G) of the power MOS FETs 11a and 11b, and a gate input to the gate pulse input terminal (Tgb) A circuit for supplying power to the gate electrodes (G) of the power MOS FETs 11a and 11b via the pulse overcurrent protection fuse 14 and the choke coil 17 and a high voltage (for example, 130˜) to the drain electrodes (D) of the power MOS FETs 11a and 11b. A circuit for supplying an operating power supply (VDD) for power amplification of about 150 V) and a power MOS FET 1 a, 11b configured to and a circuit for outputting the power amplified radio frequency signal RF (out) to the high-frequency signal output terminal Tout in. In the above configuration, the high-frequency signal RF (in) input to the high-frequency signal input terminal Tin is amplified by the power MOS FETs 11a and 11b that perform push-pull operation at class AB, and the high-frequency signal RF is output from the high-frequency signal output terminal Tout. (Out) is output.

  FIG. 3 shows a configuration example of a waveform shaping circuit provided in a gate bias circuit that supplies a gate pulse (GP) to a gate pulse input terminal (Tgb). Here, the high-frequency signal RF ( In), a gate pulse GP (in) having a predetermined width synchronized with in) is input, waveform-shaped, and supplied to the high-frequency power amplifier 10 via the overcurrent protection fuse 14 as a gate bias.

  In FIG. 3, a gate pulse waveform shaping circuit 30 provided in the gate bias circuit shapes the gate pulse input to the gate pulse input terminal 31 and supplies it to the amplifier circuit 10 shown in FIG. The gate pulse input terminal 31 is supplied with a gate pulse GP (in) having a predetermined width synchronized with the high frequency signal RF (in).

  The gate pulse waveform shaping circuit 30 includes a CR time constant circuit 32 that generates an integrated waveform of the gate pulse GP (in) input to the gate pulse input terminal 31 and a gate pulse GP (in) input to the gate pulse input terminal 31. The switching circuit 33 that validates the output of the integrated waveform generated by the CR time constant circuit 32, the operational amplifier 34 that inverts and amplifies the output of the CR time constant circuit 32, and the output gate pulse GP (out) And an arithmetic circuit element 35 that adjusts the width of the high frequency signal RF (in) within a range not exceeding the signal width. The gate pulse GP (out) after waveform shaping output to the output terminal (output terminal of the arithmetic circuit element 35) 36 of the gate pulse waveform shaping circuit 30 is powered through a variable resistor (VR) for gate bias adjustment. A gate bias signal is supplied to the gate electrodes (G) of the MOS • FETs 11a and 11b.

  The waveform of the gate pulse GP (out) output from the gate pulse waveform shaping circuit 30 is shown in FIG. 4A, and the power MOS FETs 11a and 11b and the drains associated with the waveform shaped gate pulse GP (out) are shown. The current (ID) waveform is shown in FIG.

  As shown in FIG. 4A, the gate pulse GP (out) output from the gate pulse waveform shaping circuit 30 is a signal width (pulse width modulation) of the high-frequency signal RF (in) input to the high-frequency signal input terminal Tin. This is a pulse waveform in which the potential gradually decreases (gradually decreases) that is expanded within a range not exceeding the width of the generated high-frequency signal. In FIG. 4B, ΔID indicated by a broken line is an idle current included in the drain currents (ID) of the power MOS FETs 11a and 11b, and a rising change portion is an increase (gradual increment) of the idle current (ΔID). ). The gate pulse GP (out) shown in FIG. 4A cancels the increase (gradual increase) of the idle current (ΔID) shown by the broken line from the drain current (ID) shown in FIG. In other words, the pulse is a pulse whose potential is gradually decreased (so that the increase in the idle current (ΔID) is apparently removed from the idle current (ΔID) included in the drain current (ID)) and whose width is expanded. .

  In the above configuration, the high frequency signal RF (in) is supplied to the high frequency signal input terminal Tin of the amplifier circuit 10, and the gate pulse GP (in) is supplied to the gate pulse input terminal 31 of the waveform shaping circuit 30. The amplifier circuit 10 receives the gate bias of the waveform shaping circuit 30 and amplifies the high frequency signal RF (in) supplied to the high frequency signal input terminal Tin by high frequency power.

  At this time, the waveform shaping circuit 30 applies the gate pulse GP (in) input to the gate pulse input end 31 within a range not exceeding the signal width of the high-frequency signal RF (in) as shown in FIG. A gate pulse GP (out) whose width is increased and whose potential gradually decreases is output.

  In the waveform shaping circuit 30, the gate pulse GP (in) input to the gate pulse input terminal 31 is integrated by the CR time constant circuit 32, and the integrated waveform is applied to the operational amplifier over the switch-off period of the switching circuit 33. 34 is input to the negative (−) input terminal of 34 and inverted and amplified, and further, the pulse width is adjusted by the arithmetic circuit element 35 and output from the output terminal 36 as a gate pulse GP (out) after waveform shaping.

  The gate pulse GP (in) waveform-shaped by the waveform shaping circuit 30 as shown in FIG. 2A includes a variable resistor (VR) for gate bias adjustment, a gate pulse input terminal (Tgb), and overcurrent protection. The power is supplied to the gate electrodes (G) of the power MOSFETs 11a and 11b provided in the high-frequency power amplifier 10 shown in FIG.

  In the amplifier circuit 10, the high frequency signal RF (in) input to the high frequency signal input terminal Tin is amplified by the power MOS • FETs 11 a and 11 b and output from the high frequency signal output terminal 15 as the high frequency signal RF (out). The At this time, the power MOSFETs 11a and 11b have a pulse waveform with a gradually decreasing potential shown in FIG. 4A, which is input from the waveform shaping circuit 30 via the variable resistor (VR) for gate bias adjustment. The gate pulse GP (out) is received by the gate electrode (G), and the pulse signal is used as a gate bias to amplify the high frequency signal RF (in) input to the high frequency signal input terminal Tin by class AB push-pull amplification.

  Thus, a compensation circuit that apparently cancels the gradual increase of the idle current (ΔID) is provided in the gate bias of the power MOS • FETs 11a and 11b, and the gates of the power MOS • FETs 11a and 11b By inputting a gate pulse with reverse characteristics that suppresses the increase in drain current (ID) due to transient thermal resistance, the pulse width can be expanded compared to the case without the compensation circuit, and efficient power amplification Can be done. In particular, when configuring a high-frequency high-frequency power amplifier circuit as described above, it is possible to provide an efficient and economically advantageous high-frequency power amplifier circuit by reducing the number of power MOS-FETs mounted. Furthermore, the above-described gate bias protection circuit and ID overcurrent protection circuit are provided in the high-frequency power amplifier 10 to protect the gate bias circuit including the waveform shaping circuit 30 from the failure mode of the short circuit between the gate and the drain. It is possible to avoid the catastrophic circuit function destruction due to the spread of the above and minimize the damage caused by the failure mode.

The figure which shows the structure of the high frequency power amplifier circuit which concerns on embodiment of this invention. The figure which shows the other structural example of the high frequency power amplification part in the said embodiment. The figure which shows the structure of the waveform shaping circuit in the said embodiment. The figure which shows the signal waveform of the gate pulse and drain current in the said embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... High frequency power amplifier part 11, 11a, 11b ... High frequency power MOS * FET, 12 ... Overcurrent protection fuse of ID overcurrent protection circuit, 13 ... Voltage limiter varistor, 14 ... Overcurrent protection of gate bias protection circuit Fuse, 15 ... Voltage / current limiting resistor, 16 ... Photocoupler, 17 ... Choke coil, 20 ... Gate bias output buffer, 30 ... Waveform shaping circuit, 31 ... Gate pulse input terminal, 32 ... CR time constant circuit, 33 ... Switching Circuit, 34 ... operational amplifier, 35 ... arithmetic circuit element.

Claims (8)

In a high frequency power amplifier circuit using power MOS / FET,
A high-frequency power amplifier circuit comprising a gate bias protection circuit for suppressing a return current flowing from the drain to the gate bias circuit in the gate bias circuit of the power MOS • FET.   2. The high frequency power amplifier circuit according to claim 1, wherein an overcurrent protection circuit is provided in a drain voltage supply circuit of the power MOS • FET.   2. The high frequency power amplifier circuit according to claim 1, wherein the gate bias protection circuit includes an overcurrent protection fuse and a voltage limiting varistor.   3. The high frequency power amplifier circuit according to claim 2, further comprising an overcurrent detection circuit for detecting an overcurrent state of a drain current in the drain voltage supply circuit of the power MOS FET.   2. The high frequency power amplifier circuit according to claim 1, wherein a gate pulse for intermittently amplifying the high frequency power of the power MOS • FET is supplied to the gate electrode of the power MOS • FET.   6. The high frequency power amplifier circuit according to claim 5, wherein the gate pulse is a pulse having a waveform shape in which the potential gradually decreases so as to cancel the increment of the idle current from the drain current of the power MOS FET.   7. A high frequency power amplifier circuit according to claim 6, comprising a plurality of sets of power amplifying units using the power MOS-FETs, wherein the power MOS-FETs of the respective power amplifying units receive the gate pulse in common and control the gate bias. .   The high-frequency power amplifier circuit according to claim 7, wherein the power amplifier section includes a pair of power MOS FETs that perform power amplification by a class AB push-pull operation.

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