JP2008083320A - Electro-optical device, driving method thereof, and electronic device - Google Patents

Electro-optical device, driving method thereof, and electronic device Download PDF

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JP2008083320A
JP2008083320A JP2006262309A JP2006262309A JP2008083320A JP 2008083320 A JP2008083320 A JP 2008083320A JP 2006262309 A JP2006262309 A JP 2006262309A JP 2006262309 A JP2006262309 A JP 2006262309A JP 2008083320 A JP2008083320 A JP 2008083320A
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JP2008083320A5 (en
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Tomio Ikegami
富雄 池上
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Seiko Epson Corp
セイコーエプソン株式会社
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<P>PROBLEM TO BE SOLVED: To provide an electro-optical device capable of reducing power consumption, and a driving method thereof in the line-inversion or the dot inversion system. <P>SOLUTION: The electro-optical device includes a plurality of pixel circuits P11-Pnm in correspondence with an intersection of a scan line 20 and a data line 10. The data line 10 consists of a set of the first data line 10a and the second data line 10b. A switch SW distributes a data signal X1 to the first data line 10a and the second data line 10b for each horizontal scan period. The polarity of the first data signal X1a and the polarity of the second data signal X1b are different from each other. In the pixel circuits P11 and P21 adjoining in the data line direction, the pixel circuit P11 is electrically connected to the first data line 10a, and the pixel circuit P12 is electrically connected to the second data line 10b. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、液晶などの電気光学物質を備えた電気光学装置その駆動方法および電子機器に関する。   The present invention relates to an electro-optical device including an electro-optical material such as liquid crystal, a driving method thereof, and an electronic apparatus.

液晶の透過率の変化により表示を行う電気光学装置は、情報処理機器やテレビジョンなどの表示装置して広く用いられている。この表示装置では、、行方向に延在する走査線と、列方向に延在するデータ線との交差に対応して画素電極が形成される。また、当該交差部分にあって画素電極とデータ線との間に、走査線に供給される走査信号にしたがってオンオフする薄膜トランジスタなどの画素スイッチが介挿される。さらに、液晶を介して画素電極と対向するように対向電極が設けられる。   An electro-optical device that performs display by changing the transmittance of liquid crystal is widely used as a display device such as an information processing device or a television. In this display device, pixel electrodes are formed corresponding to intersections between scanning lines extending in the row direction and data lines extending in the column direction. In addition, a pixel switch such as a thin film transistor that is turned on and off in accordance with a scanning signal supplied to the scanning line is interposed between the pixel electrode and the data line at the intersection. Further, a counter electrode is provided so as to face the pixel electrode through the liquid crystal.

このような構成において、走査線にオン電圧の走査信号が印加されると、当該走査線に接続された画素スイッチがオン状態となる。このオン状態の際に、データ線に、階調(濃度)に応じたデータ信号を供給すると、当該データ信号は画素スイッチを介して画素電極に印加されるので、当該画素電極および対向電極の間に挟持された電気光学物質には、当該データ信号に応じた電圧が印加されることになる。これによって該電気光学物質は電気光学的に変化する結果、画素における透過光量、反射光量または発光量(いずれにせよ、観察者側に視認される光量)が、画素電極に印加されたデータ信号の電圧に応じたものとなる。したがって、このような制御を画素毎に実行することによって、所定の表示が可能になる。   In such a configuration, when an on-voltage scanning signal is applied to a scanning line, a pixel switch connected to the scanning line is turned on. When a data signal corresponding to the gradation (density) is supplied to the data line in this ON state, the data signal is applied to the pixel electrode via the pixel switch, and thus between the pixel electrode and the counter electrode. A voltage corresponding to the data signal is applied to the electro-optical material sandwiched between the two. As a result, the electro-optical material changes electro-optically, and as a result, the transmitted light amount, reflected light amount, or light emission amount in the pixel (in any case, the light amount visually recognized by the observer) is the data signal applied to the pixel electrode. It depends on the voltage. Therefore, a predetermined display can be performed by executing such control for each pixel.

液晶には、直流電圧を印加するとその組成が変化し、焼きつきなどの品質劣化を生じるといった問題がある。そこで、所定の周期で、対向電極の電位を基準として正極性の電圧と負極性の電圧とを印加する交流駆動が行われる。交流駆動の方式としては、1水平走査期間ごとに印加電圧の極性を反転するライン反転の他に、上下左右隣り合う画素全てに逆の極性が印加されるドット反転が知られている(例えば、特許文献1)。ドット反転の駆動方法では、液晶の劣化を抑制しつつフリッカを低減することができる。
特開平2003−150080号公報
液晶には、直流電圧を印加するとその組成が変化し、焼きつきなどの品質劣化を生じるといった問題がある。そこで、所定の周期で、対向電極の電位を基準として正極性の電圧と負極性の電圧とを印加する交流駆動が行われる。交流駆動の方式としては、1水平走査期間ごとに印加電圧の極性を反転するライン反転の他に、上下左右隣り合う画素全てに逆の極性が印加されるドット反転が知られている(例えば、特許文献1)。ドット反転の駆動方法では、液晶の劣化を抑制しつつフリッカを低減することができる。
特開平2003−150080号公報
The liquid crystal has a problem that when a DC voltage is applied, its composition changes and quality deterioration such as image sticking occurs. Therefore, AC driving is performed by applying a positive voltage and a negative voltage with reference to the potential of the counter electrode at a predetermined cycle. As an AC driving method, in addition to line inversion that inverts the polarity of an applied voltage every horizontal scanning period, dot inversion in which a reverse polarity is applied to all the pixels that are vertically and horizontally adjacent to each other is known (for example, Patent Document 1). In the dot inversion driving method, flicker can be reduced while suppressing deterioration of the liquid crystal. The liquid crystal has a problem that when a DC voltage is applied, its composition changes and quality deterioration such as image sticking occurs. Therefore, AC driving is performed by applying a positive voltage and a negative voltage with reference to the potential of the counter electrode. at a predetermined cycle. As an AC driving method, in addition to line inversion that inverts the polarity of an applied voltage every horizontal scanning period, dot inversion in which a reverse polarity is applied to all the pixels that are vertically and horizontally adjacent to each other is known (for example, Patent Document 1). In the dot inversion driving method, flicker can be reduced while suppressing deterioration of the liquid crystal.
Japanese Patent Laid-Open No. 2003-150080 Japanese Patent Laid-Open No. 2003-150080

しかしながら、ライン反転やドット反転の駆動方法では1水平走査期間ごとに液晶に印加する電圧の極性を反転する必要があるため、データ信号の極性を1水平走査期間ごとに反転する必要があった。データ信号はデータ線を介して画素回路に供給されるが、データ線には寄生容量が付随するため、データ信号を供給するには容量性の負荷を駆動する必要がある。このため、1水平走査期間ごとにデータ信号の極性を反転すると、消費電力が増大するといった問題があった。   However, in the line inversion or dot inversion driving method, it is necessary to invert the polarity of the voltage applied to the liquid crystal every one horizontal scanning period, and thus it is necessary to invert the polarity of the data signal every one horizontal scanning period. The data signal is supplied to the pixel circuit via the data line. Since the data line is accompanied by a parasitic capacitance, it is necessary to drive a capacitive load to supply the data signal. For this reason, there is a problem that power consumption increases when the polarity of the data signal is inverted every horizontal scanning period.

本発明は、このような事情に鑑みてなされたものであり、ライン反転やドット反転の駆動方法において、消費電力を削減することが可能な電気光学装置、およびその駆動方法を提供することを解決課題とする。   SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device capable of reducing power consumption in a driving method for line inversion and dot inversion, and a driving method thereof. Let it be an issue.

上述した課題を解決するため、本発明に係る電気光学装置は、複数の走査線と、複数のデータ線と、複数の保持容量線と、前記走査線と前記データ線との交差に対応して設けられた画素回路とを備えるものであって、前記画素回路は、前記走査線を介して供給される走査信号に従ってオン・オフが制御され、第1の端子が前記データ線と電気的に接続され、第2の端子が第1電極(例えば、図1の61、図10の63)と電気的に接続されるスイッチング素子(例えば、図1の50)と、一方の端子(例えば、図1の71)が前記スイッチング素子の第2の端子と電気的に接続され、他方の端子(例えば、図1の72)が前記保持容量線と電気的に接続される保持容量と、前記第1電極と第2電極(例えば、図1の62、図10の64)との間に設けられた電気光学物質とを備え、前記複数のデータ線は、各列の画素回路に対して第1データ線および第2データ線の組として設けられており、前記データ線の方向に隣接する画素回路において、一方の画素回路は前記第1データ線と電気的に接続され、他方の画素回路は前記第2データ線と電気的に接続されることを特徴とする。   In order to solve the above-described problem, an electro-optical device according to the invention corresponds to the intersection of a plurality of scanning lines, a plurality of data lines, a plurality of storage capacitor lines, and the scanning lines and the data lines. The pixel circuit is controlled to be turned on / off according to a scanning signal supplied via the scanning line, and the first terminal is electrically connected to the data line. And a switching element (for example, 50 in FIG. 1) whose second terminal is electrically connected to the first electrode (for example, 61 in FIG. 1, 63 in FIG. 10), and one terminal (for example, FIG. 1). 71) is electrically connected to the second terminal of the switching element, and the other terminal (for example, 72 in FIG. 1) is electrically connected to the storage capacitor line, and the first electrode And the second electrode (for example, 62 in FIG. 1, 64 in FIG. 10) The plurality of data lines are provided as a set of first data lines and second data lines with respect to the pixel circuits in each column, and are adjacent to the direction of the data lines. In the pixel circuit, the one pixel circuit is electrically connected to the first data line, and the other pixel circuit is electrically connected to the second data line.

この発明によれば、1列の画素回路に対して第1データ線と第2データ線とを備えるので、各データ線に極性が同一のデータ信号を供給することが可能となる。より具体的には、一列の画素回路の各々が表示すべき階調を示し、且つ、基準電位を中心として1水平走査期間ごとに極性が反転したデータ信号を、前記走査信号による前記走査線の選択と同期して、前記第1データ線と前記第2データ線とに交互に供給するデータ線駆動回路を備えることが好ましい。この場合には、各データ線に供給されるデータ信号の極性を揃えることができるので、行ごとに電気光学物質に印加する電圧を反転しつつ、データ線の電位の変化を低減することが可能となる。データ線には寄生容量が付随するためデータ線は容量性負荷であるが、データ線の電位変化が小さくなるので、その駆動で消費される電力を大幅に削減することができる。なお、交流駆動の方式はドット反転駆動あるいはライン反転駆動のいずれであってもよい。   According to the present invention, since the first data line and the second data line are provided for the pixel circuits in one column, it is possible to supply data signals having the same polarity to each data line. More specifically, a data signal indicating the gradation to be displayed by each of the pixel circuits in one column and having the polarity inverted every horizontal scanning period with the reference potential as the center is used for the scanning line by the scanning signal. It is preferable that a data line driving circuit for alternately supplying the first data line and the second data line to be synchronized with the selection is provided. In this case, since the polarity of the data signal supplied to each data line can be made uniform, it is possible to reduce the change in potential of the data line while inverting the voltage applied to the electro-optic material for each row. It becomes. Since the data line is accompanied by a parasitic capacitance, the data line is a capacitive load. However, since the potential change of the data line is reduced, the power consumed by the driving can be greatly reduced. The AC driving method may be either dot inversion driving or line inversion driving.

また、上述した電気光学装置は、基準電位を中心として高電位の正極性電位と低電位の負極性電位とを生成し、各行の画素回路を順次選択し、最初の行から最後の行までを選択する期間を1フィールドとしたとき、1フィールドごとに前記保持容量線に供給する電位を前記正極性電位と前記負極性電位との間で遷移させる保持容量線駆動手段を備えることが好ましい。この場合には、保持容量線に供給する電位の極性を反転することによって、データ信号の振幅を小さくすることが可能となる。   Further, the electro-optical device described above generates a high-potential positive potential and a low-potential negative potential around the reference potential, sequentially selects the pixel circuits in each row, and extends from the first row to the last row. When the selection period is one field, it is preferable to include storage capacitor line driving means for transitioning the potential supplied to the storage capacitor line for each field between the positive potential and the negative potential. In this case, it is possible to reduce the amplitude of the data signal by inverting the polarity of the potential supplied to the storage capacitor line.

また、保持容量線の好ましい態様としては、前記保持容量線は前記データ線の方向に隣接する画素回路の間に設けられており、前記走査線の方向に配置された画素回路は、上側の保持容量線と下側の保持容量線とに交互に電気的に接続され、前記保持容量線駆動手段は、前記複数の保持容量線に前記正極性電位と前記負極性電位とを交互に供給し、各行の画素回路に対して前記データ信号を書き込む期間の前後で前記保持容量線に供給する電位を前記正極性電位と前記負極性電位との間で遷移させることが望ましい。この場合には、行方向と列方向に配列される複数の画素回路において、千鳥状に正極性電位および負極性電位を供給することが可能となるので、本数の少ない保持容量線を用いて、ドット反転駆動を行うことができる。   As a preferred mode of the storage capacitor line, the storage capacitor line is provided between pixel circuits adjacent to each other in the direction of the data line, and the pixel circuit arranged in the direction of the scanning line has an upper storage capacitor line. The storage capacitor line is alternately electrically connected to the capacitor line and the lower storage capacitor line, and the storage capacitor line driving unit alternately supplies the positive potential and the negative potential to the plurality of storage capacitor lines, It is desirable that the potential supplied to the storage capacitor line is changed between the positive potential and the negative potential before and after the period for writing the data signal to the pixel circuits in each row. In this case, in the plurality of pixel circuits arranged in the row direction and the column direction, it is possible to supply the positive potential and the negative potential in a zigzag manner. Dot inversion driving can be performed.

また、保持容量線の他の態様としては、前記複数の保持容量線は、各行の画素回路に対して第1保持容量線および第2保持容量線の組として設けられており、前記走査線の方向に配置された画素回路は、前記第1保持容量線と前記第2保持容量線とに交互に電気的に接続され、前記保持容量線駆動手段は、前記第1保持容量線に前記正極性電位と前記負極性電位とのうちいずれか一方を供給し、前記第2保持容量線にいずれか他方を供給することが好ましい。この場合には、1行当たり2本の保持容量線を用いて正極性電位と負極性電位とを各画素回路に供給することができる。   According to another aspect of the storage capacitor line, the plurality of storage capacitor lines are provided as a set of a first storage capacitor line and a second storage capacitor line with respect to the pixel circuit in each row. The pixel circuits arranged in the direction are electrically connected alternately to the first storage capacitor line and the second storage capacitor line, and the storage capacitor line driving means is connected to the first storage capacitor line with the positive polarity. It is preferable to supply one of the potential and the negative potential and supply the other to the second storage capacitor line. In this case, a positive potential and a negative potential can be supplied to each pixel circuit using two storage capacitor lines per row.

また、上述した電気光学装置において、前記第2電極は複数の画素回路に共通な共通電極であり、前記基準電位は前記共通電極に供給される電位であることが好ましい。この場合は、いわゆる縦電界を電気光学物資に印加することができる。
また、上述した電気光学装置において、前記第2電極は前記第1電極と同一の層で形成され、前記基準電位は前記データ信号の最大電位と最小電位との平均電位であることが好ましい。 Further, in the above-mentioned electro-optical device, it is preferable that the second electrode is formed of the same layer as the first electrode, and the reference potential is the average potential of the maximum potential and the minimum potential of the data signal. この場合は、いわゆる横電界を電気光学物質に印加することができる。 In this case, a so-called transverse electric field can be applied to the electro-optical material. In the electro-optical device described above, it is preferable that the second electrode is a common electrode common to a plurality of pixel circuits, and the reference potential is a potential supplied to the common electrode. In this case, a so-called longitudinal electric field can be applied to the electro-optical material. In the electro-optical device described above, it is preferred that the second electrode is a common electrode common to a plurality of pixel circuits, and the reference potential is a potential supplied to the common electrode. In this case, a so-called longitudinal electric field can be applied to the electro-optical material.
In the electro-optical device described above, it is preferable that the second electrode is formed of the same layer as the first electrode, and the reference potential is an average potential of the maximum potential and the minimum potential of the data signal. In this case, a so-called lateral electric field can be applied to the electro-optic material. In the electro-optical device described above, it is preferred that the second electrode is formed of the same layer as the first electrode, and the reference potential is an average potential of the maximum potential and the minimum potential of the data signal. case, a so-called lateral electric field can be applied to the electro-optic material.

次に、本発明に係る本発明に係る電子機器は、上述した電気光学装置を備えることを特徴とする。このような電子機器としては、例えば、携帯情報端末、携帯電話機、ノート型コンピュータ、ビデオカメラ、およびプロジェクタなどが該当する。   Next, an electronic apparatus according to an aspect of the invention includes the above-described electro-optical device. Examples of such an electronic device include a portable information terminal, a mobile phone, a notebook computer, a video camera, and a projector.

さらに、本発明に係る電気光学装置の駆動方法は、複数の走査線と、複数のデータ線と、複数の保持容量線と、前記走査線と前記データ線との交差に対応して設けられた画素回路とを備え、前記画素回路は、前記走査線を介して供給される走査信号に従ってオン・オフが制御され、第1の端子が前記データ線と電気的に接続され、第2の端子が第1電極と電気的に接続されるスイッチング素子と、一方の端子が前記スイッチング素子の第2の端子と電気的に接続され、他方の端子が前記保持容量線と電気的に接続される保持容量と、前記第1電極と第2電極との間に設けられた電気光学物質とを備え、前記複数のデータ線は、各列の画素回路に対して第1データ線および第2データ線の組として設けられており、前記データ線の方向に隣接する画素回路において、一方の画素回路は前記第1データ線と電気的に接続され、他方の画素回路は前記第2データ線と電気的に接続される電気光学装置を駆動する方法であって、前記複数の走査線の各々に前記走査信号を順次供給し、一列の画素回路の各々が表示すべき階調を示し、基準電位を中心として1水平走査期間ごとに極性が反転したデータ信号を生成し、前記データ信号を、前記走査信号による前記走査線の選択と同期して、前記第1データ線と前記第2データ線とに交互に供給することを特徴とする。   Furthermore, the driving method of the electro-optical device according to the present invention is provided corresponding to a plurality of scanning lines, a plurality of data lines, a plurality of storage capacitor lines, and an intersection of the scanning lines and the data lines. A pixel circuit, wherein the pixel circuit is controlled to be turned on and off in accordance with a scanning signal supplied via the scanning line, a first terminal is electrically connected to the data line, and a second terminal is A switching element electrically connected to the first electrode, a storage capacitor having one terminal electrically connected to the second terminal of the switching element and the other terminal electrically connected to the storage capacitor line And an electro-optic material provided between the first electrode and the second electrode, and the plurality of data lines are a set of first data lines and second data lines for the pixel circuits in each column. Provided adjacent to the direction of the data line. In the pixel circuit, one pixel circuit is electrically connected to the first data line, and the other pixel circuit is a method for driving an electro-optical device electrically connected to the second data line. The scanning signal is sequentially supplied to each of a plurality of scanning lines, each of the pixel circuits in one column indicates a gradation to be displayed, and a data signal whose polarity is inverted every horizontal scanning period around the reference potential is generated. The data signal is alternately supplied to the first data line and the second data line in synchronization with selection of the scanning line by the scanning signal.

この発明によれば、各データ線に供給されるデータ信号の極性を揃えることができるので、行ごとに電気光学物質に印加する電圧を反転しつつ、データ線の電位の変化を低減することが可能となる。データ線には寄生容量が付随するためデータ線は容量性負荷であるが、データ線の電位変化が小さくなるので、その駆動で消費される電力を大幅に削減することができる。
なお、上述した発明において電気光学物質とは、電気的なエネルギーによって光学特性が変化する物質の意味であり、例えば、印加電圧に応じて透過率が変化する液晶が該当する。 In the above-described invention, the electro-optical substance means a substance whose optical characteristics change with electrical energy, and corresponds to, for example, a liquid crystal whose transmittance changes according to an applied voltage. According to the present invention, since the polarity of the data signal supplied to each data line can be made uniform, the change in the potential of the data line can be reduced while inverting the voltage applied to the electro-optic material for each row. It becomes possible. Since the data line is accompanied by a parasitic capacitance, the data line is a capacitive load. However, since the potential change of the data line is reduced, the power consumed by the driving can be greatly reduced. According to the present invention, since the polarity of the data signal supplied to each data line can be made uniform, the change in the potential of the data line can be reduced while similarly the voltage applied to the electro-optic material for each row. It becomes possible. Since the data line is accompanied by a parasitic capacitance, the data line is a capacitive load. However, since the potential change of the data line is reduced, the power consumed by the driving can be greatly reduced.
In the above-described invention, the electro-optical substance means a substance whose optical characteristics change with electric energy, and for example, corresponds to a liquid crystal whose transmittance changes according to an applied voltage. In the above-described invention, the electro-optical substance means a substance whose optical characteristics change with electric energy, and for example, corresponds to a liquid crystal whose transmittance changes according to an applied voltage.

<1.第1実施形態>
図1に第1実施形態に係る電気光学装置のブロック図を示す。 FIG. 1 shows a block diagram of the electro-optical device according to the first embodiment. この電気光学装置500は電気光学材料として液晶を用いる。 The electro-optical device 500 uses a liquid crystal as an electro-optical material. 電気光学装置500は、主要部として液晶パネルAAを備える。 The electro-optical device 500 includes a liquid crystal panel AA as a main part. 液晶パネルAAは、スイッチング素子として薄膜トランジスタ(Thin Film Transistor:以下、「TFT」と称する)を形成した素子基板と対向基板とを互いに電極形成面を対向させて、かつ、一定の間隙を保って貼付し、この間隙に液晶が挟持されている。 The liquid crystal panel AA is attached by attaching an element substrate on which a thin film transistor (hereinafter referred to as "TFT") is formed as a switching element and an opposing substrate so that the electrode forming surfaces face each other and maintaining a certain gap. However, the liquid crystal is sandwiched in this gap. <1. First Embodiment> <1. First Embodiment>
FIG. 1 is a block diagram of the electro-optical device according to the first embodiment. The electro-optical device 500 uses liquid crystal as an electro-optical material. The electro-optical device 500 includes a liquid crystal panel AA as a main part. The liquid crystal panel AA is bonded to an element substrate on which a thin film transistor (hereinafter referred to as “TFT”) is formed as a switching element and a counter substrate with the electrode formation surfaces facing each other and maintaining a certain gap. However, liquid crystal is sandwiched between the gaps. FIG. 1 is a block diagram of the electro-optical device according to the first embodiment. The electro-optical device 500 uses liquid crystal as an electro-optical material. The electro-optical device 500 includes a liquid crystal panel AA as a main part. The liquid crystal panel AA is bonded to an element substrate on which a thin film transistor (hereinafter referred to as “TFT”) is formed as a switching element and a counter substrate with the diagram formation surfaces facing each other and maintaining a certain gap. However, liquid crystal is sandwiched between the gaps.

また、電気光学装置500は、液晶パネルAA、タイミング発生回路300および画像処理回路400を備える。液晶パネルAAの素子基板上には、画像表示領域A、走査線駆動回路100およびデータ線駆動回路200が形成されている。この電気光学装置500に供給される入力画像データDinは、例えば、3ビットパラレルの形式である。タイミング発生回路300は、画像処理回路400から供給される水平走査信号や垂直走査信号などの制御信号に同期して、Yクロック信号YCK、Xクロック信号XCK、Y転送開始パルスDY、およびX転送開始パルスDXを生成して、走査線駆動回路100およびデータ線駆動回路200に供給する。また、タイミング発生回路300は、画像処理回路400を制御する各種のタイミング信号を生成し、これを出力する。   The electro-optical device 500 includes a liquid crystal panel AA, a timing generation circuit 300, and an image processing circuit 400. An image display area A, a scanning line driving circuit 100, and a data line driving circuit 200 are formed on the element substrate of the liquid crystal panel AA. The input image data Din supplied to the electro-optical device 500 has, for example, a 3-bit parallel format. The timing generation circuit 300 is synchronized with a control signal such as a horizontal scanning signal and a vertical scanning signal supplied from the image processing circuit 400, and generates a Y clock signal YCK, an X clock signal XCK, a Y transfer start pulse DY, and an X transfer start. A pulse DX is generated and supplied to the scanning line driving circuit 100 and the data line driving circuit 200. The timing generation circuit 300 generates various timing signals for controlling the image processing circuit 400 and outputs them.

ここで、Yクロック信号YCKは、走査線20を選択する期間を特定し、Xクロック信号XCKは、データ線10を選択する期間を特定する。また、Y転送開始パルスDYは走査線20の選択開始を指示するパルスであり、一方、X転送開始パルスDXはデータ線10の選択開始を指示するパルスである。
次に、画像処理回路400は、入力画像データDinに、液晶パネルの光透過特性を考慮したガンマ補正等を施した後、RGB各色の画像データをD/A変換して、画像信号VIDを生成して液晶パネルAAに供給する。 Next, the image processing circuit 400 performs gamma correction or the like in consideration of the light transmission characteristics of the liquid crystal panel on the input image data Din, and then D / A-converts the image data of each RGB color to generate an image signal VID. And supply it to the liquid crystal panel AA. Here, the Y clock signal YCK specifies a period for selecting the scanning line 20, and the X clock signal XCK specifies a period for selecting the data line 10. The Y transfer start pulse DY is a pulse for instructing the start of selection of the scanning line 20, while the X transfer start pulse DX is a pulse for instructing the start of selection of the data line 10. Here, the Y clock signal YCK specifies a period for selecting the scanning line 20, and the X clock signal XCK specifies a period for selecting the data line 10. The Y transfer start pulse DY is a pulse for instructing the start of selection of the scanning line 20, while the X transfer start pulse DX is a pulse for instructing the start of selection of the data line 10.
Next, the image processing circuit 400 subjects the input image data Din to gamma correction and the like considering the light transmission characteristics of the liquid crystal panel, and then D / A converts the RGB image data to generate an image signal VID. And supplied to the liquid crystal panel AA. Next, the image processing circuit 400 subjects the input image data Din to gamma correction and the like considering the light transmission characteristics of the liquid crystal panel, and then D / A converts the RGB image data to generate an image signal VID. And supplied to the liquid crystal panel AA.

画像表示領域Aには、Xm(mは2以上の自然数)本の走査線20が、X方向に沿って平行に配列して形成される一方、n(nは2以上の自然数)本のデータ線10が、Y方向に沿って平行に配列して形成されている。そして、データ線10と走査線20との交差に対応してm×n個の画素回路P(P11〜Pmn)が配列される。
図2に画像表示領域Aおよびデータ線駆動回路200の一部の詳細な構成を示す。 FIG. 2 shows a detailed configuration of a part of the image display area A and the data line drive circuit 200. 図1では簡略化して説明したが、各列の画素回路Pに対してデータ線10は第1データ線10aと第2データ線10bの組から構成される。 Although the description has been simplified in FIG. 1, the data line 10 is composed of a pair of the first data line 10a and the second data line 10b for the pixel circuit P in each column. また、データ線10および走査線20の他に保持容量線30が設けられている。 In addition to the data line 10 and the scanning line 20, the holding capacitance line 30 is provided. この例の保持容量線30はn+1本あり、データ線10に沿って配置される画素回路Pの間、および画素回路Pの両端に配置される。 The holding capacitance line 30 of this example has n + 1, and is arranged between the pixel circuits P arranged along the data line 10 and at both ends of the pixel circuit P. In the image display area A, Xm (m is a natural number of 2 or more) scanning lines 20 are formed in parallel along the X direction, while n (n is a natural number of 2 or more) data. Lines 10 are formed in parallel along the Y direction. Then, m × n pixel circuits P (P11 to Pmn) are arranged corresponding to the intersections of the data lines 10 and the scanning lines 20. In the image display area A, Xm (m is a natural number of 2 or more) scanning lines 20 are formed in parallel along the X direction, while n (n is a natural number of 2 or more) data. Lines 10 are formed in parallel along the Y direction. Then, m × n pixel circuits P (P11 to Pmn) are arranged corresponding to the intersections of the data lines 10 and the scanning lines 20.
FIG. 2 shows a detailed configuration of part of the image display area A and the data line driving circuit 200. Although simplified in FIG. 1, the data line 10 is composed of a set of a first data line 10a and a second data line 10b for the pixel circuits P in each column. In addition to the data line 10 and the scanning line 20, a storage capacitor line 30 is provided. In this example, there are n + 1 storage capacitor lines 30, which are arranged between the pixel circuits P arranged along the data line 10 and at both ends of the pixel circuit P. FIG. 2 shows a detailed configuration of part of the image display area A and the data line driving circuit 200. Although simplified in FIG. 1, the data line 10 is composed of a set of a first data line 10a and a second data line 10b for the pixel circuits P in each column. In addition to the data line 10 and the scanning line 20, a storage capacitor line 30 is provided. In this example, there are n + 1 storage capacitor lines 30, which are arranged between the pixel circuits P arranged along the data line 10 and at both ends of the pixel circuits P.

そして、走査線20とデータ線10との交差に対応して画素回路Pが形成される。画素回路Pは、TFT50、液晶素子60および保持容量70を備える。液晶素子60は画素電極(第1電極)61と対向電極62(第2電極)との間に液晶を挟持して構成される。対向電極62には共通電位Vcomが供給される(図示略)。TFT50のゲートは走査線20と接続され、そのソースは第1データ線10aまたは第2データ線10bと接続され、そのドレインは画素電極61と接続される。保持容量70は第1端子71がTFT50のドレインと接続され第2端子72が保持容量線30と接続される。   A pixel circuit P is formed corresponding to the intersection of the scanning line 20 and the data line 10. The pixel circuit P includes a TFT 50, a liquid crystal element 60, and a storage capacitor 70. The liquid crystal element 60 is configured by sandwiching liquid crystal between a pixel electrode (first electrode) 61 and a counter electrode 62 (second electrode). A common potential Vcom is supplied to the counter electrode 62 (not shown). The gate of the TFT 50 is connected to the scanning line 20, its source is connected to the first data line 10 a or the second data line 10 b, and its drain is connected to the pixel electrode 61. The storage capacitor 70 has a first terminal 71 connected to the drain of the TFT 50 and a second terminal 72 connected to the storage capacitor line 30.

ここで、データ線10の方向(列方向)に配列された画素回路は、交互に第1データ線10aと第2データ線10bに接続される。この例では、奇数行の画素回路Pが第1データ線10aと接続される一方、偶数行の画素回路Pが第2データ線10bに接続される。換言すれば、データ線10の方向に隣接する画素回路において、一方の画素回路は第1データ線10aと電気的に接続され、他方の画素回路は第2データ線10bと電気的に接続される。例えば、第1列に着目すると、第1行、第3行、…には第1データ線10aを介してデータ信号X1aが供給され、第2行、第4行、…には第2データ線10bを介してデータ信号X1bが供給される。データ線駆動回路200の出力段には、スイッチSWが設けられており、各列のデータ信号X1、X2、…Xmを1水平走査期間ごとに第1データ線10aと第2データ10bとに振り分ける。すなわち、データ線駆動回路200は、一列の画素回路Pの各々が表示すべき階調を示すデータ信号Xを、走査信号による走査線20の選択と同期して、第1データ線10aと第2データ線10bとに交互に供給する手段として機能する。   Here, the pixel circuits arranged in the direction of the data line 10 (column direction) are alternately connected to the first data line 10a and the second data line 10b. In this example, the odd-numbered pixel circuit P is connected to the first data line 10a, while the even-numbered pixel circuit P is connected to the second data line 10b. In other words, in the pixel circuits adjacent in the direction of the data line 10, one pixel circuit is electrically connected to the first data line 10a, and the other pixel circuit is electrically connected to the second data line 10b. . For example, focusing on the first column, the data signal X1a is supplied to the first row, the third row,... Via the first data line 10a, and the second data line is supplied to the second row, the fourth row,. The data signal X1b is supplied via 10b. The output stage of the data line driving circuit 200 is provided with a switch SW, and distributes the data signals X1, X2,... Xm of each column to the first data line 10a and the second data 10b every horizontal scanning period. . That is, the data line driving circuit 200 synchronizes the first data line 10a and the second data signal X in synchronization with the selection of the scanning line 20 by the scanning signal. It functions as means for alternately supplying data lines 10b.

また、保持容量線30はデータ線10の方向(列方向)に隣接する画素回路Pの間に設けられているが、走査線20の方向(行方向)に配置された画素回路Pは、上側の保持容量線30と下側の保持容量線30とに交互に接続される。   The storage capacitor line 30 is provided between the pixel circuits P adjacent to each other in the direction of the data line 10 (column direction), but the pixel circuit P arranged in the direction of the scanning line 20 (row direction) Are alternately connected to the storage capacitor line 30 and the lower storage capacitor line 30.

また、TFT50のゲートが接続される各走査線20には、走査線駆動回路100から、走査信号GL1、GL2、…、GLmが、パルス的に線順次で印加されるようになっている。このため、ある走査線20に走査信号が供給されると、当該走査線に接続されるTFT50がオンするので、データ線10から所定のタイミングで供給されるデータ信号X1、X2、…、Xnは、対応する画素に順番に書き込まれた後、所定の期間保持されることとなる。   Further, the scanning signals GL1, GL2,..., GLm are applied from the scanning line driving circuit 100 to the scanning lines 20 to which the gates of the TFTs 50 are connected in a pulse-sequential manner. Therefore, when a scanning signal is supplied to a certain scanning line 20, the TFT 50 connected to the scanning line is turned on, so that the data signals X1, X2,..., Xn supplied from the data line 10 at a predetermined timing are After being written in order to the corresponding pixels, they are held for a predetermined period.

各画素に印加される電圧レベルに応じて液晶分子の配向や秩序が変化するので、光変調による階調表示が可能となる。例えば、液晶を通過する光量は、ノーマリーホワイトモードであれば、印加電圧が高くなるにつれて制限される一方、ノーマリーブラックモードであれば、印加電圧が高くなるにつれて緩和されるので、電気光学装置500全体では、画像信号に応じたコントラストを持つ光が各画素毎に出射される。このため、所定の表示が可能となる。また、保持された画像信号がリークするのを防ぐために、保持容量70が、画素電極61と対向電極62との間に形成される液晶容量と並列に付加される。これにより保持特性が改善される結果、高コントラスト比が実現されることとなる。
さらに、走査線駆動回路100は保持容量線30を駆動する保持容量線駆動手段として機能する。 Further, the scanning line drive circuit 100 functions as a holding capacitance line driving means for driving the holding capacitance line 30. この例の走査線駆動回路100は、保持電位HL1、HL2、…HLm+1を各保持容量線30に供給する。 The scanning line drive circuit 100 of this example supplies holding potentials HL1, HL2, ... HLm + 1 to each holding capacitance line 30. Since the orientation and order of liquid crystal molecules change according to the voltage level applied to each pixel, gradation display by light modulation becomes possible. For example, the amount of light passing through the liquid crystal is limited as the applied voltage increases in the normally white mode, whereas the amount of light that passes through the liquid crystal is reduced as the applied voltage increases in the normally black mode. In the entire 500, light having contrast according to the image signal is emitted for each pixel. For this reason, a predetermined display becomes possible. In order to prevent the held image signal from leaking, the holding capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 61 and the counter electrode 62. As a result, the holding characteristics are improved, and as a result, a high contrast ratio is realized. Since the orientation and order of liquid crystal molecules change according to the voltage level applied to each pixel, gradation display by light modulation becomes possible. For example, the amount of light passing through the liquid crystal is limited as the applied voltage increases in the normally In the entire 500, light having contrast according to the image signal is emitted for each pixel. For this reason, white mode, the amount of light that passes through the liquid crystal is reduced as the applied voltage increases in the normally black mode. In order to prevent the held image signal from leaking, the holding voltage 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 61 and the counter electrode 62. As a result, the holding characteristics are improved, and as a result, a high contrast ratio is realized.
Further, the scanning line driving circuit 100 functions as a storage capacitor line driving unit that drives the storage capacitor line 30. The scanning line driving circuit 100 in this example supplies the holding potentials HL1, HL2,... HLm + 1 to each holding capacitor line 30. Further, the scanning line driving circuit 100 functions as a storage capacitor line driving unit that drives the storage capacitor line 30. The scanning line driving circuit 100 in this example supplies the holding potentials HL1, HL2, ... HLm + 1 to each holding capacitor line 30.

次に、図3を参照して、電気光学装置の動作を説明する。まず、第1データ線10a、10bに供給されるデータ信号X1b,X2a,X3b…は、第1フィールドF1において負極性となる一方、第2フィールドF2において正極性になる。一方、データ信号X1a,X2b,X3a…は、第1フィールドF1において正極性となる一方、第2フィールドF2において負極性になる。ここで、信号の極性は、対向電極62の共通電位Vcomを基準として高電位を正極性、低電位を負極性と定める。   Next, the operation of the electro-optical device will be described with reference to FIG. First, the data signals X1b, X2a, X3b... Supplied to the first data lines 10a, 10b are negative in the first field F1, and positive in the second field F2. On the other hand, the data signals X1a, X2b, X3a,... Have a positive polarity in the first field F1, and a negative polarity in the second field F2. Here, with respect to the polarity of the signal, a high potential is defined as positive polarity and a low potential is defined as negative polarity based on the common potential Vcom of the counter electrode 62.

また、保持電位HL1、HL2、…HLmは、走査信号GL1〜GLmがハイレベルとなるデータ信号の書き込み期間が終了した後、電位が変化する。保持電位HL1〜HLmのハイレベルを正極性電位、ローレベルを負極性電位と称する。例えば、時刻t0から時刻t1の期間において走査信号GL1がハイレベルになり、データ信号X1a[1]が画素回路P11に書き込まれた後、保持電位HL1は負極性電位から正極性電位に遷移する。換言すれば、保持電位HL1〜HLmは各行の画素回路Pに対してデータ信号を書き込む期間の前後で正極性電位と負極性電位との間で遷移する。   In addition, the holding potentials HL1, HL2,... HLm change in potential after the writing period of the data signal in which the scanning signals GL1 to GLm are at the high level is completed. The high level of the holding potentials HL1 to HLm is referred to as a positive potential, and the low level is referred to as a negative potential. For example, during the period from time t0 to time t1, the scanning signal GL1 becomes high level and the data signal X1a [1] is written to the pixel circuit P11, and then the holding potential HL1 changes from the negative potential to the positive potential. In other words, the holding potentials HL1 to HLm transition between the positive potential and the negative potential before and after the period for writing the data signal to the pixel circuits P in each row.

ここで、図4および図5を参照して、画素回路Pにおける各種のノードの電位を説明する。図4は第1フィールドF1でのノード電位を、図5は第2フィールドF2でのノード電位を示している。これらの図において、「V+max」は表示時における画素電極61の電位のうち正極性の上限値であり、「V+min」は表示時における画素電極61の電位のうち正極性の下限値である。また、「V-max」は表示時における画素電極61の電位のうち負極性の上限値であり、「V-min」は表示時における画素電極61の電位のうち負極性の下限値である。また、「PX11」は画素回路P11におけるTFT50のドレイン電位(画素電極61の電位)、「PX12」は画素回路P12におけるTFT50のドレイン電位、「PX21」は画素回路P21におけるTFT50のドレイン電位である。   Here, the potentials of various nodes in the pixel circuit P will be described with reference to FIGS. 4 shows the node potential in the first field F1, and FIG. 5 shows the node potential in the second field F2. In these figures, “V + max” is the upper limit value of the positive polarity of the potential of the pixel electrode 61 at the time of display, and “V + min” is the lower limit value of the positive polarity of the potential of the pixel electrode 61 at the time of display. It is. “V-max” is a negative upper limit value of the potential of the pixel electrode 61 at the time of display, and “V-min” is a lower limit value of negative polarity of the potential of the pixel electrode 61 at the time of display. “PX11” is the drain potential of the TFT 50 in the pixel circuit P11 (the potential of the pixel electrode 61), “PX12” is the drain potential of the TFT 50 in the pixel circuit P12, and “PX21” is the drain potential of the TFT 50 in the pixel circuit P21.

第1フィールドF1において、例えば、画素回路P11に着目すると、走査信号GL1がハイレベルとなる書き込み期間において、保持電位HL1は負極性電位となっている。この状態でデータ信号X1aが画素電極61に供給されると、画素電極電位PX11がデータ信号X1aの電位に漸近する。そして、走査信号GL1がハイレベルからローレベルに遷移すると、TFT50がオフ状態となり画素電極61はフローティング状態となる。このとき、保持電位HL1が負極性電位から正極性電位に遷移する。すると、保持容量70の第2端子72の電位が正極性電位に変化し、これに伴って保持容量70の第1端子71の電位が上昇する。これによって、液晶素子60には共通電位Vcomを基準として正極性の電圧ΔV11が印加される。
次に、画素回路P21に着目すると、走査信号GL2がハイレベルとなる書き込み期間において、保持電位HL2は正極性電位となっている。 Next, focusing on the pixel circuit P21, the holding potential HL2 is the positive electrode potential during the writing period when the scanning signal GL2 is at a high level. この状態でデータ信号X1bが画素電極61に供給されると、画素電極電位PX21がデータ信号X1bの電位に漸近する。 When the data signal X1b is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX21 gradually approaches the potential of the data signal X1b. そして、走査信号GL2がハイレベルからローレベルに遷移すると、TFT50がオフ状態となり画素電極61はフローティング状態となる。 Then, when the scanning signal GL2 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in a floating state. このとき、保持電位HL2が正極性電位から負極性電位に遷移する。 At this time, the holding potential HL2 transitions from the positive electrode potential to the negative electrode potential. すると、保持容量70の第2端子72の電位が負極性電位に変化し、これに伴って保持容量70の第1端子71の電位が下降する。 Then, the potential of the second terminal 72 of the holding capacity 70 changes to the negative electrode potential, and the potential of the first terminal 71 of the holding capacity 70 drops accordingly. これによって、液晶素子60には共通電位Vcomを基準として負極性の電圧ΔV21が印加される。 As a result, the negative electrode voltage ΔV21 is applied to the liquid crystal element 60 with reference to the common potential Vcom. In the first field F1, for example, when focusing on the pixel circuit P11, the holding potential HL1 is a negative potential in the writing period in which the scanning signal GL1 is at a high level. When the data signal X1a is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX11 gradually approaches the potential of the data signal X1a. When the scanning signal GL1 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in a floating state. At this time, the holding potential HL1 transitions from the negative potential to the positive potential. Then, the potential of the second terminal 72 of the storage capacitor 70 changes to a positive potential, and accordingly, the potential of the first terminal 71 of the storage capacitor 70 increases. Thus, a positive voltage ΔV11 is applied to the liquid crystal element 60 with the common potential Vcom as a reference. In the first field F1, for example, when focusing on the pixel circuit P11, the holding potential HL1 is a negative potential in the writing period in which the scanning signal GL1 is at a high level. When the data signal X1a is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX11 gradually approaches the potential of the data signal X1a. When the scanning signal GL1 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in At this time, the holding potential HL1 transitions from the negative potential to the positive potential. Then, the potential of the second terminal 72 of the storage capacitor 70 changes to a positive potential, and accordingly, the potential of the first terminal 71 of the storage capacitor 70 increases. Thus, a positive voltage ΔV11 is applied to the liquid crystal element 60 with the common potential Vcom as a reference.
Next, focusing on the pixel circuit P21, the holding potential HL2 is a positive potential in the writing period in which the scanning signal GL2 is at a high level. When the data signal X1b is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX21 gradually approaches the potential of the data signal X1b. When the scanning signal GL2 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in a floating state. At this time, the holding potential HL2 transitions from the positive potential to the negative potential. Then, the potential of the second terminal 72 of the storage capacitor 70 changes to a negative potential, and accordingly, the potential of the first terminal 71 of the storage capacitor 70 decreases. Accordingly, a negative voltage ΔV21 is applied to the liquid crystal element 60 with the common potential Vcom as a reference. Next, focusing on the pixel circuit P21, the holding potential HL2 is a positive potential in the writing period in which the scanning signal GL2 is at a high level. When the data signal X1b is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX21 gradually approaches the potential of the data signal X1b. When the scanning signal GL2 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in a floating state. At this time, The holding potential HL2 transitions from the positive potential to the negative potential. Then, the potential of the second terminal 72 of the storage capacitor 70 changes to a negative potential, and accordingly, the potential of the first terminal 71 of the storage capacitor 70 decreases . Accordingly, a negative voltage ΔV21 is applied to the liquid crystal element 60 with the common potential Vcom as a reference.

次に、画素回路P12に着目する。画素回路P12は、図2に示すように下側の保持容量線30に接続されるので、保持電位HL2が供給される。この例では、走査信号GL1がハイレベルになると、正極性のデータ信号X2aが画素電極61に供給され、画素電極電位PX12がデータ信号X2aの電位に漸近する。そして、走査信号GL1がハイレベルからローレベルに遷移して書き込み期間が終了しても、保持電位HL2は正極性電位を維持した後、次の書き込み期間で走査信号GL2がローレベルに遷移した後で負極性電位に変化する。このため、画素回路P12の液晶素子60には共通電位Vcomを基準として負極性の電圧ΔV12が印加される。
第2フィールド期間F2では、画素回路P11に着目すると、走査信号GL1がハイレベルとなる書き込み期間において、保持電位HL1は正極性電位となっている。 In the second field period F2, focusing on the pixel circuit P11, the holding potential HL1 is a positive electrode during the writing period when the scanning signal GL1 is at a high level. この状態でデータ信号X1aが画素電極61に供給されると、画素電極電位PX11がデータ信号X1aの電位に漸近する。 When the data signal X1a is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX11 gradually approaches the potential of the data signal X1a. そして、走査信号GL1がハイレベルからローレベルに遷移すると、TFT50がオフ状態となり画素電極61はフローティング状態となる。 Then, when the scanning signal GL1 transitions from the high level to the low level, the TFT 50 is in the off state and the pixel electrode 61 is in the floating state. このとき、保持電位HL1が正極性電位から負極性電位に遷移する。 At this time, the holding potential HL1 transitions from the positive electrode potential to the negative electrode potential. すると、保持容量70の第2端子72の電位が負極性電位に変化し、これに伴って保持容量70の第1端子71の電位が下降する。 Then, the potential of the second terminal 72 of the holding capacity 70 changes to the negative electrode potential, and the potential of the first terminal 71 of the holding capacity 70 drops accordingly. これによって、液晶素子60には共通電位Vcomを基準として、第1フィールドF1での極性とは逆の負極性の電圧ΔV11が印加される。 As a result, a negative electrode voltage ΔV11 opposite to the polarity in the first field F1 is applied to the liquid crystal element 60 with reference to the common potential Vcom.
画素回路P21,P12などにおいても、ノードの電位は第2フィールド期間F2では第1フィールド期間F1と逆の極性で変化する。 Also in the pixel circuits P21, P12 and the like, the potential of the node changes in the second field period F2 with the polarity opposite to that in the first field period F1. Next, attention is focused on the pixel circuit P12. Since the pixel circuit P12 is connected to the lower storage capacitor line 30 as shown in FIG. 2, the storage potential HL2 is supplied. In this example, when the scanning signal GL1 becomes high level, the positive data signal X2a is supplied to the pixel electrode 61, and the pixel electrode potential PX12 gradually approaches the potential of the data signal X2a. Even when the scanning signal GL1 changes from the high level to the low level and the writing period ends, the holding potential HL2 maintains the positive potential, and then the scanning signal GL2 changes to the low level in the next writing period. Changes to a negative potential. Therefore, the negative voltage ΔV12 is applied to the liquid crystal element 60 of the pixel circuit P12 with reference to the common potential Vcom. Next, attention is focused on the pixel circuit P12. Since the pixel circuit P12 is connected to the lower storage capacitor line 30 as shown in FIG. 2, the storage potential HL2 is supplied. In this example, when the scanning signal GL1 becomes high level, the positive data signal X2a is supplied to the pixel electrode 61, and the pixel electrode potential PX12 gradually approaches the potential of the data signal X2a. Even when the scanning signal GL1 changes from the high level to the low level and the writing period ends, the holding potential HL2 maintains the positive potential, and then the scanning signal GL2 changes to the low level in the next writing period. Changes to a negative potential. Therefore, the negative voltage ΔV12 is applied to the liquid crystal element 60 of the pixel circuit P12 with reference to the common potential Vcom.
In the second field period F2, when attention is paid to the pixel circuit P11, the holding potential HL1 is a positive potential in the writing period in which the scanning signal GL1 is at a high level. When the data signal X1a is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX11 gradually approaches the potential of the data signal X1a. When the scanning signal GL1 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in a floating state. At this time, the holding potential HL1 transitions from the positive potential to the negative potential. Then, the potential of the second terminal 72 of the storage capacitor 70 changes to a negative potential, and accordingly, the potential of the first terminal 71 of the storage capacitor 70 decreases. Accordingly, a negative voltage ΔV11 opposite to the polarity in the first field F1 is applied to the liquid crystal element 60 with the common potential Vcom In the second field period F2, when attention is paid to the pixel circuit P11, the holding potential HL1 is a positive potential in the writing period in which the scanning signal GL1 is at a high level. When the data signal X1a is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX11 gradually approaches the potential of the data signal X1a. When the scanning signal GL1 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in At this time, the holding potential HL1 transitions from the positive potential to the negative potential. Then, the potential of the second terminal 72 of the storage capacitor 70 changes to a negative potential, and accordingly, the potential of the first terminal 71 of the storage capacitor 70 decreases. Accordingly, a negative voltage ΔV11 opposite to the polarity in the first field F1 is applied to the liquid crystal element 60 with the common potential Vcom as a reference. as a reference.
Also in the pixel circuits P21, P12, etc., the potential of the node changes in the second field period F2 with the opposite polarity to the first field period F1. Also in the pixel circuits P21, P12, etc., the potential of the node changes in the second field period F2 with the opposite polarity to the first field period F1.

このように液晶素子60に印加する電圧の極性を制御することによって、第1フィールドF1では、図6(A)に示す極性の電圧が液晶素子60に印加される一方、第2フィールドでは図6(B)に示す電圧が液晶素子60に印加される。これにより、ドット反転方式の駆動が行われる。   By controlling the polarity of the voltage applied to the liquid crystal element 60 in this way, the voltage having the polarity shown in FIG. 6A is applied to the liquid crystal element 60 in the first field F1, while the voltage shown in FIG. The voltage shown in (B) is applied to the liquid crystal element 60. Thus, dot inversion driving is performed.

本実施形態では、各列の画素回路Pに第1データ線10aと第2データ線10bとを用いてデータ信号を伝送した。このように2本で1組のデータ線10を用いたのは以下の理由による。ドット反転やライン反転の駆動方法では、1列ごとにデータ信号の極性を反転する必要がある。データ線10は容量性負荷であるから、1水平走査期間ごとにデータ信号の極性を反転させると、消費電力が増大する。そこで、第1データ線10aを奇数行の画素回路Pに接続する一方、第2データ線10bを偶数行に接続することによって、1本のデータ線10に供給されるデータ信号Xの極性を揃えることができる。画像信号には垂直方向に相関性が高いといった性質があるので、データ信号の極性を揃えることによって、データ線10の電位の変動を抑圧することができる。この結果、消費電力を大幅に削減することが可能となる。   In the present embodiment, data signals are transmitted to the pixel circuits P in each column using the first data line 10a and the second data line 10b. The reason why two sets of data lines 10 are used is as follows. In the dot inversion or line inversion driving method, it is necessary to invert the polarity of the data signal for each column. Since the data line 10 is a capacitive load, power consumption increases if the polarity of the data signal is inverted every horizontal scanning period. Therefore, the polarity of the data signal X supplied to one data line 10 is made uniform by connecting the first data line 10a to the pixel circuits P in the odd rows and connecting the second data line 10b to the even rows. be able to. Since the image signal has a property of being highly correlated in the vertical direction, it is possible to suppress fluctuations in the potential of the data line 10 by making the polarity of the data signal uniform. As a result, power consumption can be greatly reduced.

図7に画像表示領域Aのレイアウトの一部を示す。図7では、半導体層、ゲート配線層およびソース配線層のみを図示しているが、これらの層は例えばガラス等の基板上に形成されており、各層間には絶縁層等の層が介在しているが、図示の便宜上省略している。また、配線層の上には、絶縁層が形成されており、この絶縁層の上には透明な画素電極61が形成されている。上述した第1データ線10aおよび第2データ線10bは、ソース配線層によって形成される。また、走査線20および保持容量線30はゲート配線層によって形成される。さらに、保持容量70はTFT50のドレインと一体に形成された半導体層とゲート絶縁膜とゲート配線層とによって構成される。   FIG. 7 shows a part of the layout of the image display area A. In FIG. 7, only the semiconductor layer, the gate wiring layer, and the source wiring layer are illustrated, but these layers are formed on a substrate such as glass, for example, and a layer such as an insulating layer is interposed between each layer. However, it is omitted for convenience of illustration. An insulating layer is formed on the wiring layer, and a transparent pixel electrode 61 is formed on the insulating layer. The first data line 10a and the second data line 10b described above are formed by a source wiring layer. Further, the scanning line 20 and the storage capacitor line 30 are formed by a gate wiring layer. Further, the storage capacitor 70 includes a semiconductor layer, a gate insulating film, and a gate wiring layer that are formed integrally with the drain of the TFT 50.

<2.第2実施形態>
第2実施形態の電気光学装置500は、1行当たり1本の保持容量線30の替わりに1行当たり2本の第1保持容量線30aおよび第2保持容量線30bを備える点、走査線駆動回路100が第1保持容量線30aおよび第2保持容量線30bに第1保持電位と第2保持電位を各々供給する点を除いて、第1実施形態の電気光学装置500と同様に構成されている。
<2. Second Embodiment>
The electro-optical device 500 according to the second embodiment is provided with two first storage capacitor lines 30a and second storage capacitor lines 30b per row instead of one storage capacitor line 30 per row, scanning line driving The circuit 100 is configured in the same manner as the electro-optical device 500 of the first embodiment except that the circuit 100 supplies the first holding potential and the second holding potential to the first holding capacitor line 30a and the second holding capacitor line 30b, respectively. Yes. The electro-optical device 500 according to the second embodiment is provided with two first storage capacitor lines 30a and second storage capacitor lines 30b per row instead of one storage capacitor line 30 per row, scanning line driving The circuit 100 is configured in the same manner as the electro-optical device 500 of the first embodiment except that the circuit 100 supplies the first holding potential and the second holding potential to the first holding capacitor line 30a and the second holding capacitor line 30b, respectively. Yes.

図8に画像表示領域Aおよびデータ線駆動回路200の一部の詳細な構成を示す。この図に示すように奇数列の奇数行の画素回路および偶数列の偶数行の画素回路Pは第1保持容量線30aに接続され、偶数列の奇数行の画素回路Pおよび奇数列の偶数行の画素回路Pは第2保持容量線30bに接続される。すなわち、第1保持容量線30aに接続される画素回路は千鳥状に配列され、第2保持容量線30bに接続される画素回路も千鳥状に配列される。各行の第1保持容量線30aには第1保持電位HL1a〜HLnaが供給され、各行の第2保持容量線30bには第2保持電位HL1b〜HLnbが供給される。   FIG. 8 shows a detailed configuration of part of the image display area A and the data line driving circuit 200. As shown in this figure, the odd-numbered pixel circuit P in the odd-numbered column and the even-numbered pixel circuit P in the even-numbered column are connected to the first storage capacitor line 30a. The pixel circuit P is connected to the second storage capacitor line 30b. That is, the pixel circuits connected to the first storage capacitor line 30a are arranged in a staggered pattern, and the pixel circuits connected to the second storage capacitor line 30b are also arranged in a staggered pattern. The first holding potentials HL1a to HLna are supplied to the first holding capacitance lines 30a in each row, and the second holding potentials HL1b to HLnb are supplied to the second holding capacitance lines 30b in each row.

図9は第2実施形態の電気光学装置の動作を示すタイミングチャートである。この図に示すように第1保持電位HL1a〜HLnaの各々は、第1フィールドF1において、走査信号GL1〜GLmがハイレベルからローレベルに遷移すると、負極性電位から正極性電位に遷移する。一方、第2保持電位HL1b〜HLnbは第1保持電位HL1a〜HLnaを反転したものである。例えば、第1行の第1保持容量線30aに供給される第1保持電位HL1aは、走査信号GL1が時刻t1においてハイレベルからローレベルに遷移すると、負極性電位から正極性電位に遷移する。一方、第1行の第2保持容量線30bに供給される第2保持電位HL1bは、時刻t1において正極性電位から負極性電位に遷移する。   FIG. 9 is a timing chart illustrating the operation of the electro-optical device according to the second embodiment. As shown in the figure, each of the first holding potentials HL1a to HLna transitions from the negative potential to the positive potential when the scanning signals GL1 to GLm transition from the high level to the low level in the first field F1. On the other hand, the second holding potentials HL1b to HLnb are obtained by inverting the first holding potentials HL1a to HLna. For example, the first holding potential HL1a supplied to the first holding capacitor line 30a in the first row changes from a negative potential to a positive potential when the scanning signal GL1 changes from a high level to a low level at time t1. On the other hand, the second holding potential HL1b supplied to the second holding capacitor line 30b in the first row transitions from the positive potential to the negative potential at time t1.

第2実施形態においても、第1実施形態と同様に、第1データ線10aを奇数行の画素回路Pに接続する一方、第2データ線10bを偶数行に接続することによって、1本のデータ線10に供給されるデータ信号Xの極性を揃えることができ、データ線10の電位の変動を抑圧することができる。この結果、消費電力を大幅に削減することが可能となる。   Also in the second embodiment, as in the first embodiment, one data is connected by connecting the first data line 10a to the odd-numbered pixel circuit P and connecting the second data line 10b to the even-numbered row. The polarity of the data signal X supplied to the line 10 can be made uniform, and fluctuations in the potential of the data line 10 can be suppressed. As a result, power consumption can be greatly reduced.

図10に第2実施形態における画像表示領域Aのレイアウトの一部を示す。第1データ線10aおよび第2データ線10bは、ソース配線層によって形成される。また、走査線20、第1保持容量線30aおよび第2保持容量線30bはゲート配線層によって形成される。さらに、保持容量70はTFT50のドレインと一体に形成された半導体層とゲート絶縁膜とゲート配線層とによって構成される。保持容量70は第1保持容量線30aと第2保持容量線30bとの間に形成され、ゲート配線層で構成される第2端子72が第1保持容量線30aまたは第2保持容量線30bと接続される。   FIG. 10 shows a part of the layout of the image display area A in the second embodiment. The first data line 10a and the second data line 10b are formed by a source wiring layer. The scanning line 20, the first storage capacitor line 30a, and the second storage capacitor line 30b are formed by a gate wiring layer. Further, the storage capacitor 70 includes a semiconductor layer, a gate insulating film, and a gate wiring layer that are formed integrally with the drain of the TFT 50. The storage capacitor 70 is formed between the first storage capacitor line 30a and the second storage capacitor line 30b, and the second terminal 72 constituted by the gate wiring layer is connected to the first storage capacitor line 30a or the second storage capacitor line 30b. Connected.

なお、本実施形態において、上述した第1保持電位HL1a〜HLnaおよび第2保持電位HL1b〜HLnbは、負極正電位と正極性電位との間で電位を遷移させるタイミングを1水平走査期間ごとにずらしたが、1フィールドごとに負極正電位と正極性電位との間で電位を遷移させるのであれば、全部を同一のタイミングで実行してもよい。   In the present embodiment, the first holding potentials HL1a to HLna and the second holding potentials HL1b to HLnb described above are shifted in timing for shifting the potential between the negative positive potential and the positive potential every horizontal scanning period. However, as long as the potential is shifted between the negative polarity positive potential and the positive polarity potential for each field, all may be executed at the same timing.

<3.第3実施形態>
第1実施形態および第2実施形態の電気光学装置は、液晶に光の射出方向の縦電界を印加するものであった。これに対して、第3実施形態の電気光学装置は、液晶に光の射出方向と直交する方向の横電界を印加するものである。このため、液晶に電圧を印加する第1電極63と第2電極64とが同一の層で構成される。
<3. Third Embodiment>
The electro-optical devices according to the first and second embodiments apply a vertical electric field in the light emission direction to the liquid crystal. In contrast, the electro-optical device according to the third embodiment applies a lateral electric field to the liquid crystal in a direction orthogonal to the light emission direction. For this reason, the 1st electrode 63 and the 2nd electrode 64 which apply a voltage to a liquid crystal are comprised by the same layer. The electro-optical devices according to the first and second embodiments apply a vertical electric field in the light emission direction to the liquid crystal. In contrast, the electro-optical devices according to the third embodiment applies a lateral electric field to the liquid crystal in For this reason, the 1st electrode 63 and the 2nd electrode 64 which apply a voltage to a liquid crystal are sintered by the same layer.

図11に画像表示領域Aおよびデータ線駆動回路200の一部の詳細な構成を示す。この図に示すように液晶素子60は保持容量70と並列に接続される。より具体的には、液晶素子60の第1電極63と保持容量70の第1端子71とが接続され、液晶素子60の第2電極64と保持容量70の第2端子72とが接続される。   FIG. 11 shows a detailed configuration of part of the image display area A and the data line driving circuit 200. As shown in this figure, the liquid crystal element 60 is connected in parallel with the storage capacitor 70. More specifically, the first electrode 63 of the liquid crystal element 60 and the first terminal 71 of the storage capacitor 70 are connected, and the second electrode 64 of the liquid crystal element 60 and the second terminal 72 of the storage capacitor 70 are connected. .

データ線10の方向(列方向)に配列された画素回路は、交互に第1データ線10aと第2データ線10bに接続される。この例では、奇数行の画素回路Pが第1データ線10aと接続される一方、偶数行の画素回路Pが第2データ線10bに接続される。換言すれば、データ線10の方向に隣接する画素回路において、一方の画素回路は第1データ線10aと電気的に接続され、他方の画素回路は第2データ線10bと電気的に接続される。また、保持容量線30はデータ線10の方向(列方向)に隣接する画素回路Pの間に設けられているが、走査線20の方向(行方向)に配置された画素回路Pは、上側の保持容量線30と下側の保持容量線30とに交互に接続される。   The pixel circuits arranged in the direction of the data line 10 (column direction) are alternately connected to the first data line 10a and the second data line 10b. In this example, the odd-numbered pixel circuit P is connected to the first data line 10a, while the even-numbered pixel circuit P is connected to the second data line 10b. In other words, in the pixel circuits adjacent in the direction of the data line 10, one pixel circuit is electrically connected to the first data line 10a, and the other pixel circuit is electrically connected to the second data line 10b. . The storage capacitor line 30 is provided between the pixel circuits P adjacent to each other in the direction of the data line 10 (column direction), but the pixel circuit P arranged in the direction of the scanning line 20 (row direction) Are alternately connected to the storage capacitor line 30 and the lower storage capacitor line 30.

次に、図12を参照して、電気光学装置の動作を説明する。まず、第1データ線10a,10bに供給されるデータ信号X1b,X2a,X3b…は、第1フィールドF1において負極性となる一方、第2フィールドF2において正極性になる。一方、第2でーた信号X1a,X2b,X3b…は、第1フィールドF1において正極性となる一方、第2フィールドF2において負極性になる。本実施形態における電位の極性は、液晶素子60の第1電極63および第2電極64に印加される最大電位と最小電位との平均電位を基準電位としたとき、基準電位より高電位を正極性、基準電位より低電位を負極性と定める。   Next, the operation of the electro-optical device will be described with reference to FIG. First, the data signals X1b, X2a, X3b... Supplied to the first data lines 10a, 10b are negative in the first field F1, and positive in the second field F2. On the other hand, the second signals X1a, X2b, X3b... Have a positive polarity in the first field F1, and a negative polarity in the second field F2. The polarity of the potential in the present embodiment is such that when the average potential of the maximum potential and the minimum potential applied to the first electrode 63 and the second electrode 64 of the liquid crystal element 60 is a reference potential, a potential higher than the reference potential is positive. A potential lower than the reference potential is defined as negative polarity.

また、保持電位CL1、CL2、…CLmは、走査信号GL1〜GLmがハイレベルとなるデータ信号の書き込み期間が終了した後、正極性電位から負極性電位へ、あるいは負極性電位から正極性電位へ変化する。すなわち、保持電位CL1〜CLmは各行の画素回路Pに対してデータ信号を書き込む期間の前後で正極性電位と負極性電位との間で遷移する。   Further, the holding potentials CL1, CL2,... CLm are changed from the positive potential to the negative potential or from the negative potential to the positive potential after the writing period of the data signal in which the scanning signals GL1 to GLm are at the high level is completed. Change. That is, the holding potentials CL1 to CLm transition between a positive potential and a negative potential before and after a period in which a data signal is written to the pixel circuits P in each row.

図13および図14を参照して、画素回路Pにおける各種のノードの電位を説明する。図13は第1フィールドF1でのノード電位の変化を示し、図14は第2フィールドF2でのノード電位の変化を示す。画素回路P11に着目すると、走査信号GL1がハイレベルとなる書き込み期間において、保持電位CL1は電位V-max(負極性電位)となっている。この状態でデータ信号X1aが画素電極61に供給されると、画素電極電位PX11がデータ信号X1aの電位に漸近する。このとき、液晶素子60の容量および保持容量70に電圧ΔV11が印加される。そして、走査信号GL1がハイレベルからローレベルに遷移すると、TFT50がオフ状態となり画素電極61はフローティング状態となる。このとき、保持電位CL1が負極性電位から正極性電位に遷移する。すると、保持容量70の第2端子72および液晶素子60の第2電極64の電位が正極性電位に変化し、これに伴って保持容量70の第1端子71の電位および液晶素子60の第2電極64の電位が上昇するが、液晶素子60に印加された電圧ΔV11は維持される。   The potentials of various nodes in the pixel circuit P will be described with reference to FIGS. FIG. 13 shows a change in node potential in the first field F1, and FIG. 14 shows a change in node potential in the second field F2. Focusing on the pixel circuit P11, the holding potential CL1 is at the potential V-max (negative potential) in the writing period in which the scanning signal GL1 is at a high level. When the data signal X1a is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX11 gradually approaches the potential of the data signal X1a. At this time, the voltage ΔV 11 is applied to the capacitor of the liquid crystal element 60 and the storage capacitor 70. When the scanning signal GL1 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in a floating state. At this time, the holding potential CL1 transitions from the negative potential to the positive potential. Then, the potential of the second terminal 72 of the storage capacitor 70 and the second electrode 64 of the liquid crystal element 60 changes to a positive potential, and accordingly, the potential of the first terminal 71 of the storage capacitor 70 and the second potential of the liquid crystal element 60 are changed. Although the potential of the electrode 64 rises, the voltage ΔV11 applied to the liquid crystal element 60 is maintained.

次に、画素回路P21では、走査信号GL2がハイレベルとなる書き込み期間において、保持電位CL2は正極性電位となっている。この状態でデータ信号X1bが画素電極61に供給されると、画素電極電位PX21がデータ信号X1bの電位に漸近する。このとき、液晶素子60の容量および保持容量70に電圧ΔV21が印加される。そして、走査信号GL2がハイレベルからローレベルに遷移すると、TFT50がオフ状態となり画素電極61はフローティング状態となる。このとき、保持電位CL2が正極性電位から負極性電位に遷移する。すると、保持容量70の第2端子72および液晶素子60の第2電極64の電位が負極性電位に変化し、これに伴って保持容量70の第1端子71の電位が下降するが、液晶素子60に印加された電圧ΔV21は維持される。
.. Next, in the pixel circuit P21, the holding potential CL2 is a positive potential in the writing period in which the scanning signal GL2 is at a high level. When the data signal X1b is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX21 gradually approaches the potential of the data signal X1b. At this time, the voltage ΔV 21 is applied to the capacitor of the liquid crystal element 60 and the storage capacitor 70. When the scanning signal GL2 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in a floating state. At this time, the holding potential CL2 transits from the positive potential to the negative potential. Then, the potential of the second terminal 72 of the storage capacitor 70 and the second electrode 64 of the liquid crystal element 60 changes to a negative potential, and the potential of the first terminal 71 of the storage capacitor 70 decreases accordingly. The voltage ΔV21 applied to Next, in the pixel circuit P21, the holding potential CL2 is a positive potential in the writing period in which the scanning signal GL2 is at a high level. When the data signal X1b is supplied to the pixel electrode 61 in this state, the pixel electrode potential PX21 gradually approaches the potential of the data signal X1b. At this time, the voltage ΔV 21 is applied to the capacitor of the liquid crystal element 60 and the storage capacitor 70. When the scanning signal GL2 transitions from the high level to the low level, the TFT 50 is turned off and the pixel electrode 61 is in a floating state. At this time, the holding potential CL2 transits from the positive potential to the negative potential. Then, the potential of the second terminal 72 of the storage capacitor 70 and the second electrode 64 of the liquid crystal element 60 changes to a negative potential, and the potential of the first terminal 71 of the storage capacitor 70 decreases accordingly. The voltage ΔV21 applied to 60 is maintained. 60 is maintained.
. ..

次に、画素回路P12では、図11に示すように下側の保持容量線30に接続されるので、保持電位CL2が供給される。この例では、走査信号GL1がハイレベルになると、正極性のデータ信号X2aが画素電極61に供給され、画素電極電位PX12がデータ信号X2aの電位に漸近する。そして、走査信号GL1がハイレベルからローレベルに遷移して書き込み期間が終了しても、保持電位CL2は正極性電位を維持するが次の書き込み期間で走査信号GL2がハイレベルからローレベルに遷移すると保持電位GL2の極性は反転し負極性電位になる。このため、液晶素子60には電圧ΔV12が印加される。   Next, since the pixel circuit P12 is connected to the lower storage capacitor line 30 as shown in FIG. 11, the storage potential CL2 is supplied. In this example, when the scanning signal GL1 becomes high level, the positive data signal X2a is supplied to the pixel electrode 61, and the pixel electrode potential PX12 gradually approaches the potential of the data signal X2a. Even when the scanning signal GL1 changes from the high level to the low level and the writing period ends, the holding potential CL2 maintains the positive potential, but the scanning signal GL2 changes from the high level to the low level in the next writing period. Then, the polarity of the holding potential GL2 is reversed and becomes a negative potential. For this reason, the voltage ΔV12 is applied to the liquid crystal element 60.

第3実施形態では、第1および第2実施形態と同様に、第1データ線10aを奇数行の画素回路Pに接続する一方、第2データ線10bを偶数行に接続することによって、1本のデータ線10に供給されるデータ信号Xの極性を揃えることができ、データ線10の電位の変動を抑圧することができる。この結果、消費電力を大幅に削減することが可能となる。
なお、横電界方式の第3実施形態においても、第2実施形態と同様に1行あたり2本の保持容量線30を用いて、液晶素子60に印加される電圧を制御してもよい。
また、上述した各実施形態の電気光学装置500は、電気光学物質に液晶を用いた液晶表示装置であり、この液晶表示装置は、透過型、反射型または半透過半反射型のいずれにも適用可能である。 Further, the electro-optical device 500 of each of the above-described embodiments is a liquid crystal display device using a liquid crystal as an electro-optical material, and this liquid crystal display device can be applied to any of a transmissive type, a reflective type, and a semitransparent semi-reflective type. It is possible. In the third embodiment, as in the first and second embodiments, the first data line 10a is connected to the pixel circuits P in the odd-numbered rows, while the second data line 10b is connected to the even-numbered rows. The polarity of the data signal X supplied to the data line 10 can be made uniform, and fluctuations in the potential of the data line 10 can be suppressed. As a result, power consumption can be greatly reduced. In the third embodiment, as in the first and second embodiments, the first data line 10a is connected to the pixel circuits P in the odd-numbered rows, while the second data line 10b is connected to the even-numbered rows. The data signal X supplied to the data line 10 can be made uniform, and fluctuations in the potential of the data line 10 can be suppressed. As a result, power consumption can be greatly reduced.
Also in the third embodiment of the horizontal electric field method, the voltage applied to the liquid crystal element 60 may be controlled using two storage capacitor lines 30 per row as in the second embodiment. Also in the third embodiment of the horizontal electric field method, the voltage applied to the liquid crystal element 60 may be controlled using two storage capacitor lines 30 per row as in the second embodiment.
In addition, the electro-optical device 500 of each embodiment described above is a liquid crystal display device using liquid crystal as an electro-optical material, and this liquid crystal display device is applicable to any of a transmissive type, a reflective type, and a transflective type. Is possible. In addition, the electro-optical device 500 of each embodiment described above is a liquid crystal display device using liquid crystal as an electro-optical material, and this liquid crystal display device is applicable to any of a transmissive type, a reflective type, and a transflective type. Is possible.

<4.電子機器>
次に、本発明に係る電気光学装置500を利用した電子機器について説明する。 Next, an electronic device using the electro-optical device 500 according to the present invention will be described. 図15は、以上に説明した何れかの形態に係る電気光学装置500を表示装置として採用したモバイル型のパーソナルコンピュータの構成を示す斜視図である。 FIG. 15 is a perspective view showing the configuration of a mobile personal computer that employs the electro-optical device 500 according to any of the above-described forms as a display device. パーソナルコンピュータ2000は、表示装置としての電気光学装置500と本体部2010とを備える。 The personal computer 2000 includes an electro-optical device 500 as a display device and a main body 2010. 本体部2010には、電源スイッチ2001およびキーボード2002が設けられている。 The main body 2010 is provided with a power switch 2001 and a keyboard 2002. この電気光学装置500は消費電力を低減することができるので、バッテリーの駆動においても連続使用時間を伸ばすことが可能となる。 Since the electro-optical device 500 can reduce power consumption, it is possible to extend the continuous use time even when driving the battery. <4. Electronic equipment> <4. Electronic equipment>
Next, an electronic apparatus using the electro-optical device 500 according to the present invention will be described. FIG. 15 is a perspective view illustrating a configuration of a mobile personal computer that employs the electro-optical device 500 according to any one of the embodiments described above as a display device. The personal computer 2000 includes an electro-optical device 500 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. Since the electro-optical device 500 can reduce power consumption, the continuous use time can be extended even when the battery is driven. Next, an electronic apparatus using the electro-optical device 500 according to the present invention will be described. FIG. 15 is a perspective view illustrating a configuration of a mobile personal computer that employs the electro-optical device 500 according to any one of the Forms described above as a display device. The personal computer 2000 includes an electro-optical device 500 as a display device and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. Since the electro-optical device 500 can reduce power consumption, the continuous use time can be extended even when the battery is driven.

図16に、実施形態に係る電気光学装置500を適用した携帯電話機の構成を示す。携帯電話機3000は、複数の操作ボタン3001およびスクロールボタン3002、ならびに表示装置としての電気光学装置500を備える。スクロールボタン3002を操作することによって、電気光学装置500に表示される画面がスクロールされる。   FIG. 16 shows a configuration of a mobile phone to which the electro-optical device 500 according to the embodiment is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and an electro-optical device 500 as a display device. By operating the scroll button 3002, the screen displayed on the electro-optical device 500 is scrolled.

図17に、実施形態に係る電気光学装置500を適用した携帯情報端末(PDA:Personal Digital Assistants)の構成を示す。情報携帯端末4000は、複数の操作ボタン4001および電源スイッチ4002、ならびに表示装置としての電気光学装置500を備える。電源スイッチ4002を操作すると、住所録やスケジュール帳といった各種の情報が電気光学装置500に表示される。   FIG. 17 shows a configuration of a personal digital assistant (PDA) to which the electro-optical device 500 according to the embodiment is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and an electro-optical device 500 as a display device. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the electro-optical device 500.

なお、本発明に係る電気光学装置が適用される電子機器としては、図15から図17に示したもののほか、プロジェクタ、デジタルスチルカメラ、テレビ、ビデオカメラ、カーナビゲーション装置、ページャ、電子手帳、電子ペーパー、電卓、ワードプロセッサ、ワークステーション、テレビ電話、POS端末、プリンタ、スキャナ、複写機、ビデオプレーヤ、タッチパネルを備えた機器等などが挙げられる。   Note that electronic devices to which the electro-optical device according to the present invention is applied include projectors, digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic devices, in addition to those shown in FIGS. Examples include a paper, a calculator, a word processor, a workstation, a videophone, a POS terminal, a printer, a scanner, a copying machine, a video player, and a device equipped with a touch panel.

本発明の第1実施形態に係る電気光学装置のブロック図である。 1 is a block diagram of an electro-optical device according to a first embodiment of the invention. FIG. 同装置の画像表示領域およびデータ線駆動回路の一部の詳細な構成を示す回路図である。 FIG. 2 is a circuit diagram showing a detailed configuration of part of an image display region and a data line driving circuit of the same device. 同装置の動作を示すタイミングチャートである。 It is a timing chart which shows operation | movement of the apparatus. 同装置の画素回路の第1フィールドにおける各種のノードの電位を示す説明図である。 It is explanatory drawing which shows the electric potential of the various nodes in the 1st field of the pixel circuit of the apparatus. 同装置の画素回路の第2フィールドにおける各種のノードの電位を示す説明図である。 It is explanatory drawing which shows the electric potential of the various nodes in the 2nd field of the pixel circuit of the apparatus. 同装置のドット反転方式を説明するための概念図である。 It is a conceptual diagram for demonstrating the dot inversion system of the same apparatus. 同装置の画像表示領域のレイアウトの一部を示す平面図である。 It is a top view which shows a part of layout of the image display area of the apparatus. 本発明の第2実施形態に係る電気光学装置に用いる画像表示領域およびデータ線駆動回路の一部の詳細な構成を示す回路図である。 FIG. 6 is a circuit diagram illustrating a detailed configuration of part of an image display region and a data line driving circuit used in an electro-optical device according to a second embodiment of the invention. 同装置の動作を示すタイミングチャートである。 It is a timing chart which shows operation | movement of the apparatus. 同装置の画像表示領域のレイアウトの一部を示す平面図である。 It is a top view which shows a part of layout of the image display area of the apparatus. 本発明の第3実施形態に係る電気光学装置に用いる画像表示領域およびデータ線駆動回路の一部の詳細な構成を示す回路図である。 FIG. 9 is a circuit diagram illustrating a detailed configuration of part of an image display region and a data line driving circuit used in an electro-optical device according to a third embodiment of the invention. 同装置の動作を示すタイミングチャートである。 It is a timing chart which shows operation | movement of the apparatus. 同装置の画素回路の第1フィールドにおける各種のノードの電位を示す説明図である。 It is explanatory drawing which shows the electric potential of the various nodes in the 1st field of the pixel circuit of the apparatus. 同装置の画素回路の第2フィールドにおける各種のノードの電位を示す説明図である。 It is explanatory drawing which shows the electric potential of the various nodes in the 2nd field of the pixel circuit of the apparatus. 電子機器の一例たるパーソナルコンピュータの斜視図である。 It is a perspective view of the personal computer which is an example of an electronic device. 電子機器の一例たる携帯電話機の斜視図である。 It is a perspective view of the mobile telephone which is an example of an electronic device. 電子機器の一例たる携帯情報端末の斜視図である。 It is a perspective view of the portable information terminal which is an example of an electronic device.

符号の説明Explanation of symbols

10……データ線、10a……第1データ線、10b……第2データ線、20……走査線、30……保持容量線、30a……第1保持容量線、30b……第2保持容量線、50……TFT(スイッチング素子)、60……液晶素子、61……画素電極、62……対向電極(共通電極)、70……保持容量、71……第1端子、72……第2端子、100……走査線駆動回路(保持容量線駆動回路)、200……データ線駆動回路、500……電気光学装置、X1a〜Xma……第1データ信号、X1b〜Xmb……第2データ信号、
GL1〜GLm……走査信号、P11〜Pnm……画素回路。 GL1 to GLm ... Scanning signal, P11 to Pnm ... Pixel circuit. 10... Data line, 10 a... First data line, 10 b... Second data line, 20... Scan line, 30... Retention capacitor line, 30 a. Capacitance line 50 ... TFT (switching element) 60 ... Liquid crystal element 61 ... Pixel electrode 62 ... Counter electrode (common electrode) 70 ... Retention capacitor 71 ... First terminal 72 ... Second terminal, 100... Scanning line drive circuit (retention capacitor line drive circuit), 200... Data line drive circuit, 500... Electro-optical device, X1a to Xma. 2 data signals, 10 ... Data line, 10 a ... First data line, 10 b ... Second data line, 20 ... Scan line, 30 ... Retention capacitor line, 30 a. Capacitance line 50 ... TFT (switching element) 60 ... Liquid crystal element 61 ... Pixel electrode 62 ... Counter electrode (common electrode) 70 ... Retention capacitor 71 ... First terminal 72 ... Second terminal, 100 ... Scanning line drive circuit (retention capacitor line drive circuit), 200 ... Data line drive circuit, 500 ... Electro-optical device, X1a to Xma. 2 data signals,
GL1 to GLm: scanning signal, P11 to Pnm: pixel circuit. GL1 to GLm: scanning signal, P11 to Pnm: pixel circuit.

Claims (9)

  1. 複数の走査線と、複数のデータ線と、複数の保持容量線と、前記走査線と前記データ線との交差に対応して設けられた画素回路とを備える電気光学装置であって、
    前記画素回路は、
    前記走査線を介して供給される走査信号に従ってオン・オフが制御され、第1の端子が前記データ線と電気的に接続され、第2の端子が第1電極と電気的に接続されるスイッチング素子と、
    一方の端子が前記スイッチング素子の第2の端子と電気的に接続され、他方の端子が前記保持容量線と電気的に接続される保持容量と、
    前記第1電極と第2電極との間に設けられた電気光学物質とを備え、
    前記複数のデータ線は、各列の画素回路に対して第1データ線および第2データ線の組として設けられており、 The plurality of data lines are provided as a set of a first data line and a second data line for the pixel circuit of each column.
    前記データ線の方向に隣接する画素回路において、一方の画素回路は前記第1データ線と電気的に接続され、他方の画素回路は前記第2データ線と電気的に接続される、 In a pixel circuit adjacent in the direction of the data line, one pixel circuit is electrically connected to the first data line and the other pixel circuit is electrically connected to the second data line.
    ことを特徴とする電気光学装置。 An electro-optical device characterized by this. An electro-optical device comprising a plurality of scanning lines, a plurality of data lines, a plurality of storage capacitor lines, and a pixel circuit provided corresponding to the intersection of the scanning lines and the data lines, An electro-optical device comprising a plurality of scanning lines, a plurality of data lines, a plurality of storage capacitor lines, and a pixel circuit provided corresponding to the intersection of the scanning lines and the data lines,
    The pixel circuit includes: The pixel circuit includes:
    Switching in which on / off is controlled according to a scanning signal supplied through the scanning line, a first terminal is electrically connected to the data line, and a second terminal is electrically connected to the first electrode Elements, Switching in which on / off is controlled according to a scanning signal supplied through the scanning line, a first terminal is electrically connected to the data line, and a second terminal is efficiently connected to the first electrode Elements,
    A storage capacitor in which one terminal is electrically connected to the second terminal of the switching element and the other terminal is electrically connected to the storage capacitor line; A storage capacitor in which one terminal is electrically connected to the second terminal of the switching element and the other terminal is efficiently connected to the storage capacitor line;
    An electro-optic material provided between the first electrode and the second electrode, An electro-optic material provided between the first electrode and the second electrode,
    The plurality of data lines are provided as a set of first data lines and second data lines for the pixel circuits in each column, The plurality of data lines are provided as a set of first data lines and second data lines for the pixel circuits in each column,
    In a pixel circuit adjacent in the direction of the data line, one pixel circuit is electrically connected to the first data line, and the other pixel circuit is electrically connected to the second data line. In a pixel circuit adjacent in the direction of the data line, one pixel circuit is appropriately connected to the first data line, and the other pixel circuit is appropriately connected to the second data line.
    An electro-optical device. An electro-optical device.
  2. 一列の画素回路の各々が表示すべき階調を示し、且つ、基準電位を中心として1水平走査期間ごとに極性が反転したデータ信号を、前記走査信号による前記走査線の選択と同期して、前記第1データ線と前記第2データ線とに交互に供給するデータ線駆動回路を備えることを特徴とする請求項1に記載の電気光学装置。   A data signal indicating a gradation to be displayed by each of the pixel circuits in one column and having a polarity inverted every horizontal scanning period around the reference potential is synchronized with the selection of the scanning line by the scanning signal, The electro-optical device according to claim 1, further comprising a data line driving circuit that alternately supplies the first data line and the second data line.
  3. 基準電位を中心として高電位の正極性電位と低電位の負極性電位とを生成し、各行の画素回路を順次選択し、最初の行から最後の行までを選択する期間を1フィールドとしたとき、1フィールドごとに前記保持容量線に供給する電位を前記正極性電位と前記負極性電位との間で遷移させる保持容量線駆動手段を備えることを特徴とする請求項2に記載の電気光学装置。   When a high potential positive potential and a low potential negative potential are generated around the reference potential, the pixel circuits in each row are sequentially selected, and the period from the first row to the last row is set as one field 3. The electro-optical device according to claim 2, further comprising a storage capacitor line driving unit configured to transition a potential supplied to the storage capacitor line for each field between the positive potential and the negative potential. .
  4. 前記保持容量線は前記データ線の方向に隣接する画素回路の間に設けられており、
    前記走査線の方向に配置された画素回路は、上側の保持容量線と下側の保持容量線とに交互に電気的に接続され、
    前記保持容量線駆動手段は、
    前記複数の保持容量線に前記正極性電位と前記負極性電位とを交互に供給し、
    各行の画素回路に対して前記データ信号を書き込む期間の前後で前記保持容量線に供給する電位を前記正極性電位と前記負極性電位との間で遷移させる、
    ことを特徴とする請求項3に記載の電気光学装置。
    The storage capacitor line is provided between pixel circuits adjacent in the direction of the data line,
    The pixel circuits arranged in the direction of the scanning line are electrically connected alternately to the upper storage capacitor line and the lower storage capacitor line, The pixel circuits arranged in the direction of the scanning line are appropriately connected to the upper storage capacitor line and the lower storage capacitor line,
    The storage capacitor line driving means includes: The storage capacitor line driving means includes:
    Alternately supplying the positive potential and the negative potential to the plurality of storage capacitor lines; Alternately supplying the positive potential and the negative potential to the plurality of storage capacitor lines;
    The potential supplied to the storage capacitor line before and after the period for writing the data signal to the pixel circuits in each row is changed between the positive potential and the negative potential. The potential supplied to the storage capacitor line before and after the period for writing the data signal to the pixel circuits in each row is changed between the positive potential and the negative potential.
    The electro-optical device according to claim 3. The electro-optical device according to claim 3.
  5. 前記複数の保持容量線は、各行の画素回路に対して第1保持容量線および第2保持容量線の組として設けられており、
    前記走査線の方向に配置された画素回路は、前記第1保持容量線と前記第2保持容量線とに交互に電気的に接続され、 The pixel circuit arranged in the direction of the scanning line is electrically connected to the first holding capacitance line and the second holding capacitance line alternately.
    前記保持容量線駆動手段は、 The holding capacitance line driving means
    前記第1保持容量線に前記正極性電位と前記負極性電位とのうちいずれか一方を供給し、前記第2保持容量線にいずれか他方を供給する、 One of the positive electrode potential and the negative electrode potential is supplied to the first holding capacity line, and the other is supplied to the second holding capacity line.
    ことを特徴とする請求項3に記載の電気光学装置。 The electro-optical device according to claim 3. The plurality of storage capacitor lines are provided as a set of a first storage capacitor line and a second storage capacitor line for each row of pixel circuits, The plurality of storage capacitor lines are provided as a set of a first storage capacitor line and a second storage capacitor line for each row of pixel circuits,
    Pixel circuits arranged in the direction of the scanning line are electrically connected alternately to the first storage capacitor line and the second storage capacitor line, Pixel circuits arranged in the direction of the scanning line are appropriately connected to the first storage capacitor line and the second storage capacitor line,
    The storage capacitor line driving means includes: The storage capacitor line driving means includes:
    Supplying one of the positive potential and the negative potential to the first storage capacitor line and supplying the other to the second storage capacitor line; Supplying one of the positive potential and the negative potential to the first storage capacitor line and supplying the other to the second storage capacitor line;
    The electro-optical device according to claim 3. The electro-optical device according to claim 3.
  6. 前記第2電極は複数の画素回路に共通な共通電極であり、
    前記基準電位は前記共通電極に供給される電位である、
    ことを特徴とする請求項3乃至5のうちいずれか1項に記載の電気光学装置。
    The second electrode is a common electrode common to a plurality of pixel circuits,
    The reference potential is a potential supplied to the common electrode.
    The electro-optical device according to claim 3, wherein the electro-optical device is any one of claims 3 to 5.
  7. 前記第2電極は前記第1電極と同一の層で形成され、前記基準電位は前記データ信号の最大電位と最小電位との平均電位であることを特徴とする3乃至5のうちいずれか1項に記載の電気光学装置。 The second electrode is formed of the same layer as the first electrode, and the reference potential is an average potential of the maximum potential and the minimum potential of the data signal. The electro-optical device according to 1.
  8. 請求項1乃至7のうちいずれか1項に記載の電気光学装置を備えたことを特徴とする電子機器。 An electronic apparatus comprising the electro-optical device according to claim 1.
  9. 複数の走査線と、複数のデータ線と、複数の保持容量線と、前記走査線と前記データ線との交差に対応して設けられた画素回路とを備え、前記画素回路は、前記走査線を介して供給される走査信号に従ってオン・オフが制御され、第1の端子が前記データ線と電気的に接続され、第2の端子が第1電極と電気的に接続されるスイッチング素子と、一方の端子が前記スイッチング素子の第2の端子と電気的に接続され、他方の端子が前記保持容量線と電気的に接続される保持容量と、前記第1電極と第2電極との間に設けられた電気光学物質とを備え、前記複数のデータ線は、各列の画素回路に対して第1データ線および第2データ線の組として設けられており、前記データ線の方向に隣接する画素回路において、一方の画素回路は前記第1データ線と電気的に接続され、他方の画素回路は前記第2データ線と電気的に接続される電気光学装置の駆動方法であって、
    前記複数の走査線の各々に前記走査信号を順次供給し、 The scanning signal is sequentially supplied to each of the plurality of scanning lines, and the scanning signal is sequentially supplied.
    一列の画素回路の各々が表示すべき階調を示し、基準電位を中心として1水平走査期間ごとに極性が反転したデータ信号を生成し、 Each of the pixel circuits in a row indicates the gradation to be displayed, and a data signal whose polarity is inverted for each horizontal scanning period centered on the reference potential is generated.
    前記データ信号を、前記走査信号による前記走査線の選択と同期して、前記第1データ線と前記第2データ線とに交互に供給する、 The data signal is alternately supplied to the first data line and the second data line in synchronization with the selection of the scanning line by the scanning signal.
    ことを特徴とする電気光学装置の駆動方法。 A method of driving an electro-optic device. A plurality of scanning lines; a plurality of data lines; a plurality of storage capacitor lines; and a pixel circuit provided corresponding to the intersection of the scanning lines and the data lines. A switching element in which on / off is controlled in accordance with a scanning signal supplied via the first terminal, the first terminal is electrically connected to the data line, and the second terminal is electrically connected to the first electrode; One terminal is electrically connected to the second terminal of the switching element, and the other terminal is electrically connected to the storage capacitor line, and between the first electrode and the second electrode. The plurality of data lines are provided as a set of first data lines and second data lines for the pixel circuits in each column, and are adjacent to the direction of the data lines. In the pixel circuit, one of the pixel circuits is the first device. Data lines and is electrically connected, the other pixel c A plurality of scanning lines; a plurality of data lines; a plurality of storage capacitor lines; and a pixel circuit provided corresponding to the intersection of the scanning lines and the data lines. A switching element in which on / off is controlled in accordance with a scanning signal supplied via the first terminal, the first terminal is electrically connected to the data line, and the second terminal is efficiently connected to the first electrode; One terminal is efficiently connected to the second terminal of the switching element, and the other terminal The plurality of data lines are provided as a set of first data lines and second data lines for the pixel circuits in each column, and are adjacent to the is appropriately connected to the storage capacitor line, and between the first electrode and the second electrode. In the pixel circuits, one of the pixel circuits is the first device. Data lines and is appropriately connected, the other pixel c ircuits A driving method of an electro-optical device is electrically connected to the second data line, ircuits A driving method of an electro-optical device is electrically connected to the second data line,
    Sequentially supplying the scanning signal to each of the plurality of scanning lines; Sequentially supplying the scanning signal to each of the plurality of scanning lines;
    Each of the pixel circuits in one column indicates a gradation to be displayed, and generates a data signal whose polarity is inverted every horizontal scanning period around the reference potential. Each of the pixel circuits in one column indicates a gradation to be displayed, and generates a data signal whose polarity is inverted every horizontal scanning period around the reference potential.
    The data signal is alternately supplied to the first data line and the second data line in synchronization with the selection of the scanning line by the scanning signal. The data signal is appropriately supplied to the first data line and the second data line in synchronization with the selection of the scanning line by the scanning signal.
    A driving method for an electro-optical device. A driving method for an electro-optical device.
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