JP2008047943A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent dissipation of conductive particles inserted and held between a bump electrode at the side of a semiconductor device such as an LCD driver, and an opposing side electrode such as an electrode at the side of a mounting substrate connected with being opposing to the bump electrode, during mounting, so that an electrical continuity property between the both electrodes can be sufficiently ensured. <P>SOLUTION: A frame like convex portion is formed along the periphery of the electrode surface of a bump electrode 14 and serves as a stopper 14a. A wiring electrode 11 having a layer thickness that can be changed is provided below the position where the stopper 14a is formed, so that the height of the stopper 14a can be adjusted in accordance with the particle diameter of conductive particles in an anisotropic conductive film used during mounting. The height adjustment of the stopper 14a may be performed, for example, by a lamination structure of the wiring electrode 11 and a passivation film 12. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and is particularly effective when applied to a semiconductor device mounted by a flip chip method using bump electrodes.

  The technology described below has been studied by the present inventors in researching and completing the present invention, and the outline thereof is as follows.

  In semiconductor devices such as semiconductor chips, there is a strong demand for downsizing and high-density mounting. In response to such technical requirements, there is a so-called flip chip mounting technology in which a semiconductor chip provided with a bump electrode is aligned with the mounting substrate side in a face-down state and the bump electrode and the mounting substrate side electrode are connected. Widely adopted.

  Various mounting methods such as a chip on glass (COG) method, a chip on film (COF) method, and a chip on board (COB) method are known as such flip chip mounting methods. Yes.

  In recent years, in the field of liquid crystal technology where high definition and an increase in the number of pixels are required, for example, as a mounting method of an LCD driver for controlling voltage switching related to liquid crystal display, the conventional TCP (Tape Carrier Package) Instead of the method, the above method is actively adopted.

  The flip chip mounting is generally performed by interposing an anisotropic conductive film made of an anisotropic conductive resin between the bump electrode on the semiconductor device side and the mounting substrate side electrode, This is done by heat-pressing the bump electrode to the mounting substrate side electrode.

  The electrical connection between the bump electrode and the mounting substrate side electrode during such mounting is caused by the conductive particles contained in the anisotropic conductive film being crushed by being interposed between the bump electrode and the mounting substrate side electrode. Secured.

  That is, the conductive particles contained in the anisotropic conductive film are sandwiched between the bump electrode and the mounting substrate side electrode by thermocompression bonding so that both electrodes can be electrically connected. As a result, electrical connection is ensured through the route of bump electrode-conductive particle-mounting substrate side electrode.

  In order to secure the electrical connection between the two electrodes with the intervening conductive particles as an intermediary, it is necessary to increase the density of the conductive particles between the two electrodes.

  However, when non-uniformity occurs in the pressure bonding of the bump electrode to the mounting substrate side electrode during mounting, the density of the conductive particles interposed between the two electrodes is relatively lower than that of the normal pressure portion in the insufficient pressure portion. It tends to be rough, and crushing is hardly performed.

  In such under-pressurized portions, the conductive particles interposed between both electrodes are less compressed between the two electrodes than in the normal pressurized portion, and the conductive particles or between the electrodes and the conductive particles The degree of contact may be relatively weak or may be in a non-contact state. In such a case, the electrical resistance at that portion becomes high, and sufficient continuity between the two electrodes cannot be ensured.

  For example, if a potential difference is applied between both electrodes, a current will surely flow, but a sufficient current does not flow from the beginning, and an abnormality such as it takes time to sufficiently increase the voltage occurs. By smoothly switching the voltage, an LCD driver for a liquid crystal display that changes the liquid crystal state and displays it becomes a serious obstacle that makes it impossible to ensure the clearness of the liquid crystal display.

  In addition, in the inspection of a finished product of a semiconductor device such as a completed LCD driver, such an abnormality is caused by a slow reaction or no continuity when a probe for inspection is applied to a predetermined position to inspect the continuity. If the contact position is changed by moving the probe slightly, it becomes one of the causes of a problem phenomenon at the time of inspection such as continuity being confirmed.

  One of the major causes of such conduction abnormality is due to the surface shape of the bump electrode. The bump electrode is formed by removing the passivation film on the wiring electrode provided in the semiconductor device by etching or the like, and forming an electrode thereon by means such as plating.

  Therefore, in the bump electrode formed in this manner, a depression reflecting the step between the passivation film surface and the wiring electrode surface when the wiring film is exposed by etching the passivation film is formed on the electrode surface. It becomes.

  When a semiconductor device having a bump electrode having such a configuration is face-down mounted in a flip-chip manner, the electrode surface having a recess faces the mounting substrate side electrode, and the anisotropic conductive film interposed between both electrodes The pressing force to the conductive particles is slightly different between the recessed portion and the peripheral portion where the recessed portion is not recessed. That is, pressure non-uniformity occurs during mounting.

  Therefore, as a countermeasure, a means has been proposed in which the step between the passivation film surface and the wiring electrode surface is reduced by reducing the thickness of the passivation film. However, reducing the thickness of the passivation film, on the other hand, leads to a decrease in the insulation properties, and the technology for ensuring the conductivity between the bump electrode and the electrode on the mounting substrate side without reducing the thickness of the passivation film. Development of was desired.

  As a technique for solving such a problem, it has been considered to flatten the surface of the bump electrode. However, in the method of providing a passivation film on the wiring electrode and forming the bump electrode in the opening of the passivation film, the step corresponding to the passivation film thickness cannot be eliminated. A method has been proposed in which the influence of the step is reduced to such an extent that the entire electrode surface can be considered flat.

  For example, in order to reduce the planar size of the dimple on the surface of the conductive bump and suppress the influence of the step portion based on the dimple, a configuration in which a plurality of small dimples are formed instead of forming one large dimple is proposed. (For example, refer to Patent Document 1).

  As a method for forming the bump electrode, for example, in the case of a gold bump electrode, a method is known in which gold plating is grown on an Al pad serving as a wiring electrode that is opened and exposed in a passivation film. The plating grows along the vertical direction, but also grows in the horizontal direction.

Therefore, the opening provided in the passivation film is set to be small in advance, and when the bump electrode is formed by gold plating in the opening, the recess of the ridge formed in accordance with the opening is filled by the lateral growth of the plating. A technique that can be called pseudo-planarization has been proposed (see, for example, Patent Document 2).
JP 11-31698 (paragraphs 0013, 0023, 0024, FIGS. 6, 7, 8) JP-A-11-258620 (paragraphs 0038, 0048, 0049, FIGS. 3 and 4)

  However, the present inventors have found that the bump electrode level difference elimination technique has the following problems.

  That is, the bump electrode level difference elimination technique does not form a single large depression in the area where the depression on the electrode surface is formed, but rather a large number of electrical connections on the wiring electrode in the depression formation area. It can be said that a small concave portion is formed, that is, a large number of fine concave and convex portions are formed, and the upper surface of the large number of convex portions makes a pseudo plane.

  The idea of such pseudo planarization is that, as described above, in flip-chip mounting, conduction failure in electrical connection between the bump electrode and the mounting substrate side electrode via the anisotropic conductive film is caused on the electrode surface. The main reason is that a recess reflecting the step between the passivation film surface and the wiring electrode surface when the wiring electrode is exposed by etching the passivation film, and it is preferable to eliminate the stepped portion. It was proposed based on the premise.

  In other words, although it is technically desirable that the method of pseudo planarization completely eliminates the stepped portion and flattenes it, it is considered to be substantially flat within an allowable range even if it cannot be performed so far. The idea is to flatten to the extent that it can fade.

  The present inventor has been engaged in technical development related to the elimination of the bump electrode level difference for many years. However, the present inventor has noticed that there is a major problem with the above premise involved in the elimination of such a problem.

  That is, it has been found that the assumptions made so far that flattening the electrode surface as much as possible will lead to the elimination of the poor electrical connection due to the above-described steps may not always be correct.

  In the microscopic observation of the inventor, as a result of investigating the behavior of the conductive particles between the bump electrode and the mounting substrate side electrode in a state where advanced flattening has been advanced, It was found that in part, the conductive particles tend to escape in the peripheral direction from the relative range of the bump electrode and the mounting substrate side electrode as compared with the case where there is a portion.

  In other words, when the flattening is performed with the aim of eliminating the level difference on the electrode surface, the interposition between the mounting substrate side electrode and the bump electrode of the conductive particles is improved in accordance with the improvement of the flattening degree. Although the conduction failure in the mounting using the film can be solved, it has been found that if the flatness degree is set to a certain level, the intervening property of the conductive particles may be deteriorated. Such knowledge has been found for the first time by increasing the degree of flatness of the electrode surface of the bump electrode, and until now no such problem has been recognized.

  In other words, aiming to substantially eliminate the stepped portion, simply increasing the flatness degree does not improve the intervening density of the conductive particles as expected, while increasing the flatness degree. Measures to prevent escape of conductive particles during mounting are considered necessary.

  An object of the present invention is to ensure sufficient electrical conductivity between a bump electrode on a semiconductor device side such as an LCD driver and a counterpart electrode such as a mounting substrate side electrode connected to the bump electrode. is there.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, according to the present invention, a stopper is provided on the electrode surface of the bump electrode of the semiconductor device, and the periphery of the conductive particles in the anisotropic conductive film interposed between the mounting substrate side electrode and the bump electrode is pressed between them. Even when dissipation to the surface is prevented and the level of flatness of the bump electrode surface is improved, a high intervening density of the conductive particles can be ensured.

  In addition, the stopper has a laminated structure that can be appropriately changed in design according to the diameter of the conductive particles in the interposed anisotropic conductive film.

  The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.

  That is, it is possible to improve the flatness of the surface of the bump electrode and improve the conductivity between the bump electrode and the counterpart electrode.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1A is a main part sectional view schematically showing a configuration of a bump electrode in a semiconductor device according to an embodiment of the present invention, and FIG. 1B is a configuration when viewed from the direction of the arrow in FIG. It is principal part sectional drawing which shows this typically.

  In the present embodiment, a case where the semiconductor device 10 is configured as an LCD driver 10a will be described as an example. As shown in FIG. 1A, a wiring electrode 11 made of Al or the like is provided on the surface of the semiconductor device 10. A passivation film 12 is provided on the wiring electrode 11, and a base metal layer (also referred to as a UMB layer) 13 is provided thereon. A bump electrode 14 is formed on the base metal layer 13.

  As shown in FIG. 1A, the bump electrode 14 has a convex stopper 14 a formed integrally with the bump electrode 14 on the peripheral side. The height H of the stopper 14 a is defined based on the layer thickness of the wiring electrode 11.

  The wiring electrode 11 is provided in a frame shape along the peripheral edge of the formation range of the bump electrode 14 shown in FIG. On the periphery of the surface of the bump electrode 14, a stopper 14 a swelled in a convex shape whose height is defined based on the layer thickness of the wiring electrode 11 provided in a frame shape is formed. The surface of the bump electrode 14 on the side surrounded by the stopper 14a is formed in a flat portion 14b having a flat electrode surface.

  In addition, the stopper 14a is formed so that the width D is set narrow and the peripheral portion of the electrode surface is slightly raised, so that the area of the flat portion 14b surrounded by the stopper 14a can be ensured as wide as possible.

  The width D of the stopper 14a is preferably 2 μm or more and less than 5 μm, for example. Thus, by setting the width D to be narrow, the ratio of the flat portion 14b involved in electrical connection can be increased by reducing the occupation ratio of the stopper 14a on the electrode surface.

  In addition, by reducing the width D of the stopper 14a without changing the area occupied by the flat portion 14b, the electrode surface of the bump electrode 14 can be set to be small as a whole while maintaining the conductivity. This is effective for increasing the number of bump electrodes 14 installed in the range.

  In the conventional configuration using a wafer with bumps in TCP (Tape Carrier Package), a chip with Au bumps for TCP requires a structure in which an Al pad is always placed under the Au bumps to relieve stress during assembly. It was. However, when adopting a mounting method such as COG that does not require consideration of stress relaxation by the wiring electrodes, it is not necessarily necessary to adopt such an Al pad arrangement configuration, and as described above, it is framed. A configuration in which the wiring electrode 11 is provided is newly adopted.

  The electrical connection between the bump electrode 14 and the wiring electrode 11 is as shown in the cross-sectional view of the main part of FIG. 1B schematically showing the configuration viewed from the direction of the arrow in FIG. This is ensured by electrically connecting the underlying metal layer 13 provided below to the wiring electrode 11 through the through hole 15.

  In the bump electrode 14 having such a configuration, as shown in FIG. 2, since the stopper 14a is provided on the periphery of the bump electrode surface, the electrode 17a on the substrate 17 side with the anisotropic conductive film 16 interposed therebetween. In mounting, the stopper 14a can prevent dissipation to the periphery of the conductive particles 16a in the anisotropic conductive film 16.

  By preventing the conductive particles 16a from being dissipated in this way, the conductive particles 16a are held in the flat portion 14b of the bump electrode 14 even when the bump electrode 14 and the substrate 17 are pressure-bonded at the time of mounting. The density of the conductive particles 16a between the electrode 14 and the substrate 17 can be increased.

  In the configuration in which the electrode surface of the bump electrode 14 is highly planarized without providing the stopper 14a, the interposed anisotropic conductive film 16 is crushed between the bump electrode 14 and the substrate 17 during mounting. In some cases, a part of the conductive particles 16a in the anisotropic conductive film 16 is dissipated so as to be pushed out to the periphery, and in some cases, sufficient conductivity cannot be ensured. Cases are also envisaged.

  For example, as schematically shown in FIG. 3A, in the conventional bump electrode 21 in a state in which the electrode surface has been flattened, the bumps 21a are more specifically formed on the peripheral edge of the electrode after bump annealing. The inner side excluding the peripheral edge is formed in the flat portion 21b.

  Therefore, when mounting is performed using the bump electrode 21 having such a configuration, the anisotropic conductive film 16 is interposed on the electrode 17a side made of Al or the like of the substrate 17 as shown in FIG. When the bump electrode 21 is pressed as shown by the arrow in the figure to achieve electrical connection, as shown by the horizontal arrow in the figure, the conductive particles 16a leak to the surroundings when pressed, causing dissipation. Will be.

  As a result, the number of conductive particles 16a interposed between the electrodes 17a of the substrate 17 and the bump electrodes 21 to ensure electrical connection is reduced, the density of the interposition is lowered, and in some cases, poor connection occurs. Is also fully concerned.

  However, in the present invention, as shown in FIG. 2, when pressed during mounting, the conductive particles 16a are prevented from dissipating by the peripheral stopper 14a and are enclosed in the flat portion 14b of the electrode surface. Thus, the electrical connection is sufficiently ensured.

  From the viewpoint of the stopper function, if the height H of the stopper 14a is too low with respect to the conductive particle diameter, it is not sufficient to prevent the conductive particles 16a from being dissipated and is pushed out without being restrained by the stopper 14a. The ratio of the conductive particles 16a increases.

  Conversely, it is not preferable that the height H of the stopper 14a is too high with respect to the conductive particle diameter. If the height H is set higher than necessary, unevenness in the interstitial density of the conductive particles 16a and insufficient crushing of the conductive particles 16a occur due to a step based on the height H. It also leads to poor electrical connection.

  In other words, there is an appropriate range for the effective height H of the stopper 14a that exhibits the stopper function of the conductive particles 16a in order to increase the interstitial density while avoiding poor electrical connection due to steps or the like. Inferred.

  The setting of the height H is presumed to be mainly related to the pressing force at the time of mounting, the conductive particle size (δ), etc. Details have not been confirmed. However, in an experiment, for example, when the pressing force at the time of mounting is assumed to be 50 g / bump, it has been found that the range of δ / 4 ≦ H ≦ δ / 2 is sufficient.

  A method for manufacturing the semiconductor device 10 having the bump electrode 14 provided with the stopper 14a having such a configuration will be described below with reference to the flowchart shown in FIG.

  The semiconductor device 10 included in the LCD driver 10a is manufactured through the steps shown in FIG. In addition, in FIG. 4, each step which comprises a flow, and principal part sectional explanatory drawing (a)-(h) which shows the mode in contrast with each step were shown collectively.

  First, in the first layer Al wiring layer forming step S110, a driving circuit element for a liquid crystal display device is formed on the wafer W by an existing method, and 1 is made of Al along the peripheral edge of the bump electrode 14 formation range. The wiring electrode 11 of the layer is formed in a frame shape. The state of this step is schematically shown in a sectional view in FIG.

  The wiring electrode 11 is provided in a frame shape so as to surround the electrode surface of the bump electrode 14 from the peripheral side to the inside in accordance with the formation range of the bump electrode 14 on which the stopper 14a is to be formed.

  In addition, it is preferable that the stopper 14a is simply formed in a frame-like continuous rising shape because there is no gap through which the conductive particles 16a escape. However, a discontinuous portion may be provided in a range where the blocking function of the conductive particles can be exhibited, that is, a width that does not allow the conductive particles 16a to escape, and the raised shape of the stopper 14a is intermittently formed in a frame shape. It doesn't matter if you do it.

  The wafer W shown in FIG. 4A is not shown in FIGS. 4B to 4H for simplicity.

  In FIG. 4A, the case where Al is used as the wiring electrode 11 is described as an example, but other metals such as Cu may be used as long as the metal can be used as the wiring electrode. Absent.

  In passivation film layer formation step S120, a passivation film 12 is formed on the wiring electrode 11 formed as described above. In the passivation film 12, a step having a height corresponding to the layer thickness of the wiring electrode 11 is formed. Such a step is not a step reflecting the thickness of the passivation film, unlike the case of the bump electrode so far. The state of such steps is shown in FIG.

  Thereafter, in the UBM layer forming step S130, a UMB layer (underlying metal layer) 13 is formed on the passivation film 12 as shown in FIG. The base metal layer 13 can be formed, for example, by sequentially depositing a Cr layer, a Cu layer, and an Au layer by sputtering from the lower layers. In addition, you may use a vapor deposition method for formation of a UBM layer.

  In BUMP photoresist formation step S140, a photoresist is applied to the bump electrode formation range, and then, a predetermined pattern is exposed and developed on the photoresist to provide a bump photoresist 18 for bump electrode formation as shown in FIG. .

  As shown in FIG. 4 (e), the bump electrode 14 is formed by electrolytic plating using the bump photoresist 18 in the BUMP plating step S150. Thereafter, in accordance with the photoresist removal step of step S160, as shown in FIG. 4F, the bump photoresist 18 is removed by etching.

  At the same time, an unnecessary UBM layer, that is, the base metal layer 13 is removed by etching in the UBM layer etching step of step S170, and the bump electrode 14 is annealed in a bump annealing step S180. FIG. 4G shows a state of the bump electrode 14 after the bump annealing.

  In the bump electrode 14 having such a configuration, the electrical connection between the wiring electrode 11 and the bump electrode 14 passes through under the stopper 14a as shown in the cross-sectional view of FIG. 4H viewed from the direction of the arrow in FIG. This is ensured by electrically connecting the base metal layer 13 and the wiring electrode 11 through the holes 15.

  The through-hole 15 is formed in the passivation film layer forming step S120 of FIG. 4B by forming a photoresist on the passivation film 12 after formation, stepper exposure on the photoresist, forming a mask pattern by development, and passivation according to the mask pattern. What is necessary is just to perform by a series of steps, such as a film etching process and the removal of the said photoresist after an etching process.

  After the formation of the through hole 15, as shown in FIG. 4C, if the base metal layer 13 is formed in the UBM layer forming step S130, the wiring electrode 11 and the base metal 13 are formed below the stopper 14a. 15 to be electrically connected.

  In the bump electrode 14 of the LCD driver 10a manufactured in this way, a stopper 14a having a height H corresponding to the layer thickness of the wiring electrode 11 is formed at the peripheral portion of the electrode surface and surrounded by the stopper 14a. The range is formed in the flat portion 14b.

  The height of the stopper 14 a is determined according to the thickness of the wiring electrode 11. Unlike the case of the TCP, the wiring electrode 11 does not have a role of stress relaxation at the time of thermocompression bonding. In contrast, it can be made sufficiently thin as long as conductivity is ensured.

  Since the thickness of the wiring electrode 11 can be sufficiently reduced in this way, the height H of the stopper 14a is set to a value before adopting such a configuration, for example, the passivation film 12 having the configuration shown in FIG. Compared with the height h of the stepped portion 32 of the bump electrode 31 formed corresponding to the film thickness d, it can be remarkably reduced.

  For example, the step height h corresponding to the film thickness d of the passivation film 12 is assumed to be at least 2 μm or more. However, the height H of the stopper 14 a based on the film thickness of the wiring electrode 11 is 0.1 μm to less than 2 μm. Adjustments can be made within the range.

  Incidentally, in the case shown in FIG. 5A, the passivation film 12 on the semiconductor device 10 is provided on the wiring electrode 11 such as Al, and the wiring electrode 11 is exposed by providing an opening in the passivation film 12. The structure so far in which the base metal layer 13 is provided thereon and the bump electrode 31 is further formed by gold plating is shown.

  In the bump electrode 31 formed in this manner, the height h of the stepped portion 32 is too high with respect to the diameter of the conductive particles 16a, so that the pressure is applied at the stepped portion 32 as shown in FIG. Non-uniformity, a decrease in interstitial density, etc. occur and the number of contact portions decreases, so that sufficient electrical conductivity cannot be ensured.

  However, the stopper 14 a formed through each step shown in FIG. 4 has a height H reflecting the layer thickness of the wiring electrode 11, and the anisotropic conductive film 16 using the layer thickness of the wiring electrode 11. It can be set within a range of 1/4 to 1/2 of the particle diameter δ of the conductive particles 16a therein.

  Therefore, the stopper 14a is surrounded by the stopper 14a as shown in FIG. 2 without causing pressure nonuniformity based on the stepped portion 32 as shown in FIG. In a state where the flatness of the inner electrode surface is set to a high level, it is possible to effectively prevent the conductive particles 16a from being dissipated due to pressing during mounting, and the conductivity between the bump electrode 14 and the electrode 17a of the substrate 17 on the mounting side. The interposed density of the particles 16a can be kept high.

  In the configuration of the stopper 14a of the bump electrode 14 shown in FIG. 1, as shown in FIG. 4, the case where the Al wiring electrode 11 is constituted by one layer, that is, a single layer is shown. As shown in the figure, the Al wiring electrode 11 may be formed in a multilayer such as two layers.

  The semiconductor device 10 configured in the LCD driver 10a having two layers of Al wiring electrodes is manufactured through the steps shown in FIG. In addition, in FIG. 6, the principal part cross-sectional explanatory drawing (a)-(j) which shows the mode compared with each step which comprises a flow was shown.

  First, in FIG. 6A, in the same manner as shown in FIG. 4A, in the first Al wiring layer forming step S110, a drive circuit element for a liquid crystal display device is formed by an existing method, and then a bump is formed. A single-layer wiring electrode 11 made of Al is formed in a frame shape along the periphery of the formation range of the electrode 14. In the flowcharts of FIG. 6 and subsequent figures, the illustration of the wafer W is omitted for simplicity.

  After the formation of the wiring electrode 11, as shown in FIG. 6B, an interlayer insulating film 41 is formed in a first layer interlayer insulating film forming step S111. In the interlayer insulating film 41, a step having a height corresponding to the layer thickness of one wiring electrode 11 is formed. The interlayer insulating film 41 is provided with a through hole 42 as shown in FIG. The through hole 42 may be formed in the same manner as the through hole 15 described above.

  In step S112, as shown in FIG. 6C, a second-layer Al wiring electrode 11 is formed on the interlayer insulating film 41 in which the through hole 42 has been formed. The second-layer Al wiring electrode 11 is electrically connected to the first-layer Al wiring electrode 11 through the through hole 42.

  A passivation film 12 is provided on the second-layer Al wiring electrode 11 formed in this way, as shown in FIG.

  After that, steps S120 to S180 shown in FIG. 6 may be performed in the same manner as steps S120 to S180 of the flow shown in FIG.

  FIG. 6I shows a state of the bump electrode after the bump annealing. In the bump electrode 14 having such a configuration, the conduction between the wiring electrode 11 and the bump electrode 14 passes through the stopper 14a as shown in the sectional view of FIG. 6 (j) viewed from the direction of the arrow in FIG. 6 (i). This is ensured by electrically connecting the base metal layer 13 and the wiring electrode 11 through the holes 15.

  The formation of the through hole 15 may be performed as described above, and redundant description is omitted. In the bump electrode 14 of the LCD driver 10a (10) manufactured as described above, the Al wiring electrode 11 is provided in two layers with the interlayer insulating film 41 interposed therebetween, and the wiring electrode is provided on the peripheral portion of the electrode surface. A stopper 14a having a height H corresponding to the layer thickness 11 is formed, and a range surrounded by the stopper 14a is formed in the flat portion 14b.

  Thus, the bump electrode 14 formed through the steps shown in FIG. 6 has the same effect as the bump electrode 14 having the structure formed through the steps of FIG.

  In the above description, as shown in FIGS. 4 and 6, when the wiring electrode 11 is provided, the unevenness of the surface serving as the base of the wiring electrode 11 was not a particular problem. This is because it is premised that the stopper 14a formed on the base plate 14 does not affect the stopper 14a.

  However, if the underside unevenness is sufficiently large and affects the height H of the stopper 14a, the underlying side unevenness is ignored and only the height H of the stopper 14a is used as the layer thickness of the wiring electrode 11. There is no point in making adjustments. Therefore, a case where the unevenness on the base side cannot be ignored will be described below.

  In response to the recent demand for miniaturization of semiconductor devices, a large number of circuits are provided in a laminated structure in one semiconductor device. In such a situation, as shown in FIG. The base side of the electrode 11 is not flat. For this reason, even if the uneven base is left as it is, the wiring electrode 11 is provided thereon, and the bump electrode 14 is further formed thereon, the electrode surface is in an uneven state reflecting the underlying unevenness, As shown in FIG. 7B, there is a case where contact failure occurs.

  Therefore, if the underlying side of the wiring electrode 11 is so uneven that it cannot be ignored, as shown in FIG. 8, the surface of the underlying side is once flattened, and the configuration of the stopper 14a can be considered as described above. . That is, in the process before forming the wiring electrode 11, the surface irregularities based on the multilayer lamination so far may be polished once flat, and then the manufacturing procedure described above may be adopted.

  This procedure is shown in FIG. 8 by taking the LCD driver 10a having the bump electrode 14 having the structure shown in FIG. 6 as an example. In FIG. 8, as in FIG. 6, the steps constituting the flow and the cross-sectional explanatory diagrams (a), (b), (a) to (i) showing the state of the corresponding steps are combined. Showed.

  In FIG. 8A, first, before the wiring electrode 11 is formed, the surface of the insulating layer 51 corresponding to the concave and convex base side of the wiring electrode 11 that has been laminated in layers is flattened. By the chemical treatment step, the surface is flattened by CMP (Chemical Mechanical Polishing) treatment. FIG. 8A shows the state of the uneven base before flattening.

  The surface of the insulating layer 51 is uneven due to, for example, the gate electrode 52 or the like that has been stacked. 8A also shows a gate electrode 52, a source / drain semiconductor region (also referred to as a diffusion layer) 54 provided in the interlayer insulating film 53, and a gate insulating film 55. FIG.

  In this way, the surface of the insulating layer 51 having an uneven surface is flattened reflecting the unevenness of the gate electrode 52 and the like provided below. The flattened state is shown in FIG. The planarization is performed using a CMP apparatus. Of course, a method other than the CMP process may be employed for the planarization process as long as it can be used effectively.

  After planarizing the surface in this way, as shown in FIG. 8A, the process proceeds to the first Al wiring layer forming step of Step S110, and the wiring electrode 11 is formed on the surface of the insulating layer 51. . The subsequent steps S111 to S180 are the same as steps S111 to S180 in FIG. FIGS. 8A to 8I also correspond to FIGS. 6A to 6I.

  In this way, when the unevenness on the ground side of the wiring electrode 11 cannot be ignored, the bump electrode 14 is provided so as to form the stopper 14a after flattening once by CMP processing or the like. Good. By providing the flattening process on the uneven base side in this way, the bump electrode 14 in which the stopper 14a is formed so as to surround the flat portion 14b having a high surface flatness from the periphery can be effectively formed.

(Embodiment 2)
In the first embodiment, the case where the height of the stopper 14a is set based on the layer thickness of the first Al wiring electrode 11 has been described, but in this embodiment, as shown in FIGS. The configuration of the stopper 14a whose height is set based on the second-layer Al wiring electrode 11 will be described.

  9 and 10, it is assumed that the unevenness of the base of the wiring electrode 11 cannot be ignored as shown in FIG.

  First, in the case shown in FIG. 9, the wiring electrode 11 is formed by dividing into an Al wiring electrode 11a (11) for ensuring conduction and an Al wiring electrode 11b (11) for setting the height of the stopper 14a. The case where it does is demonstrated. Also in this embodiment, as shown in FIG. 9 (a), the unevenness on the base side of the wiring electrode 11 cannot be ignored as shown in FIG. 8 (a).

  Therefore, first, the planarization process is performed as shown in FIG. 9B according to the planarization process step S100 of the insulating layer. As the planarization process, for example, a CMP process or the like may be applied as described in FIG.

  A first-layer Al wiring electrode 11a (11) is provided on the insulating layer 51 after the planarization by the first-layer Al wiring layer forming step S110. The wiring electrode 11a is provided at a position outside the formation range of the bump electrode 14 as shown in FIG.

  An interlayer insulating film 41 is provided on the wiring electrode 11a as shown in FIG. 9B by the first interlayer insulating film forming step S111. In the interlayer insulating film 41, a through hole 42 communicating with the wiring electrode 11a is formed.

  In this state, according to the second-layer Al wiring layer forming step S112, as shown in FIG. 9C, an Al wiring electrode 11b (11) is formed. The wiring electrode 11b is provided in a frame shape on the periphery corresponding to the formation range of the bump electrode 14, and the second-layer Al wiring electrode is also provided in a portion that is electrically connected to the first-layer wiring electrode 11a through the through hole 42. 11c (11) is provided.

  After providing the second-layer Al wiring electrodes 11b and 11c in this way, the passivation film 12 is provided in the passivation film layer forming step S120. In the passivation film 12, an opening corresponding to the second-layer wiring electrode 11c is opened as shown in FIG.

  In this state, according to the UBM layer formation step S130, the base metal layer 13 is provided as shown in FIG. On the underlying metal layer 13, as shown in BUMP photoresist formation step S140, FIG. 9F, a bump photoresist 18 is provided so as to cover the second-layer wiring electrodes 11b and 11c.

  By using the bump photoresist 18 as a mask, the bump electrode 14 is formed by Au plating as shown in FIG.

  Thereafter, through the photoresist removal step S160, the UBM layer etching step S170, and the bump annealing step S180, the semiconductor device 10 configured in the LCD driver 10a is manufactured.

  In the manufactured semiconductor device 10, a stopper 14a having a height set based on the layer thickness of the second wiring electrode 11b is formed. A stepped portion is also generated on the side based on the second-layer wiring electrode 11c, but this stepped portion is supposed to be a side responsible for electrical connection of wiring electrode 11a-wiring electrode 11c-underlying metal layer 13-bump electrode 14. ing.

  The height of the stopper 14a is set based on the layer thickness of the wiring electrode 11b provided for defining the stopper height. The stopper 14a is formed in a frame shape on the periphery of the electrode surface of the bump electrode 14, and the inner side surrounded by the stopper 14a is formed in the flat portion 14b. By appropriately changing the layer thickness of the second-layer wiring electrode 11b, the height of the stopper 14a can be adjusted.

  Note that FIG. 9J is a cross-sectional view of the main part showing a state seen from the direction of the arrow, in which the direction shown in FIG.

  In the configuration shown in FIG. 9, the second-layer Al wiring electrode 11 includes a wiring electrode 11 b responsible for setting the stopper height 14 a, and a wiring exclusively responsible for ensuring conductivity between the bump electrode 14 and the wiring electrode 11. Although the case where the electrode 11c is configured separately has been described, as shown in FIG.

  FIGS. 10A and 10B are the same as FIGS. 9A and 9B, and the description thereof is omitted. After the uneven base of FIG. 10A is flattened as shown in FIG. 10B by the flattening step S100 of the insulating layer, the insulating layer is formed as shown in the first Al wiring layer forming step S110. A wiring electrode 11 a (11) is provided along the formation range of the bump electrode 14 on 51.

  As shown in FIG. 10A, the first-layer wiring electrode 11a is provided uniformly in accordance with the formation range of the bump electrode 14, unlike the case shown in FIG. 9A. An interlayer insulating film 41 is provided on the first-layer wiring electrode 11a having the above-described configuration so as to open the formation area of the bump electrode 14 in the first-layer interlayer insulating film forming step S111.

  Thereafter, a second-layer wiring electrode 11b (11) is provided on the wiring electrode 11a in the second-layer Al wiring layer forming step S112. As shown in FIG. 10C, that is, as shown in FIG. 9C, the second-layer wiring electrode 11b is provided in a frame shape around the periphery of the bump electrode 14 formation range. In this way, the second-layer Al wiring electrode 11b is directly provided on the first-layer Al wiring electrode 11a.

  In this state, the passivation film 12 is provided by the passivation film layer forming step S120. As shown in FIG. 10D, the passivation film 12 is provided so as to cover the interlayer insulating film 41, and the passivation film 12 is not applied to the second-layer wiring electrode 11b.

  In this state, the base metal layer 13 is formed in the UBM layer forming step S130. After step S130, processing up to step S180, that is, from FIG. 10 (e) to (i), may be performed corresponding to steps S130 to S180 and FIG. 9 (e) to (i) in FIG. The duplicate description is omitted.

  10 and 9 is the same in that the wiring electrode 11b in the second layer defines the height of the stopper 14a, but in the case of FIG. 9, the wiring electrode 11a defines the height of the stopper 14a. However, in the case shown in FIG. 10, the difference is that it is used for both height regulation and conduction.

  Therefore, in the configuration shown in FIG. 10, since the wiring electrode 11a that regulates the height of the stopper 14a is also used for ensuring conduction, it is necessary to provide the configuration of the wiring electrode 11c shown in FIG. 9 in addition to the wiring electrode 11b. There is no simpler configuration.

  Even in such a configuration, by appropriately changing the layer thickness of the second wiring electrode 11b, the height of the stopper 14a can be adjusted in accordance with the diameter of the conductive particles of the anisotropic conductive film used during mounting. The same effect as described in the first embodiment can be obtained.

(Embodiment 3)
In the present embodiment, the configuration of the stopper 14a whose height is defined based on the thicknesses of both the interlayer insulating film 41 and the passivation film 12 will be described with reference to FIG.

  Also in the case shown in FIG. 11 (a), it is assumed that the unevenness on the base side of the wiring electrode 11 is not negligible as shown in FIG. 8 (a).

  First, according to the flattening process step S100 of the insulating layer, the flattening process is performed as shown in FIG. As the planarization process, for example, a CMP process is applied as described in FIG.

  On the insulating layer 51 that has been subjected to the planarization process, the first Al wiring layer forming step S110 uniformly forms the wiring electrode 11a (in accordance with the formation range of the bump electrode 14 as shown in FIG. 11A). 11) is provided.

  As shown in FIG. 11B, an interlayer insulating film 41 is provided on the first wiring electrode 11a by the first interlayer insulating film forming step S111. The interlayer insulating film 41 is formed on the periphery of the wiring electrode 11 a so as to have a frame shape, and the center of the wiring electrode 11 a is widely opened in accordance with the formation range of the bump electrode 14. The layer thickness of the interlayer insulating film 41 can be used to adjust the height of the stopper 14a, and the height of the stopper 14a can be adjusted by changing the layer thickness.

  In this state, the wiring electrode 11b (11) is formed by the second-layer Al wiring layer forming step S112 as shown in FIG. The wiring electrode 11b is directly laminated with the first wiring electrode 11a except for the peripheral portion.

  As shown in FIG. 11D, the passivation film 12 is provided on the second-layer wiring electrode 11b thus formed so as to cover only the interlayer insulating film 41 as shown in FIG. 11D. . As shown in FIG. 11D, the passivation film 12 does not cover the wiring electrode 11b not covered with the interlayer insulating film 41.

  The height of the stopper 14 a can be adjusted by changing the layer thickness of the passivation film 12 formed in this way as with the interlayer insulating film 41.

  In the state where the interlayer insulating film 41 and the passivation film 12 contributing to the height adjustment of the stopper 14a are laminated in this way, the base metal layer 13 is passivated as shown in FIG. 11E by the UBM layer forming step S130. Provided on the film 12. The base metal layer 13 is directly laminated with the second wiring electrode 11b directly laminated on the first wiring electrode 11a in a range surrounded by the side where the interlayer insulating film 41 and the passivation film 12 are laminated. It will be.

  In this state, the bump photoresist 18 is formed on the base metal layer 13 in the BUMP photoresist forming step S140. Step S140 and subsequent steps up to step S180, that is, steps from (f) to (i) in FIG. 11 may correspond to steps S140 to S180 and FIGS. 8 (f) to (i) in FIG. Is omitted.

  As shown in FIG. 11 (i), the bump electrode 14 thus formed has an interlayer insulating film 41 and a passivation film 12 interposed as a laminated structure below the stopper 14a. 41. By adjusting the thickness of each of the passivation films 12, the height of the stopper 14a can be adjusted.

  In particular, the configuration described in the embodiment is effective in the case where conductive particles having a diameter larger than the current one are used in the future by relating the passivation film 12 to the height adjustment of the stopper 14a. It is the structure which can be applied to.

  Even in such a configuration, by adjusting the layer thickness of each or either of the interlayer insulating film 41 and the passivation film 12, the height of the stopper 14a can be adjusted according to the diameter of the conductive particles of the anisotropic conductive film used during mounting. Therefore, the same effects as described in the first embodiment can be obtained.

(Embodiment 4)
In the present embodiment, the configuration of the stopper 14a whose height is set based on the layer thicknesses of both the wiring electrode 11 and the passivation film 12 will be described.

  Also in the case shown in FIG. 12A, it is assumed that the unevenness on the base side of the wiring electrode 11 is not negligible as shown in FIG.

  First, according to the flattening process step S100 of the insulating layer, the flattening process is performed as shown in FIG. As the planarization process, for example, a CMP process is applied as described in FIG.

  As shown in FIG. 12A, the wiring electrode 11a (11) is formed on the insulating layer 51 subjected to the planarization process in accordance with the formation range of the bump electrode 14, as shown in FIG. Provide. The wiring electrode 11a is provided in a frame shape around the periphery of the bump electrode 14 formation range. With this arrangement, the layer thickness of the first wiring electrode 11a contributes to the height setting of the stopper 14a.

  In this state, the interlayer insulating film 41 is uniformly provided on the wiring electrode 11a as shown in FIG. 12B by the first interlayer insulating film forming step S111. However, the through hole 42 is formed on the wiring electrode 11a.

  On the interlayer insulating film 41 formed in this way, a second-layer wiring electrode 11b (11) is provided as shown in FIG. 12C by the second-layer Al wiring layer forming step S112. The first-layer wiring electrode 11 a and the second-layer wiring electrode 11 b are electrically connected through the through hole 42.

  As shown in FIG. 12D, the passivation film 12 is provided on the side corresponding to the first-layer wiring electrode 11a on the second-layer wiring electrode 11b by the passivation film layer forming step S120. In this way, the passivation film 12 is not provided uniformly on the wiring electrode 11b, but is provided in part corresponding to the wiring electrode 11a side, thereby contributing to the height adjustment of the stopper 14a.

  In this state, the base metal layer 13 is formed in the UBM layer forming step S130. Steps S130 to S180, that is, FIGS. 12 (e) to (i) correspond to steps S130 to S180 and FIGS. 8 (e) to (i) in FIG.

  As shown in FIG. 12 (i), the bump electrode 14 thus formed has a wiring electrode 11a and a passivation film 12 interposed as a laminated structure below the stopper 14a. By adjusting the thickness of each of the passivation films 12, the height of the stopper 14a can be adjusted.

  In particular, the configuration described in the embodiment is effective in the case where conductive particles having a diameter larger than the current one are used in the future by relating the passivation film 12 to the height adjustment of the stopper 14a. It can be said that it can be applied to the configuration.

  Even in such a configuration, the height of the stopper 14a can be adjusted according to the diameter of the conductive particles of the anisotropic conductive film used at the time of mounting by adjusting the layer thickness of each or either of the wiring electrode 11a and the passivation film 12. Adjustment can be performed, and the same effect as described in the first embodiment can be obtained.

  As described above, by using the method described in the first to fourth embodiments, that is, the vertical wiring electrode layer, the interlayer insulating film, the passivation film, and the like corresponding to the peripheral edge of the bump electrode 14 By changing the laminated pattern in the direction, the profile of the surface of the bump electrode 14 can be arbitrarily adjusted in the range of 0.1 to 2 μm.

  Up to now, the design of MOS semiconductors has focused on circuit design, and no sufficient method has been proposed for a design method that can arbitrarily change the vertical structure with respect to the profile on the electrode surface as in the present invention. The present invention can be said to be a very significant technique.

  In the first to fourth embodiments, the case where the stopper height is defined by the wiring electrode layer thickness, the interlayer insulating film thickness and the passivation film thickness, or the wiring electrode layer thickness and the passivation film film is described as an example. However, the stopper height can be defined by the wiring electrode layer thickness and the interlayer insulating film thickness in the same manner.

(Embodiment 5)
Next, a connection configuration when the LCD driver 10a for controlling the voltage switching of the liquid crystal display device having the bump electrode 14 having the configuration described in the first to fourth embodiments is incorporated in an LCD (Liquid Crystal Display). This will be described below.

  FIG. 13 shows an arrangement state of the bump electrodes 14 of the LCD driver 10a (10) formed in an elongated rectangular shape for performing voltage switching control between the gate line group and the drain line group provided in the direction intersecting each other of the liquid crystal display mechanism. An example is shown in a plan view.

  As shown in FIG. 13, the LCD driver 10a has a bump electrode 14 corresponding to a large number of lines constituting a gate line group and a drain line group corresponding to the number of pixels of the liquid crystal display screen. Many are provided along the periphery of the long side and the short side.

  Various types of LCDs have been developed. Hereinafter, a typical TFT liquid crystal display will be described as an example. In a TFT (Thin Film Transistor) display, as shown in FIGS. 14A and 14B, two glass substrates 61a and 61b each provided with an alignment film (not shown) on the inside are made to face each other. In this state, the liquid crystal panel 60 is configured with the STN liquid crystal 62 interposed therebetween.

  One glass substrate 61b of the liquid crystal panel 60 is provided with a plurality of X electrode lines and a plurality of Y electrode lines that cross each other along the plate surface direction of the glass substrate 61b, and one X electrode line is a gate line (data signal). The other Y electrode line is formed as a drain line (also referred to as an address line), and the other glass substrate 61a is formed as a common electrode.

  Pixels whose addresses are designated are set corresponding to the intersection positions of the plurality of X electrode lines and Y electrode lines, and TFT active elements are provided corresponding to the individual pixels. Therefore, in a monochrome display, the number of pixels is a product of the number of X electrodes and the number of Y electrodes. On the other hand, in the color display, each pixel is further divided into sub-pixels for displaying the three primary colors of red, blue, and yellow, and the number of X electrodes is also tripled, so the number of pixels is three times that of a monochrome display. It becomes.

  In this way, in the matrix display system in which pixels are determined at the intersection between the X electrode line group and the Y electrode line group, the image data sent from the X electrode line to the address specified by the Y electrode line is converted to the TFT active element. And video data is written to each pixel. Video data captured by the TFT active element is stored as charge / discharge charges in a storage capacitor provided in each pixel, and video display is performed using the charges.

  In the liquid crystal panel 60 having such a configuration, as shown in FIG. 14A, the glass substrate 61b is formed larger than the glass substrate 61a, and the above-mentioned necessary for matrix display along the two peripheral edges of the glass substrate 61a. In accordance with the number of X electrode line groups and Y electrode line groups, the LCD driver 10a for the X electrode lines, that is, the gate lines, and the LCD driver 10b for the Y electrode lines, that is, the drain lines, respectively, are required. It is provided in an implementation format.

  As shown in FIG. 14B, STN liquid crystal 62 sealed by a seal portion 63 is sealed between glass substrates 61a and 61b. From the liquid crystal display side, the input-side substrate wiring 64 is extended to form an external terminal. One of the external terminal and the bump electrode 14 of the LCD driver 10a is a flip-chip method, and the anisotropic conductive film 16 is interposed. Implemented.

  As shown in FIG. 14B, the other bump electrode 14 of the LCD driver 10a is mounted on the output side substrate wiring 65 by the flip chip method via the anisotropic conductive film 16, and the output side substrate wiring 65 is connected to the output side substrate wiring 65. An anisotropic conductive film 16 is interposed and connected to an external circuit 66 such as a printed circuit board. Such a configuration is the same in the LCD driver 10b.

  Video data is sent from the external circuit 66 through the output side substrate wiring 65 to the predetermined address through the LCD driver 10a and the input side substrate wiring 64 through the X electrode line. Similarly, addressing such as pixel writing by the Y electrode line is performed by the LCD driver 10b. In this way, the LCD driver 10a, 10b performs voltage control on the pixel at the required address via the X electrode line.

  In FIG. 15, a peripheral circuit necessary for a liquid crystal panel is provided on a flexible material such as a film, and an LCD driver 10 a having a bump electrode 14 that improves the flatness of the electrode surface of the above configuration is face-down mounted on the film. Shows the configuration.

  On the film 67, peripheral circuits are printed, and wiring electrodes 68 and 69 leading to the peripheral circuit are respectively provided with transparent input side substrate wiring 64 on the glass substrate 61b and the LCD driver 10a through the anisotropic conductive film 16. The bump electrode 14 is connected. As described above, the present invention can be effectively applied to the COF mounting system in the field of LCDs.

  Also in such COF mounting, as described above, the reliability of the LCD module is improved by increasing the contact area with the conductive particles by flattening the bump electrodes 14.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above description, the LCD driver has been described as an example. However, the present invention is not limited to the LCD driver, and the bump electrode is mounted on the other side such as the mounting substrate side electrode by face-down mounting with an anisotropic conductive film interposed. You may apply to the semiconductor device of the structure electrically connected with an electrode. That is, it can be applied to a bump electrode specification product having a contact portion.

  The present invention can be effectively used in the field of semiconductor devices and manufacturing techniques thereof.

(A) is principal part sectional drawing which shows typically the structure of the bump electrode in the semiconductor device of one embodiment of this invention, (b) is a structure when it sees from the arrow direction of (a). FIG. FIG. 3 is an explanatory cross-sectional view schematically showing a mounting state of the semiconductor device having the configuration shown in FIG. (A) is sectional explanatory drawing which shows typically the mode of the bump electrode which has shoulder drooping, (b) is sectional explanatory drawing which shows typically the mounting condition using the bump electrode of the structure shown to (a). is there. (A)-(h) is sectional explanatory drawing which shows a series of steps which show the manufacturing method of the semiconductor device of one embodiment of this invention. (A) is sectional explanatory drawing which showed typically the bump electrode of the structure which does not provide the stopper of this invention, (b) shows the condition where the bump electrode of the structure shown to (a) was mounted. FIG. (A)-(j) is sectional explanatory drawing which shows a series of steps which show the manufacturing method of the semiconductor device of one embodiment of this invention. (A) is sectional explanatory drawing which shows typically the uneven | corrugated condition of the bump electrode surface in case the unevenness | corrugation of a wiring electrode formation base cannot be disregarded, (b) is the condition which mounted the bump electrode of the structure of (a). It is a section explanatory view showing typically. (A), (b), (a)-(i) is sectional explanatory drawing which shows a series of steps which show the manufacturing method of the semiconductor device of one embodiment of this invention. (A), (b), (a) to (j) are cross-sectional explanatory views showing a series of steps showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. (A), (b), (a)-(i) is sectional explanatory drawing which shows a series of steps which show the manufacturing method of the semiconductor device of one embodiment of this invention. (A), (b), (a)-(i) is sectional explanatory drawing which shows a series of steps which show the manufacturing method of the semiconductor device of one embodiment of this invention. (A), (b), (a)-(i) is sectional explanatory drawing which shows a series of steps which show the manufacturing method of the semiconductor device of one embodiment of this invention. It is a top view which shows the arrangement | positioning condition of the bump electrode in the semiconductor device comprised in the LCD driver. (A) It is a top view which shows typically a liquid crystal panel, (b) is principal part sectional drawing which shows typically the connection condition of the LCD driver in (a). It is principal part sectional drawing which shows typically a mode that the LCD driver was mounted by the COF mounting system in the liquid crystal display.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 10a LCD driver 10b LCD driver 11 Wiring electrode 12 Passivation film 13 Base metal layer 14 Bump electrode 14a Stopper 14b Flat part 15 Through hole 16 Anisotropic conductive film 16a Conductive particle 17 Substrate 17a Electrode 18 Bump photoresist 21 Bump electrode 21a Shoulder 21b Flat portion 31 Bump electrode 32 Step portion 41 Interlayer insulating film 42 Through hole 51 Insulating layer 52 Gate electrode 53 Interlayer insulating film 54 Semiconductor region (diffusion layer)
55 Gate insulating film 60 Liquid crystal panel 61a Glass substrate 61b Glass substrate 62 STN liquid crystal 63 Sealing part 64 Input side substrate wiring 65 Output side substrate wiring 66 External circuit 67 Film 68 Wiring electrode 69 Wiring electrode D Width d Film thickness δ Conductive particle diameter H Height h Height W Wafer

Claims (3)

A semiconductor device having a bump electrode for electrical connection to an electrode of a mounting substrate through conductive particles in an anisotropic conductive film,
A semiconductor chip on which circuit elements are formed;
A wiring electrode formed on the main surface of the semiconductor chip and electrically connected to the circuit element;
A wiring pattern formed on the main surface of the semiconductor chip and disposed in the vicinity of the first wiring electrode, wherein the wiring pattern is formed in the same layer as the wiring electrode;
An insulating film formed on the main surface of the semiconductor chip so as to cover the wiring electrode and the wiring pattern, and having an opening above the wiring electrode;
A bump electrode base metal layer formed on the insulating film and electrically connected to the wiring electrode through the opening of the insulating film;
A bump electrode formed on the bump electrode base metal layer, having the same pattern in plan as the bump electrode base metal layer, and formed of a metal layer thicker than the bump electrode base metal layer; ,
Each of the bump electrode base metal layer and the bump electrode is formed so as to be drawn from the wiring electrode so as to overlap the wiring pattern in a planar manner. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the wiring pattern is formed to define a surface shape of the bump electrode. The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein the wiring pattern is formed in a frame shape in plan.

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