JP2008041277A - Display panel using light-emitting element, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable to form a display panel using a light-emitting element in a superior yield in which even if a pin hole is opened in a transparent anode electrode at a contact part between a wiring layer made of aluminum based metal and the transparent anode electrode at a wiring terminal part. <P>SOLUTION: In the wiring terminal part of a top emission type organic EL display panel in which an organic EL element is used as the light-emitting element, a reflecting layer 50 is formed on a drain wiring layer 42 in a shape of completely covering a region in which this drain wiring layer 42 is exposed, and furthermore, by forming the transparent anode electrode 20a in a shape of completely covering the reflecting layer 50, even if the pin hole is opened in the transparent anode electrode 20a, since combination of the transparent anode electrode 20a and the reflecting layer 50 enables to form a wiring terminal part in the superior yield since a battery reaction in a resist stripping liquid does not proceed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display panel using a light emitting element and a manufacturing method thereof, and more particularly to a display panel using an organic electroluminescence element as a light emitting element and a manufacturing method of such a display panel.

Conventionally, a current-controlled light-emitting element that emits light at a luminance corresponding to the current value of a supplied current, such as an organic electroluminescence element (hereinafter abbreviated as “organic EL element”) or a light-emitting diode (LED). 2. Description of the Related Art A self-luminous display (display device) including a display panel in which display pixels including two-dimensionally are arranged is known.

An organic EL element that is a light emitting element has a laminated structure in which an anode, an EL layer, and a cathode are laminated in this order on a substrate. When a voltage is applied between the anode and the cathode, holes and electrons are generated in the EL layer. Implanted and electroluminescent in the EL layer. An EL element designed so that light emitted from the EL layer is transmitted through a substrate on which an organic EL element is provided is referred to as a bottom emission type. An EL element designed to emit light is called a top emission type.

  Organic EL display panels using organic EL elements can be broadly classified into a passive drive type and an active matrix drive type. The active matrix driving type organic EL display panel is superior to the passive driving type in terms of high contrast and high definition.

  In an active matrix driving type organic EL display panel, one or a plurality of thin film transistors are provided for each pixel, and the organic EL elements are caused to emit light by the thin film transistors. For example, in the display panel described in Patent Document 1, a voltage signal corresponding to image data is applied to the gate to cause a current to flow through the organic EL element, and a voltage signal corresponding to the image data is applied to the gate of the drive transistor. Two thin film transistors are provided for each pixel, including a switching transistor that performs switching to supply the voltage. In manufacturing an active matrix drive type display, a transistor array substrate in which thin film transistors are patterned for each pixel is manufactured, and then an organic EL element is patterned on the surface of the transistor array substrate for each pixel. The reason why the organic EL element is patterned after the thin film transistor is that the temperature at which the thin film transistor is patterned exceeds the heat resistance temperature of the organic EL element.

  Since the thin film transistor is patterned for each pixel, when a plurality of organic EL elements are patterned in a matrix, the lower layer side anode electrode (pixel electrode) connected to the thin film transistor is patterned for each pixel independently. On the other hand, the cathode electrode (counter electrode) is formed on the entire surface as a common electrode for all organic EL elements.

As a method of patterning a plurality of organic EL elements in a matrix, a low molecular EL layer is formed by vapor deposition through a mask having a desired pattern, or a polymer organic EL layer is formed by using an organic solvent or the like. There is a method in which it is dissolved in and coated with an ink jet printer or a nozzle coater.
JP-A-8-330600

  In an organic EL display panel having a top emission structure, when an aluminum-based metal is used as a drain electrode (wiring) material and tin-doped indium oxide (hereinafter abbreviated as ITO) is used as a transparent anode electrode material, the drain electrode (wiring) After forming, there is a step of forming an ITO electrode.

  In this case, since the ITO electrode has a very thin film thickness of 500 mm or less, pinholes are likely to occur. When such a pinhole is opened in the ITO electrode on the electrode using an aluminum-based metal, the battery reaction shown below occurs in the etching process when patterning the ITO electrode. Here, the battery reaction generally means that when different metals are in contact with each other and each metal is in contact with the same electrolyte solution, the metal reaction on one side becomes the anode, and the other becomes the cathode and the chemical reaction occurs. It is a phenomenon that occurs. That is, a reduction reaction occurs at the anode and an oxidation reaction occurs at the cathode.

  In FIG. 43, an ITO electrode 3 is laminated on an aluminum-based electrode 2 formed on an insulating base layer 1, and the ITO electrode 3 is in contact with the resist stripping solution 5 with a pinhole 4 open. Shows the case. Reference numeral 6 is an insulating film.

  In such a case, as shown in FIG. 44A, the resist stripping solution 5 acts as an electrolytic solution at the pinhole 4 portion, the ITO electrode 3 is reduced, and the aluminum-based electrode 2 is oxidized. Therefore, the etching of the aluminum-based electrode 2 proceeds, and disconnection may occur as shown in FIG.

  In the organic EL display panel, such a contact structure between the drain electrode and the transparent anode electrode is used to connect a gate or drain wiring layer to a COF (Chip on Film) or COG (Chip on Grass). Or in the drain wiring terminal portion. That is, in these terminal portions, there are exposed portions of the aluminum-based alloy wiring layer, and a severe battery reaction occurs during etching of the ITO electrode. Therefore, the exposed portions of the wiring layers in the gate wiring terminal portion and the drain wiring terminal portion are Although it is necessary to completely cover with the ITO electrode, if the ITO electrode has a pinhole, the battery reaction as described above occurs and the yield is remarkably lowered.

  The present invention has been made in view of the above points, and at the contact portion between the aluminum-based metal wiring layer and the transparent anode electrode in the wiring terminal portion, it is formed with high yield even if pinholes are opened in the transparent anode electrode. An object of the present invention is to provide a display panel using a light emitting element and a method for manufacturing the same.

  One aspect of a display panel using the light-emitting element of the present invention is a display panel in which light-emitting elements having a laminated structure of transparent pixel electrodes, a light-emitting layer, and a transparent counter electrode are arranged in a matrix, and a substrate, A plurality of transistors for driving the light emitting elements provided for each of the light emitting elements on the substrate; a wiring layer for supplying a signal or a power supply voltage to the plurality of transistors on the substrate; An insulating film formed so as to cover the plurality of transistors and the wiring layer, and a pixel electrode of the light emitting element is formed on the insulating film corresponding to the arrangement of the light emitting elements. An electrically conductive reflective layer; and a wiring terminal portion in which an opening is formed in the insulating film until reaching the wiring layer for connecting the wiring layer to the outside. In the child portion, the laminated structure of the pixel electrode and the reflective layer extends to the inside of the opening formed in the insulating film, and is connected to the outside through the laminated structure of the pixel electrode and the reflective layer. It is characterized in that conduction is made.

  Another embodiment of the display panel using the light emitting device of the present invention is a display panel in which light emitting devices having a laminated structure of transparent pixel electrodes, a light emitting layer, and a transparent counter electrode are arranged in a matrix, A substrate, a plurality of transistors for driving the light emitting elements provided on the substrate, and a wiring for supplying a signal or a power supply voltage to the plurality of transistors on the substrate; A layer, an insulating film formed so as to cover the plurality of transistors and the wiring layer, and a pixel electrode of the light emitting element formed on the insulating film corresponding to the arrangement of the light emitting elements. A conductive reflection layer to be formed; a wiring terminal portion in which an opening is formed in the insulating film until reaching the wiring layer for connecting the wiring layer to the outside; and the wiring end A conductive auxiliary layer formed so as to cover the entire surface of the wiring layer exposed in the opening formed in the insulating film of the portion, and in the wiring terminal portion, the pixel electrode And a laminated structure of the reflective layer is formed to extend over the auxiliary layer in the opening formed in the insulating film, and is electrically connected to the outside through the laminated structure of the pixel electrode and the reflective layer. It is characterized by.

  One embodiment of a method for producing a display panel using the light emitting device of the present invention is a method for producing a display panel in which light emitting devices having a laminated structure of a transparent pixel electrode, a light emitting layer, and a transparent counter electrode are arranged in a matrix. A step of forming a plurality of transistors for driving the light emitting element on the substrate, and a step of forming a wiring layer for supplying a signal or a power supply voltage to the plurality of transistors on the substrate; A step of forming an insulating film covering the plurality of transistors and the wiring layer, and a wiring terminal portion for connecting the wiring layer to the outside in the insulating film, wherein an opening to reach the wiring layer is formed Forming a conductive reflective layer on the insulating film corresponding to the arrangement of the light emitting elements, and forming a pixel electrode of the light emitting element on the reflective film. A step of forming a light emitting layer of the light emitting element on the pixel electrode of the light emitting element, and a step of forming a counter electrode of the light emitting element on the light emitting layer of the light emitting element, In the wiring terminal portion, the step of forming the reflective layer and the step of forming the pixel electrode are such that the laminated structure of the reflective layer and the pixel electrode extends into the opening formed in the insulating film. The reflective layer and the pixel electrode are formed so as to be electrically connected to the outside through a laminated structure of the pixel electrode and the reflective layer.

  Another aspect of the method for manufacturing a display panel using the light emitting element of the present invention is a display panel in which light emitting elements having a laminated structure of a transparent pixel electrode, a light emitting layer, and a transparent counter electrode are arranged in a matrix. In the manufacturing method, a step of forming a plurality of transistors for driving the light emitting element on a substrate, and a wiring layer for supplying a signal or a power supply voltage to the plurality of transistors on the substrate are formed. And a step of forming an insulating film covering the plurality of transistors and the wiring layer, and a wiring terminal portion for connecting the wiring layer to the outside on the insulating film until reaching the wiring layer Forming an opening, and forming a conductive auxiliary layer so as to cover the entire surface of the wiring layer exposed inside the opening formed in the insulating film of the wiring terminal portion. Corresponding to the arrangement of the light emitting elements, forming a conductive reflective layer on the insulating film, forming a pixel electrode of the light emitting element on the reflective film, Forming the light emitting layer of the light emitting element on the pixel electrode of the light emitting element, and forming the counter electrode of the light emitting element on the light emitting layer of the light emitting element, and forming the reflective layer And the step of forming the pixel electrode includes a step in which the laminated structure of the reflective layer and the pixel electrode extends to the auxiliary layer in the opening formed in the insulating film in the wiring terminal portion. The reflective layer and the pixel electrode are formed so as to be electrically connected to the outside through a laminated structure of the electrode and the reflective layer.

  According to the present invention, a conductive reflective layer for top emission is provided between the wiring layer made of an aluminum-based metal in the wiring terminal portion and the transparent anode electrode as the pixel electrode instead of directly contacting them. Therefore, even if a pinhole is opened in the transparent anode electrode, a battery reaction does not occur, and a display panel using a light emitting element that can be formed with a high yield and a manufacturing method thereof can be provided.

  According to the present invention, the anode auxiliary layer, which is a conductive auxiliary layer formed on the wiring layer made of an aluminum-based metal in the wiring terminal portion, and the transparent anode electrode, which is a pixel electrode, are not in direct contact with each other. In addition, a conductive reflective layer for top emission is provided between the anode auxiliary layer and the transparent anode electrode, so that even if pinholes are opened in the transparent anode electrode, a cell reaction does not occur and it is formed with high yield. It is possible to provide a display panel using a light emitting element and a manufacturing method thereof.

  The best mode for carrying out the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

[First Embodiment]
FIG. 1 is a schematic view of an active matrix driving type organic EL display panel 10 according to a first embodiment of a display panel using a light emitting element of the present invention, and FIG. 2 is a plan view of the organic EL display panel 10. It is. The present embodiment is a top emission type display panel using an organic EL element as a light emitting element.

As shown in FIGS. 1 and 2, the organic EL display panel 10 includes a sheet-like or plate-like insulating substrate 12 and n (plural) signals arranged on the insulating substrate 12 so as to be parallel to each other. and line _Y 1 to Y _n, the scanning lines _X 1 to X of the m arranged on the insulating substrate 12 so as to orthogonal to the signal lines _Y 1 to Y _n in a plan view of the insulating substrate 12 (plural) and _m, and the feed interconnection 14 of the scanning lines _X 1 to X scanning line _X between the respective _m 1 to X _m parallel and staggered with so as m lines arranged on an insulating substrate 12 (plural) signal (M × n) group of pixel circuits P _{1,1 to} P _{m, n} arranged on the insulating substrate 12 so as to form a matrix along the lines Y _{1 to} Y _n and the scanning lines X _{1 to} X _m ; the common wiring 16 provided in a direction parallel to and in plan view the signal lines Y ₁ to Y _n, Provided.

Hereinafter, the extending direction of the signal lines Y _{1 to} Y _n is referred to as a vertical direction (column direction), and the extending direction of the scanning lines X _{1 to} X _m is referred to as a horizontal direction (row direction). Further, m and n are natural numbers of 2 or more, the numbers subscripted to the scanning line X represent the arrangement order from the top in FIGS. 1 and 2, and the numbers subscripted to the signal line Y are FIGS. Represents the arrangement order from the left, the front side of the numbers attached to the pixel circuit P represents the arrangement order from the top, and the rear side represents the arrangement order from the left. That is, when an arbitrary natural number of 1 to m is i and an arbitrary natural number of 1 to n is j, the scanning line X _i is the i-th row from the top, and the signal line Y _j is the left The pixel circuit P _{i, j} is the i-th row from the top and the j-th column from the left, and the pixel circuit P _{i, j} is connected to the scanning line X _i , the power supply wiring 14 and the signal line Y _j . Has been.

Feed line 14, for example, power supply voltage is applied from the left terminal 18L of the insulating substrate 12, the scanning lines _X 1 to X _m, for example scanning voltage from right terminal 18R of the insulating substrate 12 is applied. Further, a signal voltage is applied to the signal lines Y _{1 to} Y _n from, for example, the terminal 18U on the upper side of the insulating substrate 12.

  The total number of common wirings 16 is n + 1, and the common wirings 16 adjacent to each other in the row direction also function as partition walls for partitioning the organic EL layer of the organic EL element 20 which is a light emitting element interposed therebetween. Yes. The common wiring 16 is connected to the routing wiring 22F on one end side and is connected to the routing wiring 22B on the other end side. These lead-out wirings 22F and 22B have the same film thickness as the common wiring 16, and also function as partition walls that partition the organic EL layer in the front-rear direction. The common wiring 16 is connected to the outside by a wiring terminal 24 and is applied with a common potential Vcom.

In this EL display panel 10, each region partitioned in a matrix by scanning lines X _{1 to} X _m and signal lines Y _{1 to} Y _n constitutes a display pixel, and pixel circuits P _{1,1 to} P _{m. , N} are provided in each region.

Since any one of the pixel circuits P _{1,1 to} P _{m, n} is configured in the same manner _, an arbitrary pixel circuit P _{i, j} among the pixel circuits P _1,1 to P _{m, n} will be described. FIG. 3 is an equivalent circuit diagram of the pixel circuit P _{i, j} , and FIGS. 4 and 5 are plan views mainly showing electrodes of the pixel circuit P _{i, j} . In order to make the drawing easy to see _, the transparent anode electrode 20a of the pixel circuit P _{i, j} is not shown in FIG. 4, and the lower layer side electrode of the pixel circuit P _{i, j} is not shown in FIG. .

The pixel circuit P _{i, j} includes an organic EL element 20 as a light emitting element, and three N-channel amorphous silicon thin film transistors (hereinafter simply referred to as transistors) 26 and 28 disposed around the organic EL element 20. 30 and a capacitor 32. Hereinafter, the transistor 26 is referred to as a switch transistor 26, the transistor 28 is referred to as a holding transistor 28, and the transistor 30 is referred to as a drive transistor 30. The capacitor 32 may have an individual capacitor element, or the parasitic capacitance between the gate and source electrodes of the driving transistor 30 may be the capacitor 32.

As shown in FIG. 3, in the pixel circuit P _{i, j} , in the switch transistor 26, the source electrode 26 s is connected to the signal line Y _j , the drain electrode 26 d is the transparent anode electrode 20 a of the organic EL element 20, and the driving transistor. is connected to the electrode 32B of the source electrode 30s and the capacitor 32 of 30, the gate electrode 26g is connected to the gate electrode 28g and the scanning line _{X i} of the holding transistor 28.

In the holding transistor 28, the source electrode 28s is connected to the gate electrode 30g of the driving transistor 30 and the electrode 32A of the capacitor 32, the drain electrode 28d is connected to the drain electrode 30d of the driving transistor 30 and the power supply wiring 14, and the gate electrode 28g. It is connected to a gate electrode 26g and the scanning line X _i of the switch transistor 26.

  In the drive transistor 30, the source electrode 30 s is connected to the transparent anode electrode 20 a of the organic EL element 20, the drain electrode 26 d of the switch transistor 26 and the electrode 32 B of the capacitor 32, and the drain electrode 30 d is connected to the drain electrode 28 d of the holding transistor 28 and Connected to the power supply wiring 14, the gate electrode 30 g is connected to the source electrode 28 s of the holding transistor 28 and the electrode 32 A of the capacitor 32.

  In the organic EL element 20, the transparent anode electrode 20 a is connected to the drain 26 d of the switch transistor 26, the source 30 s of the drive transistor 30 and the electrode 32 B of the capacitor 32, and the transparent cathode electrode 20 c is connected to the common wiring 16.

As shown in FIGS. 1 to 5, when the entire EL display panel 10 is viewed in plan, the scanning lines X _{1 to} X _m and the power supply wirings 14 are alternately arranged and are common to the signal lines Y _{1 to} Y _n. The wirings 16 are arranged alternately.

4 and 5, when attention is paid to an arbitrary pixel circuit P _{i, j} among the pixel circuits P _{1,1 to} P _{m, n} , the signal line Y _j and the common wiring 16 are be between, between the scanning line X _i and the feed interconnection 14 is formed a rectangular region surrounded by these, the transparent anode electrode 20a of the organic EL element 20 is arranged in the rectangular region . Accordingly, when the entire EL display panel 10 is viewed in plan, the plurality of transparent anode electrodes 20a are arranged in a matrix. The transparent anode electrode 20a is provided in a rectangular shape that is long in the vertical direction of the drawing when viewed in plan.

In plan view, the switch transistor 26 and the holding transistor 28 are disposed along the signal line _Yj , and the switch transistor 26 and the holding transistor 28 overlap the edge of the transparent anode electrode 20a. On the other hand, the driving transistor 30 is disposed so as to overlap the common wiring 16 in plan view. Further, in plan view, the capacitor 32 overlaps the transparent anode electrode 20a.

  Next, the layer structure of the EL display panel 10 in this embodiment will be described. 6A is a cross-sectional view taken along line AA of the pixel circuit portion shown in FIGS. 4 and 5, and FIG. 6B is a diagram of the gate wiring terminal portion which is the terminal 18U shown in FIG. FIG. 6C is a cross-sectional view taken along the line B-B, and FIG. 6C is a cross-sectional view taken along the line C-C of the drain wiring terminal portion which is the terminal 18L or the terminal 18R shown in FIG. FIG. 7 is a cross-sectional view taken along line DD of the pixel circuit portion shown in FIGS. 4 and 5.

  As shown in FIG. 6A, the driving transistor 30 includes a gate electrode 30g formed on the insulating substrate 12, a gate insulating film 34 formed on the gate electrode 30g, and a gate sandwiching the gate insulating film 34 therebetween. The semiconductor film 30A facing the electrode 30g, the channel protection film 30B formed on the central portion of the semiconductor film 30A, and the both sides of the semiconductor film 30A are formed so as to be separated from each other and partially overlap the channel protection film 30B. The impurity semiconductor film 30C, the adhesion layer 36 made of chromium or the like formed on the impurity semiconductor film 30C, and the drain electrode 30d and the source electrode 30s formed on the adhesion layer 36 are configured. When viewed in plan, the source electrode 30s of the drive transistor 30 is provided in a U shape, so that the channel width of the drive transistor 30 is widened.

  The other transistors 26 and 28 are not shown in the cross section of FIG. 6A, but have the same structure. In this case, the drains 26d to 30d and the sources 26s to 30s of the transistors 26 to 30 are formed by patterning the same material layer of an aluminum-based metal.

  As shown in FIGS. 6A and 7, the capacitor 32 includes a lower electrode 32A formed on the insulating substrate 12, a gate insulating film 34 formed on the electrode 32A, and a gate insulating film. 34 and an upper electrode 32B opposed to the electrode 32A with the adhesion layer 36 interposed therebetween.

The gate 26g of the switch transistor 26, the gate 28g of the holding transistor 28, the gate 30g of the driving transistor 30, the electrode 32A of the capacitor 32, and the signal lines Y _{1 to} Y _n of the pixel circuits P _{1,1 to} P _{m, n} are formed on an insulating substrate. 12 is formed by patterning the same conductive film formed on the entire surface 12 by a photolithography method and an etching method. In the following description, the gate wiring layer 40 includes the gate 26g of the switch transistor 26, the gate 28g of the holding transistor 28, the gate 30g of the driving transistor 30, the electrode 32A of the capacitor 32, and the conductive film that is the source of the signal lines Y _{1 to} Y _n. Called.

Further, the gate insulating film 34, the pixel circuit _P 1, 1 _{to P m, n} of the switch transistor 26, holding transistor 28, a common film to the driving transistor 30 and capacitor 32 all deposited Betaichimen in the plane Has been. Therefore, the gate insulating film 34 covers the gate 26g of the switch transistor 26, a gate 28g of the holding transistors 28, the electrodes 32A and the signal lines _Y 1 to Y _n of the gate 30g and the capacitor 32 of the drive transistor 30.

The drain 26d and source 26s of the switch transistor 26, the drain 28d and source 28s of the holding transistor 28, the drain 30d and source 30s of the driving transistor 30, and the electrode 32B of the capacitor 32, and the pixel circuit P _{1,1 to} P _{m, n} The scanning lines X _{1 to} X _m and the power supply wiring 14 are obtained by patterning the same conductive film formed on the entire surface of the gate insulating film 34 through the adhesion layer 36 by the photolithography method and the etching method. . Hereinafter, the drains 26 d to 30 d and the sources 26 s to 30 s of the transistors 26 to 30, the electrode 32 B of the capacitor 32, the scanning lines X _{1 to} X _m and the conductive film that is the source of the power supply wiring 14 are referred to as the drain wiring layer 42. Called. As shown in FIG. 4, the drain 26d of the switch transistor 26, the source 30s of the drive transistor 30, and the electrode 32B of the capacitor 32 are formed by patterning so as to be integrated.

Further, as shown in FIG. 4, the scanning line X _i is electrically connected to the gate 26g of the switch transistor 26 and the gate 28g of the holding transistor 28 through the contact hole 38 formed in the gate insulating film 34, and the signal line Y _j Is electrically connected to the source 26s of the switch transistor 26 through the contact hole 41 formed in the gate insulating film 34, and the source 28s of the holding transistor 28 is connected to the drive transistor through the contact hole 43 formed in the gate insulating film 34. 30 is electrically connected to the gate 30g.

The switch transistor 26, the holding transistor 28, the driving transistor 30, the scanning lines X _{1 to} X _m, and the power supply wiring 14 are covered with an interlayer insulating film 44 formed on the entire surface.

An organic planarizing film 46 is laminated on the interlayer insulating film 44, and unevenness due to the switch transistor 26, the holding transistor 28, the driving transistor 30, the scanning lines X _{1 to} X _m and the power supply wiring 14 is formed on the organic planarizing film 46. Has been eliminated.

  A stacked structure from the insulating substrate 12 to the organic planarization film 46 is referred to as a transistor array substrate 48. In the transistor array substrate 48, the switch transistors 26, the holding transistors 28, and the driving transistors 30 are arranged in a matrix in a plan view.

  Next, the layer structure laminated on the surface of the transistor array substrate 48 will be described. On the surface of the transistor array substrate 48, that is, on the surface of the organic planarization film 46, a plurality of transparent anode electrodes 20 a are arranged in a matrix via a reflective layer 50 having high conductivity and high visible light reflectivity. ing. As the reflective layer 50, chromium, silver, or a silver alloy is used. The organic planarization film 46 (and the interlayer insulating film 44) is provided with at least one organic planarization film opening 46 ', and a contact hole 52 is formed there. In the contact hole 52, the reflection layer 50 and the transparent anode electrode 20a extend. Therefore, the transparent anode electrode 20a is connected to the electrode 32B of the capacitor 32 and the source 30s of the driving transistor 30 (and the drain 26d of the switch transistor 26) through the contact hole 52 formed in the organic planarization film 46 and the interlayer insulating film 44. Is conducting. The inside of the contact hole 52 is filled with the interlayer insulating film 54 formed on the organic planarizing film 46 via the reflective layer 50 and the transparent anode electrode 20a.

The transparent anode electrode 20 a is a pixel electrode of the organic EL element 20. That is, it is preferable that the transparent anode electrode 20a has a relatively high work function and efficiently injects holes into the light emitting layer 20e described later. Further, the transparent anode electrode 20a is transmissive to visible light. As the transparent anode electrode 20a, for example, ITO, zinc-doped indium oxide, indium oxide (In ₂ 0 ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), or cadmium-tin oxide (CTO) is a main component. There is what I did. In this embodiment, ITO is used.

  An adhesion layer 56 made of chromium (Cr), titanium (Ti) or the like is patterned between the adjacent transparent anode electrodes 20a. Specifically, the adhesion layer 56 is formed in a lattice shape extending in the column direction as a base layer of the common wiring 16. On the adhesion layer 56 between the transparent anode electrodes 20a adjacent in the horizontal direction, the common wiring 16 is laminated along the column direction.

Common wiring 16, the signal lines _Y 1 to Y _n, the scanning lines _X 1 to X _m and the gate electrode and the source of the feed interconnection 14 and transistors 26 to 30, sufficiently thicker than the drain electrode. The common wiring 16 includes at least one of copper, aluminum, gold, and nickel.

  A liquid repellent conductive film 58 having water and oil repellency is formed on the surface of the common wiring 16. In the liquid repellent conductive film 58, the hydrogen atom (H) of the thiol group (—SH) of triazyltrithiol is reduced and released, and the sulfur atom (S) is oxidized and adsorbed on the surface of the common wiring 16.

  Since the liquid repellent conductive film 58 is a film composed of a single layer of molecules in which triazyltrithiol molecules are regularly arranged on the surface of the common wiring 16, the liquid repellent conductive film 58 has a very low resistance and is conductive. In addition, in order to make water repellency and oil repellency remarkable, it may replace with triazyl trithiol and the thiol group of 1 or 2 of triazyl trithiol may be substituted by the fluoroalkyl group.

  The organic EL layer of the organic EL element 20 is formed on the transparent anode electrode 20a. The organic EL layer is a light-emitting layer in a broad sense, and the organic EL layer contains a light-emitting material (phosphor) that is an organic compound. The organic EL layer has a multilayer structure in which a hole injection layer 20h and a narrowly-defined light emitting layer 20e are sequentially stacked from the transparent anode electrode 20a. The hole injection layer 20h is made of PEDOT (polythiophene) which is a conductive polymer and PSS (polystyrene sulfonic acid) which is a dopant, and the light emitting layer 20e in a narrow sense is made of a polyfluorene light emitting material.

  The organic EL layer is formed by a wet application method (for example, an ink jet method) after coating the liquid repellent conductive film 58. In this case, an organic compound-containing liquid containing an organic compound that becomes an organic EL layer is applied to the transparent anode 20 a, and the liquid level of the organic compound-containing liquid is higher than the top of the interlayer insulating film 54. Since the common wiring 16 having a thick film whose top is sufficiently higher than the top of the interlayer insulating film 54 is provided between the transparent anodes 20a adjacent in the horizontal direction, the organic compound-containing liquid applied to the transparent anode 20a. Is dammed so as not to leak into the transparent anode electrode 20a adjacent in the horizontal direction. Further, since the common wiring 16 is coated with a water-repellent / oil-repellent liquid-repellent conductive film 58, it repels the organic compound-containing liquid applied to the transparent anode electrode 20a, so that it is applied to the transparent anode electrode 20a. Since the organic compound-containing liquid is not deposited extremely thick near the corner of the insulating film 56 with respect to the center of the transparent anode electrode 20a, an organic EL layer formed by drying the organic compound-containing liquid is formed with a uniform film thickness. can do.

  By forming an organic EL layer between the common wirings 16 in this way, a region where an organic EL layer emitting red light is formed, a region where an organic EL layer emitting green light is formed, and blue light emission. A region where the organic EL layer is formed forms a stripe structure arranged in this order, and a plurality of pixels in the same column emit light of the same color.

  When viewed in a plan view, the applied organic compound-containing liquid is uniformly distributed in each column in the vertical direction because the left and right sides in the horizontal direction are each partitioned into one of the common wirings 16, so that the vertical direction The plurality of arranged organic EL layers all have the same layer structure and emit light in the same color. Although the transparent anode electrode 20a and the organic EL layer are elongated in the shape of a band along the vertical direction of the drawing, they may be long in the horizontal direction of the drawing.

  In addition to the above layer structure, the organic EL layer may have a three-layer structure that becomes a hole injection layer 20h, a light emitting layer 20e in a narrow sense, and an electron injection layer in order from the transparent anode electrode 20a, or light emission in a narrow sense. A single layer structure composed of the layer 20e may be used, or a laminated structure in which an electron or hole transport layer is further interposed in these layer structures, or an electron or hole injection layer may be used instead of the electron or hole injection layer. A hole transport layer may be interposed, or another laminated structure may be used.

  On the organic EL layer, a transparent cathode electrode 20c that is a counter electrode of the organic EL element 20 is formed. The transparent cathode electrode 20c is a common electrode formed in common for all pixels, and is formed on the entire surface. The transparent cathode electrode 20c is formed on the entire surface, so that the transparent cathode electrode 20c covers the common wiring 16 with the liquid repellent conductive film 58 interposed therebetween. Therefore, as shown in the circuit diagram of FIG. 3, the transparent cathode electrode 20 c is electrically connected to the common wiring 16.

  The transparent cathode electrode 20c is formed of a material having a work function lower than that of the transparent anode electrode 20a. For example, the transparent cathode electrode 20c is formed of a simple substance or an alloy containing at least one of magnesium, calcium, lithium, barium, indium, and a rare earth metal. It is preferable. In addition, the transparent cathode electrode 20c may have a laminated structure in which layers of the above various materials are laminated. In addition to the above layers of various materials, a metal layer that is not easily oxidized is deposited in order to reduce sheet resistance. Specifically, a low-work function high-purity barium layer provided on the interface side in contact with the organic EL layer, and an aluminum layer provided so as to cover the barium layer, And a laminated structure in which a lower layer is provided with a lithium layer and an upper layer is provided with an aluminum layer. The transparent cathode electrode 20c may be a transparent electrode in which a thin film having a low work function as described above and a transparent conductive film such as ITO are laminated thereon.

  A sealing insulating thin film 60 is formed on the transparent cathode electrode 20c. The sealing insulating thin film 60 is a transparent inorganic film or organic film that covers the entire transparent cathode electrode 20c and is provided to prevent deterioration of the transparent cathode electrode 20c.

  Conventionally, in an EL display panel having a top emission type structure, a transparent electrode having a relatively high resistance value such as a metal oxide has been used for at least a part of the transparent cathode electrode 20c. If such a material is not thick enough, the sheet resistance will not be sufficiently low. However, by increasing the thickness, the transmittance of the organic EL element will inevitably decrease, and the larger the screen, the more uniform the potential in the plane. It was difficult to display the display characteristics. However, in this embodiment, since the plurality of common wirings 16 that are sufficiently thick in the vertical direction and have a low resistance are provided, the resistance value of the entire cathode electrode of the organic EL element 20 is lowered together with the transparent cathode electrode 20c. It is possible to flow a large current sufficiently and uniformly in a plane. Further, in such a structure, since the common wiring 16 reduces the resistance of the cathode electrode, it is possible to improve the transmittance by making the transparent cathode electrode 20c a thin film.

  Further, in the conventional EL display panel, the transparent anode electrode 20a is formed on the drain wiring layer 42. However, in this embodiment, the transparent anode electrode 20a is completely formed of the reflective layer 50 made of chromium, silver, or a silver alloy. The reflective layer 50 is formed so as to completely cover the region where the drain wiring layer 42 is exposed in the contact hole 52 portion. Therefore, conventionally, when a pin hole is opened in the transparent anode electrode 20a in the contact hole 52, the resist is peeled off by a combination of the transparent anode electrode 20a (for example, ITO) and the drain wiring layer 42 (for example, aluminum-based metal). Although the drain wiring layer 42 may be disconnected due to the battery reaction in the liquid, in this embodiment, even if such a pinhole is opened, the transparent anode electrode 20a (for example, ITO) and the reflective layer 50 are formed. Since the combination of (for example, chromium) does not proceed with the battery reaction in the resist stripping solution as compared with the conventional combination, the contact portion can be formed with high yield. Furthermore, if silver or a silver alloy is selected as the material of the reflective layer 50, the battery reaction in the resist stripping solution can be similarly suppressed, and the reflectance is higher than that of chromium, so that a favorable reflective layer can be formed. .

On the other hand, for the gate wiring terminal portion is a terminal 18U for connecting the signal line _Y 1 to Y _n in the external circuit of the organic EL display panel 10, as shown in FIG. 6 (B), the signal lines _Y 1 ~ on the gate wiring layer 40 is the underlying conductive film of Y _n, via an adhesion layer 36, drain wiring layer 42 is deposited. The drain wiring layer 42, as described above, when forming the electrode 32B and the scanning lines _X 1 to X _m and the feed interconnection 14 of each drain 26d~30d and source 26s~30s and capacitor 32 of the transistor 26 to 30 It is formed. Then, a reflective layer 50 is formed on the drain wiring layer 42 so as to completely cover the region where the drain wiring layer 42 is exposed, like the contact hole 52, and further, the transparent anode 20a. Are formed so as to completely cover the reflective layer 50. Therefore, in this gate wiring terminal portion as well, as in the contact hole 52 portion, even if a pin hole is opened in the transparent anode electrode 20a, the battery reaction in the resist stripping solution does not proceed. Can be formed.

The terminal 18L for connecting the scanning lines _X 1 to X _m and the power supply wiring 14 to an external circuit of the organic EL display panel 10, the drain wiring terminal portion is 18R, as shown in FIG. 6 (C) is the underlying conductive film of the scanning lines X ₁ to X _m and the power supply wiring 14 on the drain wiring layer 42, similarly to the portion of the contact hole 52, the area where the drain wiring layer 42 is exposed The reflective layer 50 is formed so as to be completely covered, and the transparent anode electrode 20a is further formed so as to completely cover the reflective layer 50. Accordingly, in this drain wiring terminal portion as well, as with the contact hole 52 portion, even if a pin hole is opened in the transparent anode electrode 20a, the battery reaction in the resist stripping solution does not proceed, so the terminal portion has high yield. Can be formed.

  Next, a method for manufacturing the EL display panel 10 in the present embodiment will be described. FIGS. 8A to 22A are cross-sectional views at each step in the pixel circuit portion as shown in FIG. 6A. Similarly, FIGS. 8B to 22B are shown. ) Is a gate wiring terminal portion as shown in FIG. 6B, and FIGS. 8C to 22C are cross-sectional views at each step in the drain wiring terminal portion as shown in FIG. 6C. Is shown.

First, a gate formation step is performed as a first step. That is, in this gate formation step, first, the gate wiring layer 40 is formed on the entire surface of the insulating substrate 12 by vapor deposition such as CVD, PVD, or sputtering. Next, by applying a photolithography etching method in order for the gate wiring layer 40, the pixel circuits _P 1, 1 _{to P m, n} of the gate 26 g, 28 g, 30 g and the electrodes 32A and the signal lines _{Y 1} patterning the ~Y _n. At the end of this step, the pattern of the gate wiring layer 40 is left on the insulating substrate 12 in the pixel circuit portion and the gate wiring terminal portion as shown in FIGS. In the portion, the gate wiring layer 40 is removed from the insulating substrate 12 as shown in FIG.

Next, a channel protective film forming step is performed as a second step. That is, in this channel protective film forming step, first, the gate insulating film 34 is formed on the entire surface by vapor deposition. Further thereon, a semiconductor film 30A is formed on the entire surface by vapor deposition. Next, the channel protective film 30B of each of the pixel circuits P _{1,1 to} P _{m, n} is patterned by sequentially performing a vapor deposition method, a photolithography method, and an etching method. At the end of this step, in the pixel circuit portion, as shown in FIG. 9A, the pattern of the channel protective film 30B is left on the semiconductor film 30A, and in the gate wiring terminal portion and the drain wiring terminal portion, FIG. As shown in FIGS. 9B and 9C, the channel protective film 30B is removed from the semiconductor film 30A.

Next, a source / drain formation step is performed as a third step. That is, in this source / drain formation step, first, the vapor deposition method, the photolithographic method, and the etching method are sequentially performed, so that the drains 26d, 28d, and 30d of the pixel circuits P _{1,1 to} P _{m, n} and the source are formed. 26s, 28s, and 30s are patterned. Further, the semiconductor film 30A is patterned by sequentially performing a photolithography method and an etching method. At the end of this process, in the pixel circuit portion, as shown in FIG. 10A _, the drains 26d, 28d, 30d of the pixel circuits P _{1,1 to} P _{m, n} and The patterns of the sources 26s, 28s, and 30s are left through the semiconductor film 30A and the channel protective film 30B, and the semiconductor films 30A and the channel protective film 30B are the patterns of the drains 26d, 28d, and 30d and the sources 26s, 28s, and 30s. It is removed except for the part. Further, in the gate wiring terminal portion and the drain wiring terminal portion, as shown in FIGS. 10B and 10C, the semiconductor film 30A is removed from the gate insulating film 34.

  Next, a gate insulating film contact formation step is performed as a fourth step. That is, in this gate insulating film contact formation step, by performing photolithography and etching in order, the gate insulating film 34 is removed from the gate wiring terminal portion as shown in FIG. Form. At the end of this step, the pixel circuit portion and the drain wiring terminal portion, as shown in FIGS. 11 (A) and (C), are shown in FIG. 10 (A) and FIG. There is no change from the state shown in (C).

Next, a drain wiring layer forming step is performed as a fifth step. That is, in this drain wiring layer forming step, first, an adhesion layer 36 of chromium or the like is formed on the entire surface of the gate insulating film 34 by vapor deposition. Next, a photolithography method and an etching method are sequentially performed on the adhesion layer 36, whereby the drains 26d, 28d, and 30d, and the sources 26s, 28s, and 30s of the pixel circuits P _{1,1 to} P _{m, n} are obtained. and patterning the electrode 32B and to become partial scan lines _X 1 to X _m and the feed interconnection 14. Further, the drain wiring layer 42 is formed on the entire surface by vapor deposition. Next, a photolithography method and an etching method are sequentially performed on the drain wiring layer 42, whereby the drains 26d, 28d, and 30d and the sources 26s, 28s, and 30s of the pixel circuits P _{1,1 to} P _{m, n} are formed. and patterning the electrode 32B and to become partial scan lines _X 1 to X _m and the feed interconnection 14. At the end of this step, as shown in FIGS. 12A to 12C, the layer structure of the adhesion layer 36 and the drain wiring layer 42 is patterned.

Next, an interlayer insulating film forming step is performed as a sixth step. That is, in this interlayer insulating film forming step, first, the interlayer insulating film 44 is formed on the entire surface by vapor deposition. Thereafter, the interlayer insulating film 44 is sequentially subjected to a photolithography method and an etching method, so that the contact of each pixel circuit P _{1,1 to} P _{m, n} is obtained as shown in FIGS. The interlayer insulating film 44 is removed from the portion to be the hole 52 and the gate wiring terminal portion and the drain wiring terminal portion.

Next, an organic planarizing film forming step is performed as a seventh step. That is, in this organic planarization film forming step, first, a resin is applied to the entire interlayer insulating film 44, and the resin is dried to form an organic planarization film 46 of about 2 μm on the entire surface. Of course, this film thickness is an example, and if the size of the organic EL display panel 10 is large, it is thick, and if it is small, it is thin. Then, as shown in FIGS. 14A to 14C, from the portions that become the contact holes 52, the gate wiring terminal portions, and the drain wiring terminal portions of the pixel circuits P _{1,1 to} P _{m, n} by the exposure development method. Then, after forming a groove-like opening (organic planarization film opening 46 ′) in the organic planarization film 46, the organic planarization film 46 is cured by a post-bake (heat treatment) method.

  Thus, the transistor array substrate 48 is completed.

Next, a reflective layer forming step is performed as an eighth step. That is, in this reflective layer forming step, first, a metal layer such as chromium or silver alloy is formed by vapor phase growth. Then, by subjecting the metal layer to photolithography and etching in order, as shown in FIGS. 15A to 15C _, the organic EL elements of the pixel circuits P _{1,1 to} P _{m, n} The reflective layer 50 is laminated at the position of 20 and the inside of the contact hole 52, and at the gate wiring terminal portion and the drain wiring terminal portion.

Next, a transparent anode electrode forming step is performed as a ninth step. That is, in this transparent anode electrode forming step, first, a transparent conductive film such as ITO is formed on the entire surface of the transistor array substrate 48 by a vapor phase growth method such as sputtering. Then, by applying a photolithography method and an etching method to the transparent conductive film in order, as shown in FIGS. 16A to 16C _, the organic circuits of the pixel circuits P _{1,1 to} P _{m, n} The transparent anode electrode 20a is laminated on the reflective layer 50 formed in the position of the EL element 20, the inside of the contact hole 52, and the gate wiring terminal portion and the drain wiring terminal portion. In this case, the transparent anode electrode 20 a is formed so as to protrude beyond the reflective layer 50.

  Since the transparent anode electrode 20a has a very thin film thickness of, for example, 500 mm or less, pinholes are easily generated. If the transparent anode electrode 20a is formed on the drain wiring layer 42 using an aluminum-based metal, a battery reaction occurs in the etching process during patterning of the transparent anode electrode 20a due to such pinholes, and the drain wiring. There is a risk of causing disconnection of the layer 42. However, in this embodiment, since the reflective layer 50 is interposed between the transparent anode electrode 20a and the drain wiring layer 42, the battery reaction in the resist stripping solution does not proceed, so that the contact in the contact hole 52 with a high yield is achieved. And gate wiring terminal portions and drain wiring terminal portions can be formed.

Next, an interlayer insulating film forming step is performed as a tenth step. That is, in this interlayer insulating film forming step, first, the interlayer insulating film 54 is formed on the entire surface by vapor deposition. Thereby, the inside of the contact hole 52 is filled with the interlayer insulating film 54. Then, by subjecting the interlayer insulating film 54 to photolithography and etching in order, as shown in FIGS. 17A to 17C _, the organic circuits of the pixel circuits P _{1,1 to} P _{m, n} The interlayer insulating film 54 is removed from the position of the EL element 20 and the gate wiring terminal portion and the drain wiring terminal portion. Thereby, the light emission part of each pixel is prescribed | regulated.

  Next, a common wiring forming step is performed as an eleventh step. That is, in this common wiring forming step, first, the adhesion layer 56 is formed by vapor deposition. Then, the adhesion layer 56 is patterned between the transparent anode electrodes 20a adjacent to each other in the horizontal direction and on the interlayer insulating film 54 by sequentially performing photolithography and etching on the adhesion layer 56. . Next, the common wiring 16 is grown thereon by a plating method. Thereafter, the common wiring 16 is patterned on the adhesion layer 56 by sequentially performing a photolithography method and an etching method on the common wiring 16 as shown in FIG. Further, as shown in FIGS. 18B and 18C, the adhesion layer 56 and the common wiring 16 are removed from the gate wiring terminal portion and the drain wiring terminal portion.

  Next, a hydrophilic / hydrophobic process is performed as a twelfth process. That is, in this hydrophilic / hydrophobic forming step, first, the common wiring 16 is coated with the triazyltrithiol solution on the entire surface of the common wiring 16, or the panel is immersed in the triazyltrithiol solution. The surface of 16 is selectively made liquid-repellent, that is, a liquid-repellent conductive film 58 is selectively formed. Although the liquid repellent conductive film 58 is formed on the surface of the common wiring 16 and the transparent anode electrode 20a due to the nature of triazyltrithiol, the liquid repellent conductive film is not formed on the surface of the interlayer insulating film 54. . Then, in order to cancel the liquid repellency on the surface of the transparent anode electrode 20a, a hydrophilic treatment is performed on the transparent anode electrode 20a. As a result, as shown in FIGS. 19A to 19C, the liquid repellent conductive film 58 remains only on the surface of the common wiring 16.

  Next, a hole injection layer forming step is performed as a thirteenth step. That is, in this hole injection layer forming step, as shown in FIG. 20A, the hole injection layer 20h is patterned by a wet coating method in which PEDOT is applied and dried. Since the thick common wiring 16 is provided between the transparent anode electrodes 20a adjacent to each other in the horizontal direction, and further, the common wiring 16 is coated with a water- and oil-repellent liquid-repellent conductive film 58. The PEDOT-containing liquid applied to the transparent anode electrode 20a does not leak to the adjacent transparent anode electrode 20a. As shown in FIGS. 20B and 20C, the hole injection layer 20h is not formed for the gate wiring terminal portion and the drain wiring terminal portion.

  Next, a light emitting layer forming step is performed as a fourteenth step. That is, in this light emitting layer forming step, the interlayer is applied and dried by a wet coating method as necessary, and then an organic compound of a polyfluorene-based luminescent material is applied and dried as shown in FIG. The light emitting layer 20e is patterned by a wet coating method. As described above, since the thick common wiring 16 is provided between the transparent anode electrodes 20a adjacent to each other in the horizontal direction, the common wiring 16 is further coated with a water- and oil-repellent liquid-repellent conductive film 58. Therefore, the organic compound-containing liquid applied to the transparent anode electrode 20a does not leak to the adjacent transparent anode electrode 20a. Further, since the organic compound-containing liquid applied to the transparent anode electrode 20a does not thicken around the transparent anode electrode 20a due to the water and oil repellency of the liquid repellent conductive film 58, the light emitting layer 20e is formed with a uniform film thickness. Can be membrane. As shown in FIGS. 21B and 21C, the light emitting layer 20e is not formed for the gate wiring terminal portion and the drain wiring terminal portion.

  Next, a cathode electrode forming step is performed as a fifteenth step. That is, in this cathode electrode forming step, an electron injection layer such as barium or calcium is vapor-deposited on the light emitting layer 20e as necessary, and then the transparent cathode electrode 20c is formed by sputtering as shown in FIG. A film is formed on one surface through a metal mask. Since the light emitting layer 20e is very sensitive to temperature, the deposition of the electron injection layer and the sputtering of the transparent cathode electrode 20c do not increase the temperature so as not to damage the light emitting layer 20e (about 100 ° C.). It is necessary to carry out with. Then, by patterning the transparent cathode electrode 20c thus formed using a metal mask, as shown in FIGS. 22 (B) and 22 (C), the transparent cathode electrode 20c is turned from the gate wiring terminal portion and the drain wiring terminal portion to the transparent cathode. The electrode 20c is removed.

  Next, a sealing insulating film forming step is performed as a sixteenth step. That is, in this sealing insulating film forming step, first, a sealing insulating thin film 60 is formed on one surface through a metal mask by vapor deposition, as shown in FIGS. 6A to 6C. Then, the sealing insulating thin film 60 is patterned.

  The organic EL display panel 10 is completed through the above steps.

  According to the first embodiment as described above, in the top emission type organic EL display panel 10 using the organic EL element as the light emitting element, the transparent anode electrode 20a is provided with the reflective layer 50 made of chromium, silver, or a silver alloy. The reflective layer 50 is formed so as to completely cover the region where the drain wiring layer 42 is exposed in the contact hole 52, so that the transparent anode is formed in the contact hole 52. Even if pinholes are opened in the electrode 20a, the combination of the transparent anode electrode 20a (for example, ITO) and the reflective layer 50 (for example, chromium) does not advance the battery reaction in the resist stripping solution, so a contact portion is formed with high yield. it can. Furthermore, if silver or a silver alloy is selected as the material of the reflective layer 50, the battery reaction in the resist stripping solution can be similarly suppressed, and the reflectance is higher than that of chromium, so that a favorable reflective layer can be formed. .

Further, in the gate wiring terminal portion which is a terminal for connecting the signal lines Y _{1 to} Y _n to the external circuit of the organic EL display panel 10, a gate which is a conductive film which is the source of the signal lines Y _{1 to} Y _n A drain wiring layer 42 is formed on the wiring layer 40 via an adhesion layer 36, and a reflective layer is formed on the drain wiring layer 42 so as to completely cover a region where the drain wiring layer 42 is exposed. 50, and further, the transparent anode electrode 20a is formed so as to completely cover the reflective layer 50. Therefore, in the gate wiring terminal portion as well as the contact hole 52, the transparent anode electrode 20a is formed. Even if a pinhole is opened at 20a, the battery reaction does not proceed in the resist stripping solution, so that the terminal portion can be formed with a high yield.

Similarly, with regard drain wiring terminal portion is a terminal for connecting the scan lines _X 1 to X _m and the power supply wiring 14 to an external circuit of the organic EL display panel 10, scan lines _X 1 to X _m and the feed interconnection 14 A reflective layer 50 is formed on the drain wiring layer 42, which is a conductive film serving as a base of the film, so as to completely cover the region where the drain wiring layer 42 is exposed. Since the layer 50 is formed so as to completely cover the drain wiring terminal portion, even if a pinhole is opened in the transparent anode electrode 20a, the battery reaction in the resist stripping solution does not proceed, so the yield is high. A terminal part can be formed.

Further, after forming the reflective layer 50 of the pixel circuits P _{1,1 to} P _{m, n} and forming the transparent anode electrode 20a such as ITO on the reflective layer 50, the interlayer insulating film 54 such as SiN film and the common wiring 16 are formed. Through this process, there is a process for forming an organic EL layer (hole injection layer 20h and light emitting layer 20e). Here, when there is no protective layer by the transparent anode electrode 20a on the reflective layer 50, the reflective layer 50 is damaged (etched) by the dry etching or the wet etching when the interlayer insulating film 54 is etched. . That is, in the case of dry etching, it is oxidized with O ₂ plasma. Further, in the case of wet etching, a hydrofluoric acid-based etching solution is used, so that the reflective layer 50 is etched by this etching solution. However, in the first embodiment, since the protective layer by the transparent anode electrode 20a is provided on the reflective layer 50, such damage can be prevented.

  Further, when forming the common wiring 16 also serving as the partition wall, the reflective layer 50 may be etched during the etching, but this embodiment can prevent this. Also, when forming the organic EL layer (the hole injection layer 20h and the light emitting layer 20e), since the general hole injection layer 20 is a strong acid, the reflective layer 50 is etched, but according to the present embodiment, This can be prevented.

Similarly, the terminals 18L, 18R, and 18U are also protected by the transparent anode electrode 20a (ITO) in the same manner as the pixel circuits _{P1,1 to} Pm _{, n} .

  Since the contact hole 52 is also covered with the insulating film 50, it is not affected by the etching described above.

  In the present embodiment, the end surface of the reflective layer 50 is entirely covered with the transparent anode electrode 20a (ITO). When the transparent anode electrode 20a is formed on the reflective layer 50 and the transparent anode electrode 20a is wet-etched, if the end surface of the reflective layer 50 is exposed, the end surface of the reflective layer 50 is side-etched and the reflective layer 50 is The cavity may recede, and a cavity may be formed below the end face of the transparent anode electrode 20a. A liquid may be poorly dried in the cavity, which may affect the reliability of the device. In the present embodiment, the end surface of the reflective layer 50 is entirely covered with the transparent anode electrode 20a, so that side etching of the reflective layer 50 can be prevented during wet etching of the transparent anode electrode 20a.

  Further, since the etching of the interlayer insulating film 54 is performed only on the transparent anode electrode 20a as in the portion of the interlayer insulating film opening 54 ', even if the end surface of the reflective layer 50 is covered with the transparent anode electrode 20a, it is covered. Even if not, there is no influence of the etching of the interlayer insulating film 54. However, the damage during the formation of the interlayer insulating film 54 is related to whether or not the end face of the reflective layer 50 is covered with the transparent anode electrode 20a. That is, if the end face of the reflective layer 50 is not covered with the transparent anode electrode 20a, the reflective layer 50 may be damaged by the deposition temperature or plasma particles when the interlayer insulating film 54 is formed. When the end face of the reflective layer 50 is covered with the transparent anode electrode 20a, such damage can be prevented from occurring.

[Second Embodiment]
Next, a second embodiment of a display panel using the light emitting device of the present invention will be described. In addition, the organic EL display panel 10 in this embodiment is also a top emission type display panel using an organic EL element as a light emitting element, as in the first embodiment. Here, portions similar to those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

23 and 24 are plan views mainly showing electrodes of the pixel circuits P _{i, j in} the active matrix driving type organic EL display panel 10 according to the present embodiment. In order to make the drawing easy to see _, the transparent anode electrode 20a of the pixel circuit P _{i, j} is not shown in FIG. 23, and the lower layer side electrode of the pixel circuit P _{i, j} is not shown in FIG. . 25A is a cross-sectional view taken along line AA of the pixel circuit portion shown in FIGS. 23 and 24, and FIG. 25B is a cross-sectional view of a gate wiring terminal portion which is a terminal 18U. FIG. 25C is a cross-sectional view of the drain wiring terminal portion which is the terminal 18L or the terminal 18R. FIG. 26 is a cross-sectional view taken along line DD of the pixel circuit portion shown in FIGS.

That is, in this embodiment, as shown in FIG. 23, FIGS. 24 and 26, on scan lines _X 1 to X _m and the feed interconnection 14, along their scanning lines _X 1 to X _m and the feed interconnection 14, contact them scan line layer 62 via the X ₁ to X _m and the feed interconnection 14 and the anode power supply wiring 63 are electrically connected it is patterned. In addition, as shown in FIGS. 25A to 25C, the contact hole 52 and the gate wiring terminal portion and the drain wiring terminal portion are in close contact with each other between the drain wiring layer 42 and the reflective layer 50. An anode auxiliary layer 64 is formed through the layer 62.

The anode power supply wiring 63 and the anode auxiliary layer 64 are formed at the same time as the scanning line X _i , the power supply wiring 14, and the drain 30 d in order to reduce the resistance of the bus line in order to prevent the voltage drop of the bus line. Laminate on top. As the material of the anode power supply wiring 63 and the anode auxiliary layer 64, aluminum, an aluminum-based alloy or the like is used, and as the material of the adhesion layer 62, chromium or the like is used.

  The transparent anode electrode 20a is formed so as to completely cover the reflective layer 50. The reflective layer 50 includes the contact hole 52 portion where the anode auxiliary layer 64 is exposed, the gate wiring terminal portion, and the drain. The wiring terminal portion is formed so as to completely cover the portion where the transparent anode electrode 20a is exposed.

  Next, a method for manufacturing the EL display panel 10 in the present embodiment will be described. FIGS. 27A to 36A are cross-sectional views in each step in the pixel circuit portion as shown in FIG. 25A. Similarly, FIGS. 27B to 36B are shown. ) Is a gate wiring terminal portion as shown in FIG. 25B, and FIGS. 27C to 36C are cross-sectional views at each step in the drain wiring terminal portion as shown in FIG. Is shown.

In the present embodiment, the first embodiment as described with reference to FIGS. 8A, 8B, and 13C to 13A, 13B, and 13C in the first embodiment. Steps (gate formation step) to sixth step (interlayer insulating film formation step) are performed. However, in the sixth step, the interlayer insulating film 44 is also removed from the scanning lines X _{1 to} X _m and the power supply wiring 14.

Thereafter, in the present embodiment, an anode auxiliary layer forming step is performed as a seventh step. That is, in this anode auxiliary layer forming step, first, an adhesion layer 62 such as chromium is formed on the entire surface of the interlayer insulating film 44 by vapor phase growth. Next, a photolithography method and an etching method are sequentially performed on the adhesion layer 62, so that the contact hole 52 portion of each of the pixel circuits _{P1,1 to} Pm _{, n} , the gate wiring terminal portion, and the drain wiring patterning the portion of the terminal portion (and the portion of the scanning lines _X 1 to X _m and the power supply wiring 14). Furthermore, an anode auxiliary layer 64 (and anode power supply wiring 63) such as aluminum or an aluminum alloy is formed on the entire surface by vapor deposition. Next, a photolithography method and an etching method are sequentially performed on the anode auxiliary layer 64 (and the anode power supply wiring 63), thereby the contact hole 52 portion of each of the pixel circuits P _{1,1 to} P _{m, n} and The portions of the gate wiring terminal portion and the drain wiring terminal portion (and the scanning lines X _{1 to} X _m and the power supply wiring 14 portions) are patterned. At the end of this step, as shown in FIGS. 27A to 27C, the layer structure of the adhesion layer 62 and the anode auxiliary layer 64 (and the anode power supply wiring 63) is patterned.

Next, as an eighth step, an organic planarization film forming step corresponding to the seventh step in the first embodiment is performed. That is, in this organic planarization film forming process, first, a resin is applied to the entire interlayer insulating film 44, and the resin is dried to form the organic planarization film 46 on the entire surface. Then, as shown in FIGS. 28A to 28C _{, from the} portions that become the contact holes 52 of the pixel circuits P _{1,1 to} P _{m, n} by the exposure development method, the gate wiring terminal portions and the drain wiring terminal portions. Then, after each of the organic planarizing film 46 is formed with a groove-like opening, the organic planarizing film 46 is cured by a post-bake (heat treatment) method.

  Thus, the transistor array substrate 48 is completed.

Next, as a ninth step, a reflective layer forming step corresponding to the eighth step in the first embodiment is performed. That is, in this reflective layer forming step, each of the pixel circuits P _{1,1 to} P is performed by sequentially performing a vapor phase growth method, a photolithography method, and an etching method, as shown in FIGS. A reflective layer 50 such as chromium or silver alloy is laminated on the position of the _{m and n} organic EL elements 20, the inside of the contact hole 52, and the gate wiring terminal portion and the drain wiring terminal portion. That is, the reflective layer 50 is formed so as to completely cover the exposed portion of the anode auxiliary layer 64.

Next, as a tenth step, a transparent anode electrode forming step corresponding to the ninth step in the first embodiment is performed. That is, in this transparent anode electrode formation step, each pixel circuit P ₁ is subjected to a vapor phase growth method such as sputtering, a photolithography method, and an etching method in order, as shown in FIGS. _{, 1 to} Pm _{, n} on the reflective layer 50 formed in the position of the organic EL element 20 and in the contact hole 52 and in the gate wiring terminal portion and the drain wiring terminal portion with a transparent conductive film such as ITO. A certain transparent anode electrode 20a is laminated. In this case, the transparent anode electrode 20 a is formed so as to protrude beyond the reflective layer 50.

  Thus, since the reflective layer 50 is interposed between the transparent anode electrode 20a and the anode auxiliary layer 64, the battery reaction in the resist stripping solution does not proceed. A wiring terminal portion and a drain wiring terminal portion can be formed.

Next, as an eleventh step, an interlayer insulating film forming step corresponding to the tenth step in the first embodiment is performed. That is, in this interlayer insulating film forming process, by performing vapor phase growth, photolithography, and etching in order, as shown in FIGS. _31A to _31C , each pixel circuit P _1,1 . An interlayer insulating film 54 is formed except for the position of the Pm _{, n} organic EL element 20 and the gate wiring terminal portion and the drain wiring terminal portion. Thereby, the light emission part of each pixel is prescribed | regulated. Further, the inside of the contact hole 52 is filled with an interlayer insulating film 54.

  Next, as a twelfth step, a common wiring forming step corresponding to the eleventh step in the first embodiment is performed. That is, in this common wiring formation step, first, vapor deposition, photolithography, and etching are performed in order, so that the transparent anode electrodes 20a adjacent to each other in the horizontal direction are formed on the interlayer insulating film 54. The adhesion layer 56 is patterned. Further, the common wiring 16 is patterned on the adhesion layer 56 by sequentially performing a plating method, a photolithography method, and an etching method, as shown in FIG. Further, as shown in FIGS. 32B and 32C, the insulating film 56 and the common wiring 16 are removed from the gate wiring terminal portion and the drain wiring terminal portion.

  Next, as a thirteenth step, a hydrophilic / hydrophobic step corresponding to the twelfth step in the first embodiment is performed. That is, in this hydrophilic / water-repellent process, first, the surface of the common wiring 16 is selectively liquid-repellent, that is, the liquid-repellent conductive film 58 is selectively formed. Then, in order to cancel the liquid repellency on the surface of the transparent anode electrode 20a, a hydrophilic treatment is performed on the transparent anode electrode 20a. As a result, as shown in FIGS. 33A to 33C, the liquid repellent conductive film 58 remains only on the surface of the common wiring 16.

  Next, as a fourteenth step, a hole injection layer forming step corresponding to the thirteenth step in the first embodiment is performed. That is, in this hole injection layer forming step, as shown in FIG. 34A, the hole injection layer 20h is patterned by a wet coating method in which PEDOT is applied and dried. Since the thick common wiring 16 is provided between the transparent anode electrodes 20a adjacent to each other in the horizontal direction, and further, the common wiring 16 is coated with a water- and oil-repellent liquid-repellent conductive film 58. The PEDOT-containing liquid applied to the transparent anode electrode 20a does not leak to the adjacent transparent anode electrode 20a. As shown in FIGS. 34B and 34C, the hole injection layer 20h is not formed for the gate wiring terminal portion and the drain wiring terminal portion.

  Next, as a fifteenth step, a light emitting layer forming step corresponding to the fourteenth step in the first embodiment is performed. That is, in this light emitting layer forming step, an interlayer is applied and dried by a wet coating method as necessary, and then an organic compound of a polyfluorene-based light emitting material is applied and dried as shown in FIG. The light emitting layer 20e is patterned by a wet coating method. As described above, since the thick common wiring 16 is provided between the transparent anode electrodes 20a adjacent to each other in the horizontal direction, the common wiring 16 is further coated with a water- and oil-repellent liquid-repellent conductive film 58. Therefore, the organic compound-containing liquid applied to the transparent anode electrode 20a does not leak to the adjacent transparent anode electrode 20a. Further, since the organic compound-containing liquid applied to the transparent anode electrode 20a does not thicken around the transparent anode electrode 20a due to the water and oil repellency of the liquid repellent conductive film 58, the light emitting layer 20e is formed with a uniform film thickness. Can be membrane. As for the gate wiring terminal portion and the drain wiring terminal portion, as shown in FIGS. 35B and 35C, the light emitting layer 20e is not formed.

  Next, as a sixteenth step, a cathode electrode forming step corresponding to the fifteenth step in the first embodiment is performed. That is, in this cathode electrode forming step, an electron injection layer such as barium or calcium is deposited on the light emitting layer 20e as necessary, and then the transparent cathode electrode 20c is formed by sputtering as shown in FIG. A film is formed on one surface through a metal mask. Since the light emitting layer 20e is very sensitive to temperature, the deposition of the electron injection layer and the sputtering of the transparent cathode electrode 20c do not increase the temperature so as not to damage the light emitting layer 20e (about 100 degrees). It is necessary to carry out with. Then, by patterning the transparent cathode electrode 20c thus formed using a metal mask, as shown in FIGS. 36 (B) and 36 (C), the transparent cathode electrode 20c is turned from the gate wiring terminal portion and the drain wiring terminal portion to the transparent cathode. The electrode 20c is removed.

  Next, as a seventeenth process, a sealing insulating film forming process corresponding to the sixteenth process in the first embodiment is performed. That is, in this sealing insulating film forming step, the sealing insulating thin film 60 is formed on one surface through a metal mask by vapor deposition, as shown in FIGS. 25A to 25C. The stop insulating thin film 60 is patterned.

  The organic EL display panel 10 is completed through the above steps.

  According to the second embodiment as described above, in the top emission type organic EL display panel 10 using the organic EL element as the light emitting element, the transparent anode electrode 20a is provided with the reflective layer 50 made of chromium, silver, or a silver alloy. The reflective layer 50 is formed so as to completely cover the region where the anode auxiliary layer 64 is exposed in the contact hole 52 portion, so that the transparent anode is formed in the contact hole 52 portion. Even if pinholes are opened in the electrode 20a, the combination of the transparent anode electrode 20a (for example, ITO) and the reflective layer 50 (for example, chromium) does not advance the battery reaction in the resist stripping solution, so a contact portion is formed with high yield. it can. Furthermore, if silver or a silver alloy is selected as the material of the reflective layer 50, the battery reaction in the resist stripping solution can be similarly suppressed, and the reflectance is higher than that of chromium, so that a favorable reflective layer can be formed. .

Further, in the gate wiring terminal portion which is a terminal for connecting the signal lines Y _{1 to} Y _n to the external circuit of the organic EL display panel 10, a gate which is a conductive film which is the source of the signal lines Y _{1 to} Y _n A drain wiring layer 42 is formed on the wiring layer 40 via the adhesion layer 36, and an anode auxiliary layer 64 is formed on the drain wiring layer 42 via the adhesion layer 62. The reflective layer 50 is formed so as to completely cover the region where the 64 is exposed, and the transparent anode electrode 20a is formed so as to completely cover the reflective layer 50. However, similarly to the contact hole 52, even if a pinhole is opened in the transparent anode electrode 20a, the battery reaction does not proceed in the resist stripping solution, so that the terminal portion can be formed with high yield.

Similarly, with regard drain wiring terminal portion is a terminal for connecting the scan lines _X 1 to X _m and the power supply wiring 14 to an external circuit of the organic EL display panel 10, scan lines _X 1 to X _m and the feed interconnection 14 An anode auxiliary layer 64 is formed on the drain wiring layer 42, which is a conductive film serving as a base of the film, via the adhesion layer 62, and is reflected so as to completely cover the region where the anode auxiliary layer 64 is exposed. Since the layer 50 is formed and the transparent anode electrode 20a is formed so as to completely cover the reflective layer 50, even in the drain wiring terminal portion, even if a pinhole is opened in the transparent anode electrode 20a. Since the battery reaction does not proceed in the resist stripping solution, the terminal portion can be formed with high yield.

  Moreover, since the protective layer by the transparent anode electrode 20a is provided on the reflective layer 50, there can exist an effect similar to the said 1st Embodiment. Furthermore, the effect of the configuration in which the end surface of the reflective layer 50 is entirely covered with the transparent anode electrode 20a such as ITO is the same as that in the first embodiment.

[Third Embodiment]
Next, a third embodiment of a display panel using the light emitting device of the present invention will be described. In addition, the organic EL display panel 10 in this embodiment is also a top emission type display panel using an organic EL element as a light emitting element, as in the second embodiment. Here, parts similar to those of the second embodiment are given the same reference numerals, and descriptions thereof are omitted.

FIG. 37 is a plan view mainly showing electrodes of the pixel circuits _{Pi, j} in the organic EL display panel 10 of the active matrix driving system according to the present embodiment. In order to make the drawing easier to see, in FIG. 37, illustration of electrodes on the lower layer side of the pixel circuit _{Pi, j} is omitted. 38A is a cross-sectional view taken along the line AA of the pixel circuit portion shown in FIG. 37, and FIG. 38B is a cross-sectional view of the gate wiring terminal portion which is the terminal 18U. C) is a cross-sectional view of the drain wiring terminal portion which is the terminals 18L and 18R. Note that the cross-sectional view taken along the line DD of the pixel circuit portion shown in FIG. 37 is the same as FIG.

  That is, in the present embodiment, as shown in FIGS. 37 and 38A to 38C, a simple partition 66 is formed instead of the common wiring 16 that also functions as a partition that partitions the organic EL element 20. It is what I did. In this case, the partition 66 is formed directly on the interlayer insulating film 54, and the transparent cathode electrode 20 c is formed on the surface of the partition 66.

  Next, a method for manufacturing the EL display panel 10 in the present embodiment will be described. FIGS. 39A to 42A are cross-sectional views at each step in the pixel circuit portion as shown in FIG. 38A. Similarly, FIGS. 39B to 42B are shown. ) Is a gate wiring terminal portion as shown in FIG. 38B, and FIGS. 39C to 42C are cross-sectional views at each step in the drain wiring terminal portion as shown in FIG. 38C. Is shown.

  In the present embodiment, the first embodiment described with reference to FIGS. 8A, 8B, and 13C to 13A, 13B, and 13C in the first embodiment is used. Steps (gate formation step) to sixth step (interlayer insulating film formation step), and the subsequent steps shown in FIGS. 27A, 27B, 27C to 31A in the second embodiment. The seventh step (anode auxiliary layer forming step) to the eleventh step (interlayer insulating film forming step) as described with reference to (B) and (C) are performed.

  Thereafter, in the present embodiment, a partition wall forming step is performed as a twelfth step. That is, in this partition wall forming step, first, a partition wall material is applied, and the partition wall material is dried to form a partition wall material on the entire surface. Then, as shown in FIGS. 39A to 39C, after the partition wall material is left only between the transparent anode electrodes 20a adjacent to each other in the horizontal direction by an exposure development method, the partition wall is formed by a post-bake (heat treatment) method. The material is cured to form the partition 66.

  Next, a hydrophilization process is implemented as a 13th process. That is, in the present embodiment, a hydrophilic treatment is performed on the transparent anode electrode 20a.

  Thereafter, as a fourteenth step, a hole injection layer forming step corresponding to the fourteenth step in the second embodiment is performed. That is, in this hole injection layer forming step, as shown in FIG. 40A, the hole injection layer 20h is patterned by a wet coating method in which PEDOT is applied and dried. Since the thick partition wall 66 is provided between the transparent anode electrodes 20a adjacent in the horizontal direction, the PEDOT-containing liquid applied to the transparent anode electrode 20a does not leak to the adjacent transparent anode electrode 20a. Note that as shown in FIGS. 40B and 40C, the hole injection layer 20h is not formed in the gate wiring terminal portion and the drain wiring terminal portion.

  Next, as a fifteenth step, a light emitting layer forming step corresponding to the fifteenth step in the second embodiment is performed. That is, in this light emitting layer forming step, the interlayer is applied and dried by a wet coating method as necessary, and then an organic compound of a polyfluorene-based light emitting material is applied and dried as shown in FIG. The light emitting layer 20e is patterned by a wet coating method. As described above, since the thick partition wall 66 is provided between the transparent anode electrodes 20a adjacent in the horizontal direction, the organic compound-containing liquid applied to the transparent anode electrode 20a leaks to the adjacent transparent anode electrode 20a. There is no. As for the gate wiring terminal portion and the drain wiring terminal portion, as shown in FIGS. 41B and 41C, the light emitting layer 20e is not formed.

  Next, as a sixteenth step, a cathode electrode forming step corresponding to the sixteenth step in the second embodiment is performed. That is, in this cathode electrode formation step, first, if necessary, an electron injection layer such as barium or calcium is deposited on the light emitting layer 20e, and then the transparent cathode electrode is formed by sputtering as shown in FIG. 20c is formed on one surface through a metal mask. Since the light emitting layer 20e is very sensitive to temperature, the deposition of the electron injection layer and the sputtering of the transparent cathode electrode 20c do not increase the temperature so as not to damage the light emitting layer 20e (about 100 degrees). It is necessary to carry out with. Then, by patterning the transparent cathode electrode 20c thus formed using a metal mask, as shown in FIGS. 42B and 42C, the transparent cathode electrode 20c is formed from the gate wiring terminal portion and the drain wiring terminal portion. The electrode 20c is removed.

  Next, as a seventeenth step, a sealing insulating film forming step corresponding to the seventeenth step in the second embodiment is performed. That is, in this sealing insulating film forming step, the sealing insulating thin film 60 is formed on one surface through a metal mask by vapor deposition, as shown in FIGS. 38 (A) to (C). The stop insulating thin film 60 is patterned.

  The organic EL display panel 10 is completed through the above steps.

  According to the third embodiment, the same effect as that of the second embodiment can be obtained.

  In the first embodiment as well, the partition 66 can be formed instead of the common wiring 16 as in the third embodiment.

  The present invention has been described above based on the embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications and applications are possible within the scope of the gist of the present invention. .

  For example, in the above embodiment, the organic EL element is described as an example of the light emitting element, but other light emitting elements may be used.

  Further, the circuit configuration of the pixel circuit is not limited to the example shown in FIG.

  Further, the organic planarization film 46 may not be provided around the gate wiring terminal portion and the drain wiring terminal portion.

  Further, since the contact hole 52 has a hole, it is not flush with the pixel portion. Therefore, when the contact hole 52 is out of the common wiring 16 or the partition wall 66 in plan view, it is difficult to form the organic EL layers (the hole injection layer 20h and the light emitting layer 20e) uniformly. Therefore, it is more effective to form the contact hole 52 so as to be hidden under the common wiring 16 or the partition wall 66 in plan view.

FIG. 1 is a schematic view of an active matrix driving type organic EL display panel according to a first embodiment of a display panel using a light emitting element of the present invention. FIG. 2 is a plan view of the organic EL display panel according to the first embodiment. FIG. 3 is an equivalent circuit diagram of a pixel circuit in the organic EL display panel according to the first embodiment. FIG. 4 is a plan view showing electrodes of the pixel circuit of the organic EL display panel according to the first embodiment. FIG. 5 is a plan view showing electrodes of the pixel circuit of the organic EL display panel according to the first embodiment. 6A is a cross-sectional view taken along line AA of the pixel circuit portion shown in FIGS. 4 and 5 in the organic EL display panel according to the first embodiment, and FIG. 6B is the same figure. 6 is a cross-sectional view taken along the line BB of the gate wiring terminal portion shown in FIG. 2, and FIG. 6C is a cross-sectional view taken along the line CC of the drain wiring terminal portion shown in FIG. It is. FIG. 7 is a cross-sectional view taken along line DD of the pixel circuit portion illustrated in FIGS. 4 and 5 in the organic EL display panel according to the first embodiment. FIG. 8A is a cross-sectional view of the pixel circuit portion in the gate forming step as the first step in the method for manufacturing the organic EL display panel according to the first embodiment, and FIG. FIG. 8C is a cross-sectional view of the drain wiring terminal portion. FIG. 9A is a cross-sectional view of the pixel circuit portion in the channel protective film forming step as the second step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.9 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 10A is a cross-sectional view of the pixel circuit portion in the source / drain forming step as the third step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.10 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 11A is a cross-sectional view of the pixel circuit portion in the gate insulating film contact forming step as the fourth step in the method for manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a gate wiring terminal part, FIG.11 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 12A is a cross-sectional view of the pixel circuit portion in the drain wiring layer forming step as the fifth step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.12 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 13A is a cross-sectional view of the pixel circuit portion in the interlayer insulating film forming step as the sixth step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.13 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 14A is a cross-sectional view of the pixel circuit portion in the organic planarization film forming step as the seventh step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a gate wiring terminal part, FIG.14 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 15A is a cross-sectional view of the pixel circuit portion in the reflective layer forming step as the eighth step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a terminal part, FIG.15 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 16A is a cross-sectional view of the pixel circuit portion in the transparent anode electrode forming step as the ninth step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.16 (C) is sectional drawing of a drain wiring terminal part similarly. 17A is a cross-sectional view of the pixel circuit portion in the interlayer insulating film forming step as the tenth step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.17 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 18A is a cross-sectional view of the pixel circuit portion in the common wiring forming step as the eleventh step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a terminal part, FIG.18 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 19A is a cross-sectional view of a pixel circuit portion in a hydrophilic / water-repellent step as a twelfth step in the method of manufacturing an organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.19 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 20A is a cross-sectional view of the pixel circuit portion in the hole injection layer forming step as the thirteenth step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a gate wiring terminal part, FIG.20 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 21A is a cross-sectional view of the pixel circuit portion in the light emitting layer forming step as the fourteenth step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a terminal part, FIG.21 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 22A is a cross-sectional view of the pixel circuit portion in the cathode electrode forming step as the fifteenth step in the method of manufacturing the organic EL display panel according to the first embodiment, and FIG. It is sectional drawing of a terminal part, FIG.22 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 23 is a plan view showing electrodes of a pixel circuit of an organic EL display panel according to a second embodiment of the display panel using the light emitting element of the present invention. FIG. 24 is a plan view showing electrodes of a pixel circuit of the organic EL display panel according to the second embodiment. FIG. 25A is a cross-sectional view taken along the line AA of the pixel circuit portion shown in FIGS. 23 and 24 in the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.25 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 26 is a cross-sectional view taken along the line DD of the pixel circuit portion shown in FIGS. 23 and 24 in the organic EL display panel according to the second embodiment. FIG. 27A is a cross-sectional view of the pixel circuit portion in the anode auxiliary layer forming step as the seventh step in the method of manufacturing the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.27 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 28A is a cross-sectional view of the pixel circuit portion in the organic planarization film forming step as the eighth step in the method of manufacturing the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a gate wiring terminal part, FIG.28 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 29A is a cross-sectional view of the pixel circuit portion in the reflective layer forming step as the ninth step in the method of manufacturing the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a terminal part, FIG.29 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 30A is a cross-sectional view of the pixel circuit part in the transparent anode electrode forming step as the tenth step in the method of manufacturing the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.30 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 31A is a cross-sectional view of the pixel circuit portion in the interlayer insulating film forming step as the eleventh step in the method of manufacturing the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.31 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 32A is a cross-sectional view of the pixel circuit portion in the common wiring forming step as the twelfth step in the method of manufacturing the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a terminal part, FIG.32 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 33A is a cross-sectional view of a pixel circuit portion in a hydrophilic / water-repellent step as a thirteenth step in the method for manufacturing an organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a wiring terminal part, FIG.33 (C) is sectional drawing of a drain wiring terminal part similarly. 34A is a cross-sectional view of the pixel circuit portion in the hole injection layer forming step as the fourteenth step in the method of manufacturing the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a gate wiring terminal part, FIG.34 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 35A is a cross-sectional view of the pixel circuit portion in the light emitting layer forming step as the fifteenth step in the method of manufacturing the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a terminal part, FIG.35 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 36A is a cross-sectional view of the pixel circuit portion in the cathode electrode forming step as the sixteenth step in the method of manufacturing the organic EL display panel according to the second embodiment, and FIG. It is sectional drawing of a terminal part, FIG.36 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 37 is a plan view showing electrodes of a pixel circuit of an organic EL display panel according to a third embodiment of a display panel using the light emitting element of the present invention. 38A is a cross-sectional view taken along line AA of the pixel circuit portion shown in FIG. 37 in the organic EL display panel according to the third embodiment, and FIG. 38B is a gate wiring terminal portion. FIG. 38C is a sectional view of the drain wiring terminal portion. FIG. 39A is a cross-sectional view of the pixel circuit portion in the partition forming step as the twelfth step in the method of manufacturing the organic EL display panel according to the third embodiment, and FIG. FIG. 39C is a cross-sectional view of the drain wiring terminal portion. FIG. 40A is a cross-sectional view of the pixel circuit portion in the hole injection layer forming step as the fourteenth step in the method of manufacturing the organic EL display panel according to the third embodiment, and FIG. It is sectional drawing of a gate wiring terminal part, FIG.40 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 41A is a cross-sectional view of the pixel circuit portion in the light emitting layer forming step as the fifteenth step in the method of manufacturing the organic EL display panel according to the third embodiment, and FIG. It is sectional drawing of a terminal part, FIG.41 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 42A is a cross-sectional view of the pixel circuit portion in the cathode electrode forming step as the sixteenth step in the method of manufacturing the organic EL display panel according to the third embodiment, and FIG. It is sectional drawing of a terminal part, FIG.42 (C) is sectional drawing of a drain wiring terminal part similarly. FIG. 43 is a diagram showing a case where an ITO electrode is laminated on an aluminum-based electrode formed on an insulating underlayer, and the ITO electrode is in contact with a resist stripping solution in a state where a pinhole is opened. . FIG. 44A is a diagram for explaining a battery reaction at a pinhole portion, and FIG. 44B is a diagram showing a state in which an aluminum-based electrode is disconnected as a result of the battery reaction.

Explanation of symbols

    DESCRIPTION OF SYMBOLS 10 ... EL display panel, 12 ... Insulating substrate, 14 ... Power supply wiring, 16 ... Common wiring, 18L, 18R, 18U ... Terminal, 20 ... EL element, 20a ... Transparent anode electrode, 20c ... Transparent cathode electrode, 20e ... Light emitting layer 20h ... hole injection layer, 22F, 22B ... routing wiring, 24 ... wiring terminal, 26 ... switch transistor, 28 ... holding transistor, 30 ... drive transistor, 30s ... source, 30g ... gate, 30d ... drain, 30A ... semiconductor Film, 30B ... channel protective film, 30C ... impurity semiconductor film, 32 ... capacitor, 32A ... electrode, 32B ... electrode, 34 ... gate insulating film, 36, 62 ... adhesion layer, 38, 41, 43, 52 ... contact hole, 40 ... Gate wiring layer, 42 ... Drain wiring layer, 44, 4 6 ... Organic planarization film, 46 '... Organic planarization film opening, 48 ... Transistor array substrate, 50 ... Reflective layer, 54 ... Interlayer insulation film, 54' ... Insulation film opening, 56 ... Adhesion layer, 58 ... Liquid repellency Conductive film, 60: sealing insulating thin film, 63: anode power supply wiring, 64: anode auxiliary layer, 66: partition.

Claims (12)

A display panel in which light emitting elements having a laminated structure of a transparent pixel electrode, a light emitting layer, and a transparent counter electrode are arranged in a matrix,
A substrate,
On the substrate, a plurality of transistors provided for each of the light emitting elements, for driving the light emitting elements,
A wiring layer for supplying a signal or a power supply voltage to the plurality of transistors on the substrate;
An insulating film formed to cover the plurality of transistors and the wiring layer;
A conductive reflective layer formed on the insulating film corresponding to the arrangement of the light emitting elements;
A pixel electrode of the light emitting element formed on the reflective layer;
A wiring terminal portion having an opening formed in the insulating film until reaching the wiring layer, for connecting the wiring layer to the outside;
Comprising
In the wiring terminal portion, a laminated structure of the pixel electrode and the reflective layer is formed to extend to the inside of the opening formed in the insulating film, and externally through the laminated structure of the pixel electrode and the reflective layer. A display panel using a light emitting element characterized in that it is electrically connected to the display. The reflective layer also functions as a battery reaction preventing layer that prevents a battery reaction between the pixel electrode and the wiring layer inside the opening formed in the insulating film of the wiring terminal portion. The display panel according to claim 1, wherein the display panel is a display panel. The display panel according to claim 2, wherein the reflective layer is made of at least one of chromium, silver, and a silver alloy. The pixel electrode covers the entire surface of the reflective layer, and the reflective layer covers the entire surface of the wiring layer exposed inside the opening formed in the insulating film of the wiring terminal portion. The display panel according to claim 1. A display panel in which light emitting elements having a laminated structure of a transparent pixel electrode, a light emitting layer, and a transparent counter electrode are arranged in a matrix,
A substrate,
On the substrate, a plurality of transistors provided for each of the light emitting elements, for driving the light emitting elements,
A wiring layer for supplying a signal or a power supply voltage to the plurality of transistors on the substrate;
An insulating film formed to cover the plurality of transistors and the wiring layer;
A conductive reflective layer formed on the insulating film corresponding to the arrangement of the light emitting elements;
A pixel electrode of the light emitting element formed on the reflective film;
A wiring terminal portion having an opening formed in the insulating film until reaching the wiring layer, for connecting the wiring layer to the outside;
A conductive auxiliary layer formed so as to cover the entire surface of the wiring layer exposed inside the opening formed in the insulating film of the wiring terminal portion;
Comprising
In the wiring terminal portion, a laminated structure of the pixel electrode and the reflective layer is formed to extend over the auxiliary layer in the opening formed in the insulating film, and the laminated structure of the pixel electrode and the reflective layer is interposed therebetween. A display panel using a light-emitting element characterized by being electrically connected to the outside. The reflective layer also functions as a battery reaction preventing layer that prevents a battery reaction between the pixel electrode and the wiring layer inside the opening formed in the insulating film of the wiring terminal portion. The display panel according to claim 5, wherein the display panel is a display panel. The display panel according to claim 6, wherein the reflective layer is made of at least one of chromium, silver, and a silver alloy. The pixel electrode covers the entire surface of the reflective layer, and the reflective layer covers the entire surface of the auxiliary layer exposed inside the opening formed in the insulating film of the wiring terminal portion. The display panel according to claim 5. The display panel according to claim 1, wherein the light emitting element is an organic EL element. A method of manufacturing a display panel in which light emitting elements having a laminated structure of a transparent pixel electrode, a light emitting layer, and a transparent counter electrode are arranged in a matrix,
Forming a plurality of transistors for driving the light emitting element on a substrate;
Forming a wiring layer on the substrate for supplying a signal or a power supply voltage to the plurality of transistors;
Forming an insulating film covering the plurality of transistors and the wiring layer;
A step of forming an opening to reach the wiring layer in a wiring terminal portion for connecting the wiring layer to the outside in the insulating film;
Corresponding to the arrangement of the light emitting elements, forming a conductive reflective layer on the insulating film;
Forming a pixel electrode of the light emitting element on the reflective film;
Forming a light emitting layer of the light emitting element on the pixel electrode of the light emitting element;
Forming a counter electrode of the light emitting element on the light emitting layer of the light emitting element;
Comprising
In the wiring terminal portion, the step of forming the reflective layer and the step of forming the pixel electrode are such that the laminated structure of the reflective layer and the pixel electrode extends into the opening formed in the insulating film. A method of manufacturing a display panel using a light emitting element, wherein the reflective layer and the pixel electrode are formed so as to be electrically connected to the outside through a laminated structure of the pixel electrode and the reflective layer. A method of manufacturing a display panel in which light emitting elements having a laminated structure of a transparent pixel electrode, a light emitting layer, and a transparent counter electrode are arranged in a matrix,
Forming a plurality of transistors for driving the light emitting element on a substrate;
Forming a wiring layer on the substrate for supplying a signal or a power supply voltage to the plurality of transistors;
Forming an insulating film covering the plurality of transistors and the wiring layer;
A step of forming an opening to reach the wiring layer in a wiring terminal portion for connecting the wiring layer to the outside in the insulating film;
Forming a conductive auxiliary layer so as to cover the entire surface of the wiring layer exposed inside the opening formed in the insulating film of the wiring terminal portion;
Corresponding to the arrangement of the light emitting elements, forming a conductive reflective layer on the insulating film;
Forming a pixel electrode of the light emitting element on the reflective film;
Forming a light emitting layer of the light emitting element on the pixel electrode of the light emitting element;
Forming a counter electrode of the light emitting element on the light emitting layer of the light emitting element;
Comprising
In the wiring terminal portion, the step of forming the reflective layer and the step of forming the pixel electrode extend over the auxiliary layer in the opening formed in the insulating film in the laminated structure of the reflective layer and the pixel electrode. Manufacturing of a display panel using a light emitting element, wherein the reflective layer and the pixel electrode are formed so as to be electrically connected to the outside through a laminated structure of the pixel electrode and the reflective layer Method. The method for manufacturing a display panel according to claim 10, wherein the light emitting element is an organic EL element.

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