JP2008003820A - Nonvolatile storage device and adapter device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid various problems such as a decrease in reliability of read data caused by heat generation resulting from high speed operation, risk of burns, etc. <P>SOLUTION: A nonvolatile storage device 120 is designed to be able to achieve the fastest speed. Further, the nonvolatile storage device 120 is provided with an adapter device installation detecting part 122 and a data transfer speed control part 131. A memory controller 130 is permitted to operate at high speed only if attached to an adapter device 110 that is more effective in dissipating heat than the nonvolatile storage device 120; the operating speed of the memory controller is kept low when the adapter device 110 is not installed. In this way it is possible to avoid risks such as decrease in reliability of read data caused by heat generation that increases in proportion to the operating speed, and burns during the handling of the nonvolatile storage device 120. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device such as a semiconductor memory card provided with a nonvolatile memory, and an adapter device to which the nonvolatile memory device is attached and used.

  The demand for nonvolatile memory devices including a rewritable nonvolatile memory is increasing, especially for semiconductor memory cards. Although semiconductor memory cards are somewhat more expensive than optical discs and tape media, they are portable, such as digital still cameras and mobile phones, due to their merits such as small size, light weight, earthquake resistance, and ease of handling. The demand for the recording medium of equipment has increased, and recently it has come to be used as a recording medium for consumer video recording equipment and professional video recording equipment for broadcasting stations. Furthermore, not only portable devices but also stationary devices such as digital TVs and DVD recorders are equipped with a slot for a semiconductor memory card as a standard feature. You can view still images taken with a digital still camera on a digital TV, or a consumer video. It has become possible to dubb videos recorded with a recording device to a DVD recorder.

  This semiconductor memory card includes a flash memory as a nonvolatile main memory, and has a memory controller for controlling the flash memory. The memory controller performs read / write control on the flash memory in response to a read / write instruction from an access device such as a digital still camera body.

  In recent years, there is a growing need for further increase in the capacity of semiconductor memory cards in order to cope with higher quality of AV contents such as still images and moving images, that is, higher capacity. As a result, when dubbing AV content recorded on a semiconductor memory card to a recording medium such as a hard disk recorder or a DVD recorder built in a hard disk recorder or personal computer (PC), data can be read from the semiconductor memory card at a higher speed. Has come to be required. In addition, when dubbing AV content recorded on a recording medium such as a hard disk onto a semiconductor memory card, it has been demanded that data can be written to the semiconductor memory card at a higher speed. That is, it will become important in the future to shorten the waiting time of the user by high-speed dubbing the recorded data between the recording media.

  Prior arts related to high-speed transfer of data in a semiconductor memory card include, for example, those related to parallel access of a flash memory as shown in Patent Document 1, and high-speed buses connecting a semiconductor memory card and an access device as shown in Patent Document 2. Technology.

By applying the techniques disclosed in these documents, it is possible to read data from the semiconductor memory card at high speed or write data to the semiconductor memory card at high speed. For example, an SD (Secure Digital) memory card has a transfer speed of 25 MBps according to the standard, but the above-described technology will enable high-speed access of 100 MBps or more in the future.
JP 2000-510634 Gazette JP 2003-223623 A

  However, if the reading / writing is performed at a very high speed, the amount of heat generated in the flash memory becomes very large, and in particular, there arises a problem in terms of reliability such that the read data changes.

  In addition, since the semiconductor memory card has a small surface area and it is difficult for heat to escape to the surroundings, there is a possibility of burns depending on the structure of the host device and the amount of heat generated by the flash memory.

  Therefore, in view of the above problems, the present invention uses a nonvolatile storage device that can be safely handled without deteriorating the reliability of the read data while retaining the features of a small size, and the nonvolatile storage device is mounted and used. An object of the present invention is to provide an adapter device.

  In order to achieve the above object, the present invention takes the following technical means.

  That is, the technical means in the present invention is a non-volatile storage device that reads and writes data in accordance with an external access instruction, and includes a non-volatile memory and an adapter that detects whether or not the mounting destination is an adapter device A device mounting detection unit; and a data transfer rate limiting unit that limits a data transfer rate related to reading and writing of data. The data transfer rate limiting unit is configured so that the adapter mounting detection unit is mounted on the adapter device. If not detected, the data transfer rate is limited to a predetermined value or less.

  The data transfer rate limiting unit preferably limits the data transfer rate based on a previously stored speed limit parameter.

  More preferably, it further includes an external notification unit, and the external notification unit notifies the outside whether or not the data transfer rate control unit limits the data transfer rate, or information related to the limitation of the data transfer rate. Good.

  The technical means in the present invention is an adapter device used intervening between a nonvolatile memory device having at least a nonvolatile memory and an access device for reading and writing the nonvolatile memory device, A non-volatile storage device mounting detection unit that detects whether or not a non-volatile storage device is mounted, and a data transfer rate limit that limits a data transfer rate related to reading and writing of data in the non-volatile storage device. A data transfer rate restriction instructing unit that instructs the device, and the data transfer rate restriction instructing unit receives data when the non-volatile storage device attachment detection unit does not detect attachment of the non-volatile storage device. An instruction is given to limit the transfer rate to a predetermined value or less.

  The adapter device preferably has a surface area wider than the surface area of the nonvolatile memory device.

  Moreover, it is preferable that the said adapter apparatus has a part shape | molded by the high heat conductive material at least.

  Moreover, it is preferable that the said adapter apparatus is provided with the heat radiating member.

  More preferably, the adapter device preferably includes a cooling device.

  According to the present invention, when the nonvolatile memory device is not attached to the adapter device, that is, the structure having a larger surface area than the nonvolatile memory device, the data transfer rate is limited to a predetermined value or less, in other words, the adapter device. The data transfer speed is not limited when the adapter is installed. Therefore, when the adapter device is installed, the heat of the nonvolatile memory device is released by the adapter device, and the reliability of the read data can be improved even in high-speed data transfer. Risks such as decline and burns can be avoided. Further, when the adapter device is not attached, that is, when the nonvolatile storage device is used alone, high-speed data transfer is prohibited, and the risk of data reliability deterioration and burns can be avoided. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a method for implementing a nonvolatile memory system according to Embodiment 1 of the present invention. In FIG. 1, the nonvolatile storage system includes an access device 100, an adapter device 110, and a nonvolatile storage device 120.

  The access device 100 includes a card interface 101 and an access control unit 102. An insertion port 109 is provided on the right side surface of the access device 100, and the terminal portion 113 provided in the adapter device 110 is inserted into the insertion port 109 for use. Alternatively, the nonvolatile storage device 120 may be inserted and used. A card interface 101 is provided in the back of the insertion port 109, and data is transmitted and received between the adapter device 110 and the nonvolatile storage device 120 via nine terminals (terminals 1 to 9) arranged in the card interface 101. I do. Note that the specifications of the nine terminals (terminals 1 to 9) are the same as, for example, the specifications of the SD memory card, and the description thereof is omitted.

  The adapter device 110 includes a housing portion 112 and a terminal portion 113, an insertion port 119 is provided on the right side surface of the housing portion 112, and a power supply terminal 111 is provided on the upper side surface inside the housing portion 112. Power is supplied through the card interface terminal 4 in the housing 112. Terminal portion 113 is inserted in a state of being in close contact with the inner surface of insertion port 109 of access device 100. Note that a mechanism for preventing the terminal portion 113 from being easily removed from the insertion port 109 can be realized by using a generally known technique, and thus description thereof is omitted.

  The nonvolatile storage device 120 includes a memory controller 130, a nonvolatile memory group 140, an adapter device attachment detection contact 121, and an adapter device attachment detection unit 122. The nonvolatile storage device 120 is provided with nine terminals (terminals 1 to 9) similarly to the access device 100 and the adapter device 110, and is connected to the memory controller 130. An adapter device attachment detection contact 121 is provided on the upper side surface of the nonvolatile memory device 120, and the adapter device attachment detection contact 121 is a power source when the nonvolatile memory device 120 is inserted into the insertion port 119 of the adapter device 110. Power is supplied from the terminal 111. The adapter device attachment detection contact 121 is connected to an adapter device attachment detection unit 122 provided inside the nonvolatile storage device 120, and information detected by the adapter device attachment detection unit 122, that is, the nonvolatile storage device 120 is an adapter. Information about whether or not the device is attached to the device 110 is notified to the memory controller 130.

  FIG. 2 is a block diagram illustrating a configuration of the nonvolatile storage device 120. The nonvolatile storage device 120 includes an adapter device attachment detection unit 122, a memory controller 130, and a nonvolatile memory group 140.

  The adapter device attachment detection unit 122 is a circuit in which the adapter device attachment detection contact 121, the resistor 202, and the ground 203 are connected in series. When the nonvolatile memory device 120 is attached to the adapter device 110, the adapter device attachment detection unit 122 The power supply 201 is supplied via the adapter device attachment detection contact 121, and the voltage level of the data transfer speed control terminal 150 is switched from "Low" to "High".

  The memory controller 130 includes a host interface 210, buffer RAMs 220 to 227, a read / write control unit 230, an address management unit 240, a data transfer rate control unit 131, and an external notification unit 133.

  The host interface 210 is a block that communicates with the access device 100 via terminals 1-9. As will be described later, when reading and writing in the high-speed mode, the adapter device 110 is inserted between the host interface 210 and the access device 100. The buffer RAMs 220 to 227 are blocks that temporarily hold data written from the access device 100 or data read from the nonvolatile memory group 140, each having a size of 4 kbytes, and cyclically descending from the buffer RAM 220. used. The address management unit 240 is a block that converts a logical address transferred with the access of the access device 100 into a physical address of the nonvolatile memory group 140 and manages a recording state of the nonvolatile memory group 140. Note that the address management method can be realized by using a general technique, and thus the description thereof is omitted.

  The read / write controller 230 writes data temporarily stored in the buffer RAMs 220 to 227 to the nonvolatile memory group 140 or reads data from the nonvolatile memory group 140 based on the physical address designated by the address manager 240. It is a block to do. The nonvolatile memory group 140 includes eight nonvolatile memories 260 to 267, and the capacity of each nonvolatile memory is 1 Gbyte. Each nonvolatile memory is connected to the read / write control unit 230 via an 8-bit I / O bus, and is further connected to the data transfer rate control unit 131 via an RB signal line (1 bit each). The data transfer speed control unit 131 includes a speed limit parameter storage unit 132 therein, and the speed limit parameter storage unit 132 is configured by a ROM or the like that stores speed limit parameters in advance.

  FIG. 3 is an explanatory diagram showing the configuration of any one of the nonvolatile memories 260 to 267. In the present embodiment, a multi-value NAND flash memory, which is expected to become the mainstream in the future as a nonvolatile memory, is assumed. In FIG. 3, nonvolatile memories 260 to 267 include a memory cell array 300, I / O registers 310 and 320, and a peripheral circuit 330. The memory cell array 300 is divided into two districts (hereinafter referred to as D1 and D0), and each district has 2048 physical blocks, and each physical block has 128 pages. Data transferred via the I / O bus can be simultaneously written to any page in D0 and any page in D1 via I / O registers 310 and 320, respectively. It is also possible to simultaneously read from any page in D0 and any page in D1.

  FIG. 4 is a flowchart showing the processing contents of the data transfer rate control unit 131. Details will be described later.

  FIG. 5 is a time chart showing the reading process in the high-speed mode. In FIG. 5, the uppermost row represents a state in which the access device 100 reads data from the buffer RAMs 220 to 227. The buffer RAMs 220 to 227 are sequentially used such that the leftmost frame corresponds to the buffer RAM 220, the right neighbor is the buffer RAM 221, and the right neighbor is the buffer RAM 222. Note that the right side of the buffer RAM 227 returns to the buffer RAM 220. The time required for reading data from each buffer RAM of the access device 100 is 40 μS per 4 kbytes.

  FIG. 6 is a time chart showing the reading process in the normal mode. The buffer RAMs 220 to 227 are the same as those in FIG.

  FIG. 7 is a time chart showing the writing process in the high-speed mode. In FIG. 7, the uppermost row represents a state in which the access device 100 writes data to the buffer RAMs 220 to 227. The buffer RAMs 220 to 227 are sequentially used such that the leftmost frame corresponds to the buffer RAM 220, the right neighbor is the buffer RAM 221, and the right neighbor is the buffer RAM 222. Note that the right side of the buffer RAM 227 returns to the buffer RAM 220. In addition, the time required for writing data to each buffer RAM of the access device 100 is 40 μS per 4 kbytes.

  FIG. 8 is a time chart showing the writing process in the normal mode.

  FIG. 9 is an external view of the adapter device. 9A is an external view of an adapter device including a housing portion 112 having a sufficiently larger surface area than the nonvolatile memory device 120. FIG. FIG. 5B is an external view of an adapter device including a small casing 900 formed of a high heat conductive member and a terminal 910 formed of a high heat conductive member. FIG. 6C is an external view of an adapter device in which a heat radiating member 920 is bonded to a small casing 920.

Regarding the nonvolatile storage system according to the first embodiment of the present invention configured as described above, data is read out separately for each case where the adapter device 110 is attached to the nonvolatile storage device 120 and when the adapter device 110 is not attached. The description will be divided into writing. For the contents that are not directly related to the present invention, for example, system information to be stored in a part of the non-volatile memory group 140, detailed operation of the address management unit 240, etc. are omitted for the sake of simplicity. To do.
[When adapter device 110 is mounted]
In FIG. 1, the nonvolatile storage device 120 is inserted into the insertion port 119 of the adapter device 110, and is inserted into the insertion port 109 of the access device 100 while being attached to the adapter device 110. Is electrically connected to the access device 100 via the card interface 101. At this time, the power supply terminal 111 installed in the adapter device 110 and the adapter device attachment detection contact 121 installed on the upper surface of the nonvolatile memory device 120 are connected.

  Thereafter, the ground levels of the nonvolatile memory device 120 side and the access device 100 side are made common through the terminal 3 and the terminal 6, and power is supplied from the access device 100 to the nonvolatile memory device 120 via the terminal 4. The device 120 starts the initialization process and, as shown in FIG. 2, the voltage level of the data transfer speed control terminal 150 becomes “High” via the power supply terminal 111 and the adapter device attachment detection contact 121. Table 1 shows the difference depending on whether the nonvolatile storage device 120 and the adapter device 110 are attached or not.

  The voltage level of the data transfer rate control terminal 150 is transferred to the data transfer rate control unit 131 through the host interface 210 as a data transfer rate flag (value 1). As shown in Table 1, the operation mode is set when the data transfer rate flag is 1, and the normal mode is set when the value is 0. Thereafter, the nonvolatile storage device 120 enters a state of waiting for access from the access device 100.

  When reading data, the access device 100 transfers the start address (logical address) of the data to be read and the data size to be read together with the read command to the nonvolatile storage device 120. Here, the relationship between the logical address and the physical address will be described with reference to Table 2, FIG. 2 and FIG.

  First, in Table 2, logical addresses are cyclically assigned to the non-volatile memories 400 to 407 every 4 kbytes in descending order from address 0. The logical addresses shown in Table 2 are expressed in hexadecimal numbers. Normally, data such as still images and moving images have a relatively large capacity of several megabytes or more, and are recorded at consecutive logical addresses as much as possible so that they can be accessed at high speed. In other words, the nonvolatile memories 400 to 407 are accessed cyclically when data is written to or read from the nonvolatile memories 400 to 407.

  In reading and writing to the nonvolatile memories 400 to 407, data is performed via the buffer RAMs 220 to 227. The buffer RAMs 220 to 227 are used cyclically in units of 4 kbytes, such as data in which logical addresses of 4 kbytes from the address 0 are continuous in the buffer RAM 220, and data for the next 4 kbytes in the buffer RAM 221. Is done.

  Next, the relationship between the logical address and the district will be described with reference to FIG. For example, for data having logical addresses of 4 kbytes starting from address 0, the first 2 kbytes are allocated to the D0 side of the non-volatile memory 300, and the second 2 kbytes are allocated to the D1 side of the non-volatile memory 300. The physical block in D0 or D1 is determined by the address management unit 240, and is allocated to each page so as to be logically continuous in the physical block. Since the selection of the physical block of the address management unit 240, that is, the logical physical conversion process can be realized by using a conventional technique, the description thereof is omitted.

Data Read Processing Next, data read processing will be described. Here, the case of continuous reading from the logical address 0 will be described with reference to FIGS.

  First, in FIG. 2, the access device 100 transfers the start address (logical address) of the data to be read and the data size to be read together with the read command. The host interface 210 transfers the received start address and data size to the address management unit 240. The address management unit 240 counts the logical address in units of pages (2 kbytes), determines a physical address for each logical address, The physical address is transferred to the read / write controller 230. The read / write control unit 230 reads data from the nonvolatile memories 260 to 267 based on the physical address, and temporarily stores the data in the buffer RAMs 220 to 227 in a cyclic manner.

  Next, contents processed by the data transfer rate control unit 131 will be described with reference to FIG. In FIG. 4, the data transfer rate control unit 131 receives the data transfer rate control flag from the host interface 210 (S400), and when the adapter device 110 is not attached to the nonvolatile storage device 120, that is, in the normal mode, after S402. On the other hand, when the adapter device 110 is attached to the nonvolatile storage device 120, that is, in the high-speed mode, the processing ends. Here, since the adapter device 110 is mounted, that is, in the high speed mode, the processing of the data transfer rate control unit 131 is terminated. As will be described later, in the normal mode, the data transfer rate control unit 131 outputs a wait signal WS to the read / write control unit 230.

  Next, data generated by the data reading process, the reading rate, and the reading process will be described with reference to FIG. In FIG. 5, the read / write control unit 230 transfers the read command and the physical address received from the address management unit 240 to the non-volatile memory 260, and the non-volatile memory 260 reads the I / O registers 310 and 320 from the memory cell array 300 (“ The read / write control unit 230 reads the data corresponding to 2 kbytes from the logical address 0 from D0 of the nonvolatile memory 260 and the data corresponding to the subsequent 2 kbytes of the nonvolatile memory 260. Reading from D1 (transfer period hatched with diagonal lines), 4 kbytes of data are collectively stored in the buffer RAM 220. Immediately after temporary storage, the access device 100 reads 40 μS. The transfer rate required for reading the buffer RAMs 220 to 227 of the access device 100 is 100 MBps as shown in (Equation 1).

  During the read busy period, the non-volatile memory 260 returns the read busy flag RB0 to the data transfer rate control unit 131, and during the transfer period, the read / write control unit 230 returns the transfer in progress flag TF0 to the data transfer rate control unit 131. However, since the high-speed mode is used as described above, the wait signal WS output from the data transfer rate control unit 131 remains “Low”. Accordingly, the read / write control unit 230 continuously reads data from the buffer RAMs 220 to 227, and the access device 100 continuously reads data temporarily stored in the buffer RAMs 220 to 227. The read rate at this time is the smaller of the value obtained by (Equation 2) and the transfer rate obtained by (Equation 1). That is, the read rate is 100 MBps. Note that since the transfer rate obtained by (Equation 1) is smaller than the value obtained by (Equation 2), a state in which reading from any one of the nonvolatile memories 260 to 267 is waited at some point occurs. To do.

  Next, the average temperature rise ΔT generated in the adapter device 110 by this reading process is obtained by the conventionally known (Equation 3). However, in (Equation 3), Q is the power required to read the nonvolatile memories 260 to 267, and the average current 10mA and voltage 3.3V during reading, the number of simultaneous reads from D0 / D1 (2), nonvolatile It can be calculated from the number of parallel accesses (8) of the non-volatile memories 260 to 267 and the correction coefficient (100 MBps / 131 MBps) due to waiting for reading from any of the non-volatile memories 260 to 267 described above. Note that S is the surface area of the adapter device 110 shown in FIG. When the ambient temperature TE of the adapter device 110 is 25 ° C., the surface temperature T of the adapter device 110 is the sum of TE (25 ° C.) and ΔT (18 ° C.), that is, T = 43 ° C. There is no risk of burns, and there is a relatively low possibility that a decrease in reliability during reading will be a problem.

  Here, when the nonvolatile memory device 120 is operated in the high-speed mode without attaching the adapter device 110, the average temperature rise ΔT generated in the nonvolatile memory device 120 is about 48 ° C. according to (Equation 4). . Note that S is a surface area when the nonvolatile storage device 120 is an SD memory card. When the ambient temperature TE of the nonvolatile memory device 120 is 25 ° C., the surface temperature T of the nonvolatile memory device 120 is the sum of TE and ΔT, that is, T = 73 ° C. There is a high possibility that the risk increases and a decrease in reliability at the time of reading becomes a problem.

  As described above, when data is continuously read out in the high-speed mode, by attaching the adapter device 110 having a sufficiently large surface area as shown in FIG. Can be avoided. Further, as shown in FIG. 9B, the surface area is not as large as that shown in FIG. 9A, but a small casing portion 900 formed of a high heat conductive member or a small terminal portion 901 formed of a high heat conductive member is used. Accordingly, it is possible to suppress the temperature rise by releasing heat to the access device 100 side, that is, to reduce ΔT. Furthermore, as shown in FIG. 9C, it is possible to suppress the temperature rise by adhering the heat radiating member 920 to the small casing 910.

Data writing process Next, the data writing process will be described. Also in the writing process, the case of writing continuously from the logical address 0 will be described with reference to FIGS.

  First, in FIG. 2, the access device 100 transfers a start address (logical address) of data to be written together with a write command. Note that the writing is completed by transferring the interruption command from the access device 100.

  The host interface 210 cyclically temporarily stores the received data in the buffer RAMs 220 to 227 and transfers a logical address corresponding to the data temporarily stored in the buffer RAMs 220 to 227 to the address management unit 240 based on the received start address. To do. The address management unit 240 determines a physical address based on the logical address, instructs the read / write control unit 230 on the physical address, and writes the data cyclically in the data nonvolatile memories 260 to 267 temporarily stored in the buffer RAMs 220 to 227 sequentially.

  The operation of the data transfer rate control unit 131 is the same as the data reading process described above, and is controlled as the high-speed mode, so the description thereof is omitted here.

  Next, data generated by the data writing process, the writing rate, and the writing process will be described with reference to FIG. In FIG. 7, the read / write control unit 230 transfers the transfer start command, the physical address, and the data temporarily stored in the buffer RAM 220 to the nonvolatile memory 260 (transfer period hatched with diagonal lines), and then transfers the write command to the nonvolatile memory. The memory 260 writes the data transferred to the I / O registers 310 and 320 to the page corresponding to the designated physical address (write busy period expressed as “W”). Data corresponding to 2 kbytes from the logical address 0 is written in D0 of the non-volatile memory 260, and data corresponding to the subsequent 2 kbytes is written in D1 of the non-volatile memory 260. The time for transferring data from the access device 100 to each of the buffer RAMs 220 to 227 is 40 μS, and the transfer rate is 100 MBps as shown in (Equation 1).

  During the write busy period, the nonvolatile memory 260 returns the write busy flag RB0 to the data transfer rate control unit 131, and during the transfer period, the read / write control unit 230 returns the transfer in progress flag TF0 to the data transfer rate control unit 131. However, since the high-speed mode is used as described above, the wait signal WS output from the data transfer rate control unit 131 remains “Low”. Therefore, the read / write control unit 230 continuously transfers the data temporarily stored in the buffer RAMs 220 to 227 to the 260 to 267 and writes them in the nonvolatile memory. The write rate at this time is the smaller of the value obtained by (Equation 5) and the transfer rate obtained by (Equation 1). That is, the write rate is about 34 MBps. Since the transfer rate obtained by (Equation 1) is larger than the value obtained by (Equation 5), the temporary storage processing of data from the access device to the buffer RAMs 220 to 227 is waited at some point in time. Occurs.

  Next, the average temperature rise ΔT generated in the adapter device 110 by this writing process is obtained by (Equation 6). However, Q is the power required for writing to the nonvolatile memories 260 to 267. The average current at the time of writing is 10 mA, the voltage is 3.3 V, the number of simultaneous reads from D0 / D1 (2), and the nonvolatile memories 260 to 267 It can be calculated by the number of parallel accesses (8). S is the surface area of the adapter device 110 shown in FIG. When the ambient temperature TE of the adapter device 110 is 25 ° C., the surface temperature T of the adapter device 110 is the sum of TE and ΔT (23 ° C.), that is, T = 48 ° C., and there is a risk of burns when the adapter device 110 is handled. There is no. In addition, when data is read immediately after writing in such a high-speed mode, that is, when data is read without waiting for the cooling period of the adapter device 110, there is a relatively small possibility that a decrease in reliability at the time of data reading becomes a problem.

  Here, when the nonvolatile memory device 120 is operated in the high-speed mode without attaching the adapter device 110, the average temperature rise ΔT generated in the nonvolatile memory device 120 is about 60 ° C. according to (Equation 7). . Note that S is a surface area when the nonvolatile storage device 120 is an SD memory card. When the ambient temperature TE of the nonvolatile memory device 120 is 25 ° C., the surface temperature T of the nonvolatile memory device 120 is the sum of TE and ΔT, that is, T = 85 ° C., and when the nonvolatile memory device 120 is handled, There is a risk. In addition, when data is read immediately after writing in such a high-speed mode, that is, without waiting for the cooling period of the adapter device 110, there is a high possibility that a decrease in reliability at the time of reading becomes a problem.

As described above, even when data is continuously written in the high-speed mode, as described above, by mounting the adapter device 110 as shown in FIGS. 9A, 9B, and 9C, safety can be improved. Data reliability can be ensured.
[When adapter device 110 is not attached]
Next, a case where data is read / written from / to the nonvolatile storage device 120 directly from the access device 100 without mounting the adapter device 110 will be described.

  In FIG. 1, the nonvolatile storage device 120 is directly inserted into the insertion port 109 of the access device 100, so that the nonvolatile storage device 120 is electrically connected to the access device 100 via the card interface 101. . At this time, the nonvolatile storage device 120 starts the initialization process without supplying power to the adapter device attachment detection contact 121 installed on the upper side surface of the nonvolatile storage device 120. Therefore, the voltage level of the data transfer rate control terminal 150 becomes “Low” and is transferred to the data transfer rate control unit 131 as the data transfer rate flag (value 0), and operates in the normal mode as shown in Table 1. It becomes.

Data Reading Process Compared with the above-described “when the adapter device 110 is attached”, the contents to be processed by the data transfer rate control unit 131 are different, and this point will be mainly described.

  In FIG. 4, the data transfer rate control unit 131 receives the data transfer rate control flag from the host interface 210 (S400), and when the adapter device 110 is not attached to the nonvolatile storage device 120, that is, in the normal mode, after S402. The process proceeds to (S401). The data transfer rate control unit 131 receives the RB signal RBn (n = 0 to 7) from the nonvolatile memory group 140, and further receives the transfer flag TFn (n = 0 to 7) from the read / write control unit 230 (S402). . Then, after calculating the in-access flag AFn (n = 0 to 7) based on (Equation 8) described above (S403), the speed control parameter stored in advance in the speed control parameter storage unit 132 in the data transfer rate control unit 131 is obtained. M is read, and a wait signal WS is calculated based on (Equation 9) (S404). In this embodiment, M is a value of 1. In this case, data is transferred to any one or more of the nonvolatile memories 260 to 267, or any one or more of the nonvolatile memories 260 to 267 is used. When is busy, the wait signal WS becomes 1. Then, the data transfer rate control unit 131 outputs the wait signal WS to the read / write control unit 230 (S405). When the wait signal WS is the value 1, the read / write control unit 230 continues until the wait signal WS becomes the value 0. The reading process will be stopped. Note that the speed limit parameter M is a parameter stored in advance in the speed limit parameter storage unit 132 in the data transfer rate control unit 131, and may be set to a value other than the value 1.

  Next, data generated by the data reading process, the reading rate, and the reading process will be described with reference to FIG. The difference from FIG. 5 is that the read start time of the nonvolatile memories 260 to 267 is controlled by the wait signal WS. Specifically, AF0 that is set to a value of 1 by reading data from the nonvolatile memory 260 is output to the read / write controller 230 as a wait signal WS, and the read / write controller 230 reads the next read, that is, from the nonvolatile memory 261. The data reading is interrupted. When the data reading from the nonvolatile memory 260 is completed, the value AF0 becomes 0, so the wait signal WS becomes “Low”, and the read / write control unit 230 starts reading data from the nonvolatile memory 261. As described above, the read period of the non-volatile memories 260 to 267 is dispersed by controlling the start of reading of the next non-volatile memory by the wait signal WS.

  The read rate at this time is the smaller of the value obtained by (Equation 10) and the transfer rate obtained by (Equation 1). That is, the read rate is 16 MBps obtained by (Equation 10). Since the transfer rate obtained by (Equation 1) is larger than the value obtained by (Equation 10), a state in which reading from the buffer RAMs 220 to 227 of the access device 100 is awaited occurs.

  The average temperature rise ΔT generated in the non-volatile memory device 120 by this reading process is obtained as 11 ° C. according to (Equation 11). However, Q is the power required for reading the nonvolatile memories 260 to 267, and can be calculated from the average current 10mA at the time of reading, the voltage 3.3V, and the number of simultaneous reads 2 from D0 / D1. Note that S is a surface area when the nonvolatile storage device 120 is an SD memory card. When the ambient temperature TE of the nonvolatile memory device 120 is 25 ° C., the surface temperature T of the nonvolatile memory device 120 is the sum of TE and ΔT, that is, T = 36 ° C., and there is a risk of burns when the adapter device 110 is handled. In addition, there is a relatively small possibility that a decrease in reliability during reading will be a problem.

  As described above, when data is read in the normal mode, that is, when the speed limit parameter M is set to a value of 1, the read processing of the non-volatile memories 260 to 267 is performed so as not to overlap in time. It is possible to ensure safety and data reliability without mounting.

  Note that by setting the value of the speed limit parameter M to 2, reading processing of only two nonvolatile memories out of the nonvolatile memories 260 to 267 is overlapped. In this case, the average temperature rise ΔT generated in the nonvolatile memory device 120 is calculated to be 20 ° C. according to (Equation 12). In this case, the surface temperature T of the nonvolatile memory device 120 is the sum of TE and ΔT, that is, T = 45 ° C., and there is no risk of burns when handling the adapter device 110, and there is a decrease in reliability during reading. The potential for problems is relatively small.

  The value of the speed limit parameter M may be appropriately set according to conditions such as the reliability of the nonvolatile memory to be used at the stage of designing the nonvolatile storage device 120.

Data writing process Compared with the above-mentioned “when the adapter device 110 is mounted”, the data transfer rate control unit 131 differs in processing contents as in the data read process, and the data transfer rate control unit 131 generates As shown in FIG. 8, the write period to the nonvolatile memories 260 to 267 is dispersed by the wait signal WS to be performed.

  The read rate at this time is the smaller of the value obtained by (Equation 13) and the transfer rate obtained by (Equation 1). That is, the read rate is 4.3 MBps obtained by (Equation 13). Since the transfer rate obtained by (Equation 1) is larger than the value obtained by (Equation 13), a state in which writing to the buffer RAMs 220 to 227 of the access device 100 is awaited occurs.

  The average temperature rise ΔT generated in the nonvolatile memory device 120 by this writing process is obtained by (Equation 11) as in the data reading process described with reference to FIG. That is, the surface temperature T of the nonvolatile memory device 120 is 36 ° C., there is no risk of burns when the adapter device 110 is handled, and there is a relatively low possibility that reliability degradation during reading will be a problem.

  As described above, even when data is written in the normal mode, that is, when the reading process of the nonvolatile memories 260 to 267 is performed so as not to overlap in time by setting the speed limit parameter M to the value 1, the adapter device Safety and data reliability can be ensured without wearing 110.

  Note that the value of the speed limit parameter M may be appropriately set according to conditions such as the reliability of the nonvolatile memory to be used in the stage of designing the nonvolatile storage device 120, as in the data reading process described above. .

  As described above, the reading and writing of data have been described separately for the case where the adapter device 110 is attached to the nonvolatile memory device 120 and the case where the adapter device 110 is used without being attached. Further, by providing the nonvolatile memory device 120 with the adapter device attachment detection unit 122 and the data transfer rate control unit 131, the surface area is sufficiently larger than that of the nonvolatile memory device 120 or high heat conduction is achieved. Since the high speed operation is permitted only when the adapter device 110 formed of a member is mounted, and the operation speed is suppressed when the adapter device 110 is not mounted, it is caused by heat generation that increases in proportion to the operation speed. Decreased reliability of read data and burns when handling the non-volatile storage device 120 What danger can be avoided.

(Embodiment 2)
FIG. 10 is a block diagram showing a method for implementing the nonvolatile memory system according to Embodiment 2 of the present invention. In FIG. 10, the nonvolatile storage system includes an access device 100, an adapter device 1010, and a nonvolatile storage device 1020. Reference numeral 1011 denotes a conductive switch, 1012 denotes a non-volatile storage device mounting detection unit, 1013 denotes a data transfer rate control signal transmission terminal, 1014, 1015, and 1021 denote conductive members, and 1022 denotes a data transfer rate control signal reception terminal.

  FIG. 11 is a block diagram illustrating the nonvolatile memory device 1020 and the nonvolatile memory device attachment detection unit 1012. 1101 is a resistor and 1102 is a ground. Others are the same as FIG.

  The non-volatile storage system according to Embodiment 2 of the present invention configured as described above will be described. The difference from the first embodiment is only that the adapter device 1010 has a function of detecting whether or not the adapter device 1010 is attached to the nonvolatile memory device 1020. Since this is the same as that of the first embodiment, only the operation of detecting the mounting of the adapter device 1010 will be described.

  In FIG. 10, the nonvolatile storage device 1020 is inserted into the insertion port 119 of the adapter device 1010, the adapter device 1010 is attached, and is inserted into the insertion port 109 of the access device 100, whereby the nonvolatile storage device 1020 is inserted into the card interface 101. It is electrically connected to the access device 100 via At this time, the conductive members 1014 and 1015 provided in the adapter device 1010 are conducted by the conductive member 1021 provided in the nonvolatile storage device 1020, and the power source is connected via the terminal 4 and the conductive members 1014 and 1015. The data is supplied to the nonvolatile memory device attachment detection unit 1012 provided in the adapter device 1010.

  Further, the data transfer rate control signal transmission terminal 1013 provided in the adapter device 1010 and the data transfer rate control signal reception terminal 1022 provided in the nonvolatile storage device 1020 are joined.

  In the non-volatile storage device mounting detection unit 1012, as shown in FIG. 11, the power is supplied to the data transfer rate control signal transmission terminal 1013 by the conductive member 1021, and further the data joined to the data transfer rate control signal transmission terminal 1013. The power is also supplied to the transfer rate control signal receiving terminal 1022 and the voltage level of the data transfer rate control terminal 150 becomes “High”. The relationship with the operation mode at this time is as shown in Table 1.

  The voltage level of the data transfer rate control terminal 150 is transferred to the data transfer rate control unit 131 through the host interface 210 as a data transfer rate flag (value 1). As shown in Table 1, the operation mode is set when the data transfer rate flag is 1, and the normal mode is set when the value is 0. Thereafter, the nonvolatile storage device 120 enters a state of waiting for access from the access device 100. Since the subsequent processing is the same as that of the first embodiment, description thereof is omitted.

  As described above, also in the second embodiment, the adapter device 1010 is allowed to operate at high speed only when the adapter device 1010 having a surface area sufficiently larger than that of the nonvolatile memory device 1020 or the adapter device 1010 formed of a high heat conductive member is attached. Since the operation speed is suppressed when the battery is not mounted, there is a risk of a decrease in reliability of read data caused by heat generation that increases in proportion to the operation speed or a burn in handling the nonvolatile memory device 1020. It can be avoided.

  There are various types of the adapter device 110 and the adapter device 1010 as shown in FIGS. 9A, 9B, and 9C. For example, a cooling device is provided in the adapter device 110 or 1010. Other means such as suppression of heat generation may be used. Therefore, as an example, instead of detecting the adapter device, a heat dissipation function detection unit that detects the effectiveness of the heat dissipation function of the attachment destination, and a data transfer rate limiting unit that limits the data transfer rate related to data reading and writing The data transfer rate limiting unit may be configured to limit the data transfer rate to a predetermined value or less when the heat dissipation function detection unit detects invalidity of the heat dissipation function.

  Further, the switching of the speed mode for the data transfer speed control unit 131 or the method of setting the value of the speed limit parameter M is not limited to the first embodiment or the second embodiment. In addition, as problems caused by heat generation due to high-speed operation, problems related to data reliability and safety problems such as burns were raised, but the technology disclosed in the present invention should also deal with other problems. Is possible.

  The nonvolatile memory system according to the present invention proposes a method that can cope with various problems caused by heat generated due to high-speed operation. Needless to say, a semiconductor memory card, a nonvolatile memory such as a semiconductor memory card is proposed. The present invention is also useful in a still image recording / reproducing apparatus, a moving image recording / reproducing apparatus, or a mobile phone using the apparatus.

1 is a block diagram showing a method for implementing a nonvolatile memory system in Embodiment 1 of the present invention. The block diagram which shows the structure of the non-volatile memory device by Embodiment 1 Schematic diagram showing the configuration of a nonvolatile memory in the nonvolatile memory device A flowchart showing the processing contents of the data transfer rate control unit in the nonvolatile storage device Time chart showing read processing in high-speed mode in the nonvolatile memory device Time chart showing read processing in normal mode in the nonvolatile memory device Time chart showing write processing in high-speed mode in the nonvolatile memory device Time chart showing write processing in normal mode in the nonvolatile memory device Outline drawing of adapter device according to embodiment 1 of the present invention The block diagram which shows the implementation method of the non-volatile storage system in Embodiment 2 of this invention The block diagram which shows the non-volatile memory device by the same Embodiment 2, and a non-volatile memory device mounting | wearing detection part

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Access apparatus 101 Card interface 109,119 Insertion slot 110,1010 Adapter apparatus 111 Power supply terminal 120,1020 Nonvolatile memory device 121 Contact for adapter apparatus installation detection 122 Adapter apparatus installation detection part 130 Memory controller 131 Data transfer speed control part 140 Nonvolatile Memory group (flash memory group)
200 Adapter Mounting Detection Unit 201 Power Supply 202, 1101 Resistor 203, 1102 Ground 210 Host Interface 220-227 Buffer RAM
240 Address management unit 250 Speed limit parameter storage unit 251 External notification unit 260 to 267 Non-volatile memory (flash memory)
DESCRIPTION OF SYMBOLS 300 Memory cell array 310,320 I / O register 330 Peripheral circuit 900 Small housing | casing part shape | molded with the high heat conductive member 901 Terminal part formed with the high heat conductive member 910 Small housing | casing part which adhere | attached the heat radiating member 920 920 Heat radiating member 1011 Conductive switch 1012 Non-volatile storage device mounting detector 1013 Data transfer rate control signal transmission terminal 1014, 1015, 1021 Conductive member 1022 Data transfer rate control signal reception terminal

Claims (9)

A nonvolatile storage device that reads and writes data in response to an external access instruction,
A non-volatile memory, an adapter device attachment detection unit that detects whether or not the attachment destination is an adapter device, and a data transfer rate limiting unit that limits a data transfer rate related to data reading and writing,
The non-volatile storage device, wherein the data transfer rate limiting unit limits the data transfer rate to a predetermined value or less when the adapter mounting detection unit does not detect mounting on the adapter device. The nonvolatile memory device according to claim 1, wherein the data transfer rate limiting unit limits the data transfer rate based on a previously stored speed limit parameter. An external notification unit,
3. The external notification unit according to claim 1, wherein the external notification unit notifies the outside whether or not the data transfer rate control unit limits the data transfer rate, or information related to the limitation of the data transfer rate. Non-volatile storage device. An adapter device used at least between a non-volatile storage device having a non-volatile memory and an access device for reading and writing the non-volatile storage device,
A non-volatile storage device attachment detection unit that detects whether or not the non-volatile storage device is attached, and a data transfer rate limit that restricts a data transfer rate related to reading and writing of data in the non-volatile storage device. A data transfer rate limit instruction unit for instructing the volatile storage device,
The data transfer rate restriction instruction unit performs an instruction to limit the data transfer rate to a predetermined value or less when the nonvolatile storage device attachment detection unit does not detect the attachment of the nonvolatile storage device. Adapter device. The adapter device according to claim 4, wherein the adapter device has a surface area larger than a surface area of the nonvolatile memory device. 6. The adapter device according to claim 4, wherein the adapter device has a portion formed by at least a high thermal conductivity material. The adapter device according to claim 4, wherein the adapter device includes a heat radiating member. The adapter device according to claim 4, wherein the adapter device includes a cooling device. A nonvolatile storage device that reads and writes data in response to an external access instruction,
A non-volatile memory, a heat dissipation function detection unit that detects the effectiveness of the heat dissipation function of the mounting destination, and a data transfer rate limiting unit that limits the data transfer rate related to data reading and writing,
The data transfer rate limiting unit limits a data transfer rate to a predetermined value or less when the heat dissipation function detection unit detects invalidity of the heat dissipation function.

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