JP2007316871A - Processor unit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a processor unit enabling efficient use of various softwares by CPU. <P>SOLUTION: The processor unit 10 having a CPU connected to a main memory storing programs to be executed by the CPU through a common bus comprises a memory card control part 13 interposed between the CPU 11 and an external memory card 22 detachably connected thereto to access the memory card; and a loader unit 30 connected to the common bus, which reads a CPU activating program from a predetermined address of the memory card through the memory card control part with system reset of the CPU as a trigger and develops it to an activating program storage area of the main memory. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a processor unit, and more particularly to a processor unit in which a CPU and a main memory storing a program executed by the CPU are connected via a common bus.

  Today, various electronic devices such as mobile phones operate under the control of a processor unit (such as an embedded processor). Once the system is fixed, the size of the main memory fixed on the board and the main memory It is not always easy to change or extend functions (programs) or to collect log information that was not initially scheduled due to access restrictions.

In this regard, conventionally, the system activation program is inserted from the memory card 4 while the main controller 12 is interposed between the main controller 12 and the external removable memory card 4 and the system is reset. The access control device 11 is provided to read out and store it in its own storage unit 25. After the main control unit 12 is reset, the main control unit 12 reads out and starts the activation program from the storage unit 25, and then the memory card 4 An electronic device that executes the various programs is known (Patent Document 1). As a result, various programs including the startup program can be easily changed without increasing the size of the system.
JP 2005-122532 A

  However, if the startup program for the main control unit 12 is stored in the externally provided storage unit 25, an extra storage unit 25 is required in addition to the original main storage unit 13, and the main control A device for setting the unit 12 to start up using the external storage unit 25 (setting / changing the memory space for the CPU, etc.) is required.

  The present invention has been made in view of the above-mentioned problems of the prior art, and its object is to provide a processor unit that can efficiently use various software by a CPU without providing a separate startup program storage memory outside. Is to provide.

  The processor unit according to the first aspect of the present invention is a processor unit in which a CPU and a main memory storing a program executed by the CPU are connected via a common bus, and the CPU is detachably connected to the outside. A memory card control unit for accessing the memory card interposed between the memory card and the memory card, connected to the common bus, and triggered by a system reset of the CPU via the memory card control unit A loader unit that reads a CPU activation program from a predetermined address of the memory card and expands it in the activation program storage area of the main memory.

According to the present invention, the CPU startup program read from the memory card is expanded and executed in the startup program storage area of the main memory, so that no extra memory is required, and the CPU and the main memory can be used. Even if the existing system is not changed, the system can be started up normally, and thereafter, various software on the external memory card can be used effectively. Also, by removing this memory card, program updates and log analysis can be performed easily using an external personal computer. In addition, capacity expansion can be easily handled by changing the memory card.

  In the second aspect of the present invention, the loader unit is configured by a hardware logic circuit such as FPGA or PLD. Therefore, a hardware loader unit capable of accessing various memory cards can be configured flexibly and efficiently.

  In the third aspect of the present invention, the memory card is a compact flash (registered trademark) or a PC-ATA card.

  As described above, according to the present invention, an external memory card and various software on the memory card can be used by connecting a relatively simple loader unit to the common bus of the system. The place that contributes to the improvement of expandability is extremely large.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. Note that the same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 1 is a block diagram of a processor unit according to an embodiment. Reference numeral 10 denotes a processor unit (PU) that is mounted on various electronic devices to realize each required function. An external memory card 22 made of a registered trademark or a PC card is detachably provided.

  In the PU 10, 11 is a CPU that performs main control and processing of the PU 11, 12 is a main memory (MM) used by the CPU 11, and 13 is a memory that is interposed between the CPU 11 and the memory card 22 and performs access control of the memory card 22. The card control unit 14 is connected to the common bus 14 of the PU 14, and 30 is connected to the common bus 14 and is activated when the system (CPU 11) is reset, reads the activation program for the CPU 11 from the memory card 22, and reads the main memory 12. Is a loader unit that is expanded in the startup program storage area. When the operation is resumed after the system reset of the present system, the CPU 11 fetches an instruction at a predetermined address in the main memory 12 (for example, the first address of the activation program storage area) and executes it.

  When a system reset signal is input to the loader unit 30, a wait signal to the CPU 11 is energized to stop the operation of the CPU 11 and execute the sector read process of FIG. Thus, the activation program for the CPU 11 is read from a predetermined address of the memory card 22 and expanded in the activation program storage area of the main memory 12. Thus, when the development of the activation program is finished, the wait signal is deactivated and the CPU 11 can be operated. As a result, the CPU 1 starts execution from the top command in the startup program storage area and, if necessary, reads a higher startup program from a predetermined address of the main memory 12 via the memory card control unit 13 to read the main memory. 12 and execute sequentially. In this way, when the CPU 11 is activated, various application programs can be read from the memory card 22 and executed, and log data can be written to the memory card 22.

FIG. 2 is a flowchart of an access (sector read) method for the memory card 22 and shows an example of application to a memory card using CompactFlash (registered trademark). In step S11, cylinder addresses are set in the low register and high register of the cylinder. In step S12, the head number is set in the drive head register. In step S13, the sector number is set in the sector number register. In step S14, the number of read sectors (here, “01h” is described as an example) is set in the sector count register. Here, h represents hexadecimal notation.

  In step S15, the sector read command “20h” is set in the command register. In step S16, the status register is read. In step S17, it is determined whether or not the DREQ bit is set to "58h". If NO, the process returns to step S16. Thus, if YES is eventually reached, the data register is read 256 times (512 bytes) in step S18. In step S19, the status register is read. In step S20, it is determined whether or not the DREQ bit is reset to “50h”. If NO, the process returns to step S19. Thus, when the answer is YES, the process is terminated and the next command input is waited.

  The loader unit 30 outputs a sector read command to the memory card control unit 13 to read sector data, and sequentially stores the obtained data in the activation program storage area of the main memory 12.

  FIG. 3 is a block diagram of the loader unit according to the embodiment. Although this loader unit 30 is basically configured by hardware, it is energized by the input of a system reset, and reads the activation program from the memory card 22 and expands it in the main memory 12 to some extent. In order to efficiently implement complex functions, it consists of a general-purpose processor that can execute a minimum number of commands. Such a circuit is preferably constituted by a PLD (Programmable Logic Device) or an FPGA (Field Programmable Gate Array), and FIG. 3 shows a functional block diagram as a general-purpose processor.

  The loader unit 30 includes a microprocessor unit (MPU) 40 having a program code fetch cycle and an execute cycle, and the MPU 40 via internal bus lines (address bus AB, data bus DA, control bus CB). And a program memory (PMEM) 60 including a ROM and an EEPROM to be connected.

  In the MPU 40, 41 is a program counter (PCTR) that controls the fetch address of a program instruction, 42 is a memory stack (STCK) that holds (push / pop) the interrupt address of the PCTR 41, 43 is a set address (jump address) to the PCTR 41 The data multiplexer (MUX) 44 selects an instruction register (IREG) that holds an instruction code (operation code, operand code, etc.) fetched from the PMEM 60, and 45 indicates an operand bus (OPLB) for transferring operand data of the IREG 44. ), 46 is an instruction decoder (IDEC) that decodes the operation code portion (including the address qualifier) of the IREG 44 and generates a corresponding series of control signals CT, and 47 is a logic / arithmetic circuit unit that performs simple logic determination and calculation ALU), 48 is a general purpose register (WREG) cooperating with the ALU 47, 49 is a data multiplexer (MUX) for selecting data to be input to the ALU 47, and 50 is a storage address (indirect address IAD) of an instruction code or operand data. Is an address register (ADR) 51, 51 is a data multiplexer (MUX) for selecting an operand address (direct address DAD) of the operand bus 45 and an indirect address IAD of the ADR 50 and outputting it to the address bus AB, and 52 is an MPU 40. A bus interface (BIF) that connects the internal bus and the common bus 14 of the PU 10. Here, AB is an address bus of the MPU 40, DB is a data bus, and CB is a control bus in which various control signal lines output from the IDEC 46 are bundled.

The control signal CT output from the instruction decoder 46 includes a fetch signal FECH / execute signal EXE indicating a fetch / execute machine cycle, a set signal ST for setting data in various registers, PCTR 41, and the like. An output energizing signal OE for outputting output data of the PCTR 41 and the like to a bus and a target circuit, a selection signal SL for selecting input data in a data multiplexer, a data write control signal WR to the memory, a memory Data read control signal RD from I, an I / O command signal I / OCOM output to the outside via BIF 52, and the like.

  The PMEM 60 stores in advance a program for executing the sector read of FIG. 2 and developing it in the main memory 12. By sequentially executing the program, the data read from the memory card 22 is stored in the main memory 12. Expands to a predetermined address.

  In the above embodiment, the loader unit 30 is realized by a hardware circuit having a processor configuration in order to efficiently realize a somewhat advanced control function for the memory card 22 via the memory card control unit 13. Not exclusively. In addition, the loader unit 30 can be configured by sequencer logic closer to a normal hardware configuration. An example sequencer logic includes a memory that stores a series of commands, a counter that generates an access address of the memory, a count value of the counter, a read output of a part of the memory, and a predetermined external condition. Based on this, a sequencer circuit unit (gate circuit unit) that performs +1 (or -1) control and a logic circuit unit that applies the read output of the memory to the memory card control unit 13 or the like can be used.

  Further, although the preferred embodiment of the present invention has been described, it goes without saying that various changes in the configuration, control, processing, and combination of each part can be made without departing from the spirit of the present invention.

It is a block diagram of the processor unit by embodiment. It is a flowchart of a memory card access method. It is a block diagram of the loader unit by an embodiment.

Explanation of symbols

10 processor unit 11 CPU
12 Main memory (MM)
13 Memory Card Control Unit 14 Common Bus 21 Connector 22 Memory Card 30 Loader Unit

Claims (3)

A processor unit in which a CPU and a main memory storing a program executed by the CPU are connected via a common bus,
A memory card controller for accessing the memory card interposed between the CPU and an externally detachably connected memory card;
Connected to the common bus and triggered by a system reset of the CPU, a CPU startup program is read from a predetermined address of the memory card via the memory card control unit and stored in the main memory startup program storage A processor unit comprising: a loader unit that develops in an area. 2. The processor unit according to claim 1, wherein the loader unit includes a hardware logic circuit such as an FPGA or a PLD. 2. The processor unit according to claim 1, wherein the memory card is a compact flash (registered trademark) or a PC card.

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