JP2007310640A - Semiconductor integrated circuit and ic card using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for simplifying disconnection tests of a plurality of wiring connected to a plurality of photodetectors arranged on a chip for protection against attacks by spot light irradiation. <P>SOLUTION: A plurality of photodetectors PD1 to PD 7 and a driving/sense circuit 11 including a plurality of driving circuits MP1, MN1 to MP7 and MN7 and a plurality of sense amplifying circuits MP12, MN12 to MP72 and MN 72 are formed on the chip. Pull-up driving elements MP1 to MP7 and pull-down driving elements MN1 to MN7 are connected to one ends of the PD1 to PD7 via pull-up driving signal lines Lup1 to Lup7 and pull-down driving signal lines Ldn1 to Ldn7 respectively. Other ends of the PD1 to PD7 are connected to one ends of operation source voltage Vdd and base voltage Vss. A plurality of input terminals of the plurality of sense amplifying circuits are connected inside or near the driving/sense circuit 11 to one driving signal line. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit and an IC card using the same, and more particularly to a technique useful for providing high security by providing a plurality of light receiving elements on a chip.

  A microcomputer (hereinafter referred to as an IC card microcomputer) to be mounted on an IC card having a function of electronic settlement such as a credit card requires high security. In recent years, such IC cards have been used in mobile phones such as GSM-SIM (Global System for Mobile Communications Subscriber Identity Module) cards, credit cards, bank cash cards, ETC (Electronic Toll Collection system) cards, electronic tickets, It is used for various purposes such as ID cards, and is spreading.

  Conventionally, an IC card microcomputer has a security function such as a random number generator. This random number generator is an important cryptographic source widely used in one-time password, key generation and authentication protocols to achieve a high degree of security. In cryptographic processing, random numbers are generated in order to generate endurance information that is not understood by an attacker or a thief.

  However, the attacker attempts to read the personal information of the user of the IC card microcomputer and the encryption key for encryption processing by opening the IC card and performing reverse engineering. For example, by supplying a clock or power supply voltage with a frequency outside the standard to the IC card microcomputer or by irradiating strong electromagnetic waves, the IC card microcomputer malfunctions, and an encryption key for personal information or encryption processing is used. A read is attempted. Moreover, as another attack technique, attack and hacking by light irradiation are increasing year by year. This is reverse engineering in which a malfunction of the IC card microcomputer is induced by light irradiation and analysis is attempted by a statistical method.

  In Patent Document 1 below, a single light receiving element such as a static latch, a MOS transistor, a light receiving diode, etc., is formed on an IC card microcomputer chip. The operation is stopped.

  Patent Document 2 below also describes that a plurality of light receiving elements are distributed and arranged in a high security IC for an IC card or the like.

JP 2004-206680 A JP-A-11-102324

  However, in recent years, the attack method by light irradiation has changed from light irradiation to the whole chip of the IC card microcomputer to spot light irradiation by a laser beam. In this laser beam spot light irradiation, the light receiving element that causes the internal circuit to stop operating is not irradiated with the spot light, while the weak circuit part of the internal circuit that causes the IC card microcomputer malfunction is selectively irradiated with the spot light. Is what you do.

  Therefore, the defense method using only one light receiving element described in Patent Document 1 described above cannot cope with the attack caused by the spot light irradiation.

  In order to cope with the above attack by spot light irradiation, it is necessary to disperse and arrange a plurality of light receiving elements on the chip of the IC card microcomputer as described in Patent Document 2 above. . In particular, it is effective to arrange a plurality of light receiving elements that cause the operation of the internal circuit to stop in the vicinity of a fragile circuit portion that may cause a malfunction on the chip of the IC card microcomputer.

  On the other hand, prior to the present invention, the present inventors engaged in the development of a chip of an IC card microcomputer in which the protection performance against attack by spot light irradiation was improved.

  In this development, when arranging a plurality of light receiving elements, the inventors have been given a technical problem of minimizing the increase in chip area and power consumption.

  In order to solve this technical problem, when the present inventors arrange N light receiving elements (N ≧ 2), the number of drive circuits for driving the N light receiving elements is N, and detection of the N light receiving elements is performed. Although it is unavoidable that the number of sense circuits for sensing signals is N, it has been considered to use one bias circuit for supplying a bias voltage to N drive circuits and N sense circuits. Since the bias voltage of a semiconductor integrated circuit varies due to the manufacturing process, a bias voltage trimming function is required. Adding a bias voltage trimming function to the bias circuit increases the chip area of the bias circuit. Therefore, by using one bias circuit, the increase in chip area and power consumption of the IC card microcomputer can be reduced.

  However, new technical issues with this method have also been clarified. The new technical problem is that N drive circuits, N sense circuits, and N sense circuits are arranged in the vicinity of one bias circuit on the chip. There is a problem that the wiring distance of a plurality of wirings on the chip between the light receiving elements becomes long.

  FIG. 1 is a diagram showing a chip layout of an IC card microcomputer studied by the present inventors prior to the present invention.

  As shown in the figure, on a chip 10 of an IC card microcomputer, a bias / drive / sense circuit 11, a central processing unit (CPU) 12, a read only memory (ROM) 13, and a random access memory (RAM) are provided. 14, an electrically writable / erasable nonvolatile memory (EEPROM) 15, an input / output unit (I / O) 16, and a power supply circuit (Pwr_Spy_Cirt) 17 are arranged.

  Further, photodiodes PD1, PD2, PD3, PD4, which are light receiving elements that cause the entire IC card microcomputer to stop operating in the vicinity of a weak circuit portion inside the CPU 12, ROM 13, RAM 14, EEPROM 15, I / O 16, and power supply circuit 17. Seven PD5, PD6, and PD7 are arranged. Wirings L1, L2, L3, L4, L5, L6, and L7 are connected to the photodiodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7, respectively, but wirings L1, L2, L4, other than the wiring L3, are connected. The wiring distances of L5, L6, and L7 are particularly long.

  FIG. 2 is a circuit diagram showing a bias / drive / sense circuit 11 and photodiodes PD1... PD7 of an IC card microcomputer, which have been studied by the present inventors prior to the present invention.

  As shown in the figure, the bias / drive / sense circuit 11 is connected to the first photodiode PD1 and the seventh photodiode PD7 among the seven photodiodes PD1... PD7. Although not shown, five photodiodes PD2 to PD6 from the second to the sixth are connected in the same manner as the bias / drive / sense circuit 11. The bias / drive / sense circuit 11 includes a first drive / sense circuit DR_SN1 and a seventh DR_SN7 of the seven drive / sense circuits DR_SN1... DR_SN7. Although not shown, five drive / sense circuits DR_SN2... DR_SN6 from the second to the sixth are similarly arranged in the bias / drive / sense circuit 11. One common bias circuit Bias_Cirt for supplying a bias voltage to the seven drive / sense circuits DR_SN 1... DR_SN 7 is arranged in the bias / drive / sense circuit 11.

In the common bias circuit Bias_Cirt, the constant current I ₀ from the constant current source is supplied to the P-channel MOS transistor BMP21 which is a diode-connected input transistor of the first current mirrors BMP21 and BMP22, and is generated by the diode-connected input transistor BMP21. The first bias voltage V1 is commonly supplied to the gates of the seven P-channel MOS transistors MP11... MP71 of the seven drive / sense circuits DR_SN1. A diode-connected N-channel MOS transistor BMN21 is connected to the drain of the P-channel MOS transistor BMP23 which is an output transistor of the first current mirrors BMP21 and BMP22, and the second bias voltage V2 generated by the N-channel MOS transistor BMN21 is 7 pieces. Commonly supplied to the gates of the seven N-channel MOS transistors MN11... MN71 of the drive / sense circuits DR_SN1. In the common bias circuit Bias_Cirt, the constant current 2I from the trimmed constant current source is supplied to the P-channel MOS transistor BMP23 which is a diode-connected input transistor of the second current mirrors BMP23 and BMP24, and the diode-connected input transistor BMP23. The generated third bias voltage V3 is commonly supplied to the gates of seven pull-up drive P-channel MOS transistors MP1... MP7 of the seven drive / sense circuits DR_SN1. The drain current of the P-channel MOS transistor BMP24, which is the output transistor of the second current mirrors BMP23 and BMP24, is supplied to the diode-connected N-channel MOS transistor BMN22. The fourth bias voltage V4 generated by the diode-connected N-channel MOS transistor BMN22 is commonly supplied to the gates of the seven pull-down drive N-channel MOS transistors MN1... MN7 of the seven drive / sense circuits DR_SN1. ing. The photodetection signals from the seven photodiodes PD1... PD7 are sensed by the seven CMOS inverters Inv1... Inv7 of the seven drive / sense circuits DR_SN1. The source of the P-channel MOS transistor MP12 of the first CMOS inverter Inv1 is connected to the power supply voltage Vdd via the P-channel MOS transistor MP11, while the source of the N-channel MOS transistor MN12 is grounded via the N-channel MOS transistor MN11. It is connected to the potential Vss. Accordingly, the rush current flowing through the first CMOS inverter Inv1 is limited by the P-channel MOS transistor MP11 and the N-channel MOS transistor MN11. The source of the P-channel MOS transistor MP72 of the seventh CMOS inverter Inv7 is connected to the power supply voltage Vdd via the P-channel MOS transistor MP71, while the source of the N-channel MOS transistor MN72 is grounded via the N-channel MOS transistor MN71. It is connected to the potential Vss. Accordingly, the rush current flowing through the seventh CMOS inverter Inv7 is limited by the P-channel MOS transistor MP71 and the N-channel MOS transistor MN71. The second CMOS inverter Inv2 to the sixth CMOS inverter Inv6 are configured in the same manner as the first CMOS inverter Inv1 and the seventh CMOS inverter Inv7.

  In the bias / drive / sense circuit 11 of FIG. 2, the channel width of the diode-connected N-channel MOS transistor BMN22 of the common bias circuit Bias_Cirt is N channels for seven pull-down drives of the seven drive / sense circuits DR_SN1. It is set to be twice the channel width of the MOS transistors MN1. In addition, the channel width of the diode-connected P-channel MOS transistor BMP23 of the common bias circuit Bias_Cirt is equal to the channel width of the P-channel MOS transistor BMP24 of the common bias circuit Bias_Cirt and the seven drive / sense circuits DR_SN1... DR_SN7. It is equal to the channel width of the pull-up drive P-channel MOS transistors MP1... MP7. As a result, the current sink capability of the seven pull-down drive N-channel MOS transistors MN1... MN7 of the seven drive / sense circuits DR_SN1... DR_SN7 becomes the current I, and the seven drive / sense circuits DR_SN1. The current supply capability of the pull-up drive P-channel MOS transistors MP1... MP7 is the current 2I.

  For example, when the light Lgt by spot light irradiation is irradiated only to the first photodiode PD1 as the light receiving element, the photocurrent Ipd due to the reverse current of the PN junction of the first photodiode PD1 flows, and the second The reverse current at the PN junction of the seventh photodiode PD2 to the seventh photodiode PD7 is a negligible current. When the photocurrent Ipd of the first photodiode PD1 becomes larger than the current I, the charge charged in the parasitic capacitance of the first photodiode PD1 is discharged. Then, the voltage of the input sense node In1 of the first CMOS inverter Inv1 is lowered from the power supply voltage Vdd to the ground voltage Vss, and the output OUT1 is changed from the low level to the high level. Since the charge charges of the parasitic capacitances of the second photodiode PD2 to the seventh photodiode PD7 are maintained, the outputs OUT2... OUT7 of the second CMOS inverter Inv2 to the seventh CMOS inverter Inv7 are at a low level. Maintained.

  As described with reference to FIG. 1, the wiring distances of the wirings L1, L2, L4, L5, L6, and L7 other than the wiring L3 are particularly long. When the wiring distance of the wiring is increased in the semiconductor integrated circuit, there is a high possibility that a part of the long wiring is partially disconnected in the wiring metal deposition process in the manufacturing process. Increasing the wiring width of the wiring having a long wiring distance reduces this possibility, but increases the chip occupation area of the wiring region and decreases the integration density.

  For example, when all the wirings L1... L7 are disconnected in FIG. 2, the parasitic capacitances of the input sense nodes In1... In7 of all the CMOS inverters Inv1... CMOS inverter Inv7 are charged to the power supply voltage Vdd, and all the outputs OUT1. Goes low. In this completely disconnected state, even if an attack due to spot light irradiation is received, the photocurrent Ipd does not flow through any of the seven photodiodes PD1... PD7, and the light from the seven photodiodes PD1. All the CMOS inverters Inv1... CMOS inverter Inv7 cannot sense the detection signal.

  Therefore, in the mass production process of the chip of the IC card microcomputer, a disconnection test of the wirings L1... L7 is necessary, but the outputs OUT1 of the seven CMOS inverters Inv1. ... it is necessary to test the output change of OUT7.

  However, such a test by irradiating / blocking light on a chip is complicated and increases the cost of the chip of the IC card microcomputer.

  Furthermore, the present inventors also examined other methods in advance.

  FIG. 3 is a circuit diagram showing a bias / drive / sense circuit 11 and photodiodes PD1... PD7 of another IC card microcomputer examined by the present inventors prior to the present invention.

  As shown in the figure, seven drive circuits DR1... DR7 are separated from the seven sense circuits SN_1... SN7 and arranged in the vicinity of the seven photodiodes PD1. As a result, a reduction in the possibility of disconnection between the seven drive circuits DR1... DR7 and the seven photodiodes PD1. However, the wiring LPbs for supplying the third bias voltage V3 to the gates of the seven pull-up drive P channel MOS transistors MP1... MP7 of the seven drive circuits DR1... DR7 and the seven pull-down drive N channel MOS transistors MN1. ... The wiring distance of the wiring LNbs that supplies the fourth bias voltage V4 to the gate of MN7 becomes long, and there is a possibility that the wirings LPbs and LNbs are disconnected. Further, the wiring distance of the wiring L1... L7 between the seven photodiodes PD1... PD7 and the input sense nodes In1... In7 of the seven CMOS inverters Inv1. There is a possibility of disconnection. Further, since the long distance wirings L1... L7 are arranged on a logic circuit such as a CPU, noise from the logic circuit crosstalks with the long distance wirings L1. As a result, output noise at the time of detecting light irradiation increases. Furthermore, when trying to lay out the circuit of FIG. 3 on the chip of an IC card microcomputer, a new problem became clear.

  FIG. 4 is a diagram showing a chip layout of another IC card microcomputer studied by the present inventors prior to the present invention.

  As shown in the figure, it has been found that three wiring distances are actually required between one photodiode / drive circuit and one sense circuit. One of the three is a sense signal line from the photodiode, and the other two are bias voltage supply lines for the pull-up driving P-channel MOS transistors and the pull-down driving N-channel MOS transistors MN1.

  Therefore, the present invention has been made on the basis of the above-described IC card microcomputer chip development by the present inventors prior to the present invention.

  Accordingly, an object of the present invention is to facilitate a test of disconnection of a plurality of wirings connected to a plurality of light receiving elements arranged on a chip of a semiconductor integrated circuit in order to protect against an attack caused by spot light irradiation. It is an object of the present invention to provide a semiconductor integrated circuit that can be used. Another object of the present invention is to reduce output noise at the time of detection of light irradiation from a plurality of light receiving elements arranged on a chip of a semiconductor integrated circuit in order to protect against attack by spot light irradiation. There is.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows.

  That is, a semiconductor integrated circuit according to one embodiment of the present invention includes a plurality of light receiving elements (PD1... PD7) and a plurality of drive circuits (MP1, MN1... MP7, MN7) that drive the plurality of light receiving elements (PD1... PD7). And a drive / sense circuit (11) including a plurality of sense amplifier circuits (MP12, MN12... MP72, MN72) for amplifying detection signals of light irradiation from the plurality of light receiving elements (PD1... PD7). It has.

  The plurality of driving circuits (MP1, MN1,..., MP7, MN7) include a plurality of pull-up driving transistors (MP1... MP7) connected to the operating power supply voltage (Vdd) and a plurality connected to the base voltage (Vss). Pull-down driving transistors (MN1... MN7).

  A plurality of output terminals of the plurality of pull-up driving transistors (MP1... MP7) of the plurality of driving circuits (MP1, MN1,..., MP7, MN7) are a plurality of one ends and a plurality of ends of the plurality of light receiving elements (PD1... PD7). The plurality of output terminals of the plurality of pull-down drive transistors (MN1... MN7) of the plurality of drive circuits (MP1, MN1... MP7, MN7) are connected via the pull-up drive signal lines (Lup1... Lup7). The plurality of one ends of the plurality of light receiving elements (PD1... PD7) are connected to the plurality of pull-down drive signal lines (Ldn1... Ldn7).

  The other ends of the plurality of light receiving elements (PD1... PD7) are connected to one voltage (Vss, Vdd) of the operating power supply voltage (Vdd) and the base voltage (Vss).

  The plurality of input terminals (In1... In7) of the plurality of sense amplifier circuits (MP12, MN12... MP72, MN72) are connected to the plurality of pull-up drive signal lines (inside or near the drive / sense circuit (11)). Lup1... Lup7) and a plurality of signal lines (Ldn1... Ldn7, Lup1... Lup7) of the plurality of pull-down drive signal lines (Ldn1... Ldn7). The driving voltages (Vss, Vdd) by the one signal lines (Ldn1... Ldn7, Lup1... Lup7) are the operating power supply voltages to which the plurality of other ends of the plurality of light receiving elements (PD1... PD7) are connected. It is set substantially equal to the one voltage (Vss, Vdd) of (Vdd) and the base voltage (Vss) (see FIGS. 5 and 6).

  According to the means of the one aspect of the present invention, the plurality of pull-up drive signal lines (Lup1... Lup7) or the plurality of pull-down drive signal lines are outside the drive / sense circuit (11) by a semiconductor manufacturing process. When disconnection occurs, disconnection voltages of the plurality of input terminals (In1... In7) of the plurality of sense amplifier circuits (MP12, MN12... MP72, MN72) are caused by the one of the plurality of signal lines (Ldn1... Ldn7, Lup1... Lup7). The driving voltage (Vss, Vdd) is obtained. This disconnection voltage is the voltage (Vss, Vdd) of the operating power supply voltage (Vdd) to which the other ends of the light receiving elements (PD1... PD7) are connected and the base voltage (Vss). Is set to be substantially equal. The sense amplifier circuits (MP12, MN12,..., MP72, MN72) of the plurality of light receiving elements (PD1,..., PD7) when the plurality of light receiving elements (PD1,. The input voltages of the plurality of input terminals (In1... In7) are the operation power supply voltage (Vdd) to which the other ends of the plurality of light receiving elements (PD1... PD7) are connected and the base voltage (Vss). The one voltage (Vss, Vdd) is obtained. Accordingly, an abnormality output signal similar to an abnormality detection signal from the plurality of light receiving elements (PD1... PD7) due to the attack by spot light irradiation generates the plurality of pull-up drive signal lines outside the drive / sense circuit (11). (Lup1... Lup7) or a plurality of outputs from the plurality of sense amplifier circuits (MP12, MN12... MP72, MN72) when the plurality of pull-down drive signal lines are disconnected.

  In the semiconductor integrated circuit according to one specific form of the present invention, the plurality of input terminals (In1... In7) of the plurality of sense amplifier circuits (MP12, MN12... MP72, MN72) are connected to the drive / sense circuit ( 11) or a plurality of connection points (CN1... CN7) connected to the one of the plurality of signal lines (Ldn1... Ldn7, Lup1... Lup7) and the plurality of sense amplifier circuits (MP12). , MN12... MP72, MN72), the wiring distance between the plurality of input terminals (In1... In7) is that of the plurality of pull-up driving transistors (MP1... MP7) of the plurality of driving circuits. The plurality of pull-up drive signal lines (Lu) between the plurality of output terminals and the plurality of one ends of the plurality of light receiving elements (PD1... PD7). 1... Lup7) and the plurality of output terminals of the plurality of pull-down drive transistors (MN1... MN7) of the plurality of drive circuits and the plurality of one ends of the plurality of light receiving elements (PD1... PD7). It is set to be sufficiently shorter than the wiring distance of the plurality of pull-down drive signal lines (Ldn1... Ldn7) between them (see FIGS. 5, 6, and 10).

  According to the means of a specific form of the present invention, the plurality of input terminals (In1... Of the plurality of sense amplifier circuits (MP12, MN12... MP72, MN72)) due to a difference in wiring distance in a semiconductor manufacturing process. A plurality of connection points (CN1... CN7) in which In7) is connected to the one of the plurality of signal lines (Ldn1... Ldn7, Lup1... Lup7) inside or in the vicinity (18) of the drive / sense circuit (11). And the plurality of input terminals (In1... In7) of the plurality of sense amplifier circuits (MP12, MN12... MP72, MN72). Before the plurality of output terminals of the up driving transistors (MP1... MP7) and the plurality of one ends of the plurality of light receiving elements (PD1... PD7) Probability of disconnection of the plurality of pull-up drive signal lines (Lup1... Lup7) and the plurality of output terminals of the plurality of pull-down drive transistors (MN1... MN7) of the plurality of drive circuits and the plurality of light receiving elements (PD1. The probability of disconnection of the plurality of pull-down drive signal lines (Ldn1... Ldn7) between the plurality of one ends of PD7) can be made much lower.

  In the semiconductor integrated circuit according to a specific embodiment of the present invention, the plurality of other ends of the plurality of light receiving elements (PD1... PD7) are connected to the base voltage (Vss), and the plurality of sense amplifier circuits. A plurality of input terminals (In1... In7) of (MP12, MN12... MP72, MN72) are connected to the plurality of pull-down drive signal lines (Ldn1... Ldn7) in the drive / sense circuit (11) ( (See FIG. 5).

  According to the means according to the one specific form of the present invention, the plurality of senses are detected at the time of attack by spot light irradiation and when the drive signal line is disconnected outside the drive / sense circuit (11). The voltages of the plurality of input terminals (In1... In7) of the amplifier circuits (MP12, MN12... MP72, MN72) become the base voltage (Vss).

  In the semiconductor integrated circuit according to another specific embodiment of the present invention, the plurality of other ends of the plurality of light receiving elements (PD1... PD7) are connected to the operation power supply voltage (Vdd). A plurality of input terminals (In1... In7) of the sense amplifier circuits (MP12, MN12... MP72, MN72) are connected to the plurality of pull-up drive signal lines (Lup1... Lup7) inside the drive / sense circuit (11). (See FIG. 6).

  According to the means according to the one specific form of the present invention, the plurality of senses are detected at the time of attack by spot light irradiation and when the drive signal line is disconnected outside the drive / sense circuit (11). The voltages of the plurality of input terminals (In1... In7) of the amplifier circuits (MP12, MN12... MP72, MN72) become the operation power supply voltage (Vdd).

  In the semiconductor integrated circuit according to a more specific form of the present invention, the plurality of pull-up drive signal lines (Lup1... Lup7) are used for the plurality of pull-up drives of the plurality of drive circuits (MP1, MN1... MP7, MN7). A plurality of pull-up output currents from transistors (MP1... MP7) are supplied to the plurality of light receiving elements (PD1... PD7), while the plurality of pull-down drive signal lines (Ldn1... Ldn7) are the plurality of pull-down drive transistors. A plurality of pull-down output currents (MN1... MN7) are supplied from the plurality of light receiving elements (PD1... PD7) (see FIGS. 5 and 6).

  According to the more specific embodiment of the present invention, the plurality of pull-up drive signal lines (Lup1... Lup7) and the plurality of pull-down drive signal lines (Ldn1... Ldn7) are the plurality of light receiving elements. The drive current of (PD1... PD7) is passed. As a result, even if the plurality of pull-up drive signal lines (Lup1... Lup7) and the plurality of pull-down drive signal lines (Ldn1... Ldn7) are long-distance wirings, the noise voltage from the logic circuit arranged thereunder The influence of can be reduced.

  In the semiconductor integrated circuit according to a more specific form of the present invention, the drive / sense circuit (11) includes the plurality of pull-up drive transistors (MP1,...) Of the plurality of drive circuits (MP1, MN1,..., MP7, MN7). A first bias element (BMP23) for setting the plurality of pull-up output currents of MP7) and a second bias element (BMN22) for setting the plurality of pull-down output currents of the plurality of pull-down driving transistors (MN1... MN7). And a trimming circuit (Trimm) capable of setting the first bias current of the first bias element (BMP23) and the second bias current of the second bias element (BMN22) by external adjustment information (FIG. 5). FIG. 6).

  A semiconductor integrated circuit according to a more specific form of the present invention includes a central processing unit (12) for processing user personal information and an encryption key for encryption processing, and the personal information or encryption key for encryption processing. An internal memory (13, 14, 15) for storing data, an input / output unit (16) for data transfer with an external device, the central processing unit (12), the internal memory (13, 14, 15) and the input A power supply circuit (17) for supplying an operating voltage to the output unit (16) is provided inside the chip. The plurality of light receiving elements (PD1... PD7) are internal circuits including the central processing unit (12), the internal memories (13, 14, 15), the input / output unit (16), and the power supply circuit (17). (See FIG. 7).

  In a semiconductor integrated circuit according to a more specific form of the present invention, a security processing program is stored in the nonvolatile memory (13, 15) of the internal memory (13, 14, 15) (see FIG. 7).

  In the semiconductor integrated circuit according to a more specific form of the present invention, the security processing program is an authentication application for user identification (see FIG. 7).

  In a semiconductor integrated circuit according to a more specific form of the present invention, the plurality of pull-up drive signal lines (Lup1... Lup7) and the plurality of pull-down drive signal lines (Ldn1... Ldn7) are at least a part of the internal circuit. It is formed on the circuit (see FIG. 7).

  In a semiconductor integrated circuit according to a more specific form of the present invention, the plurality of light receiving elements (PD1... PD7) are distributed in the vicinity of a portion vulnerable to attack in the internal circuit (see FIG. 7).

  An IC card according to one embodiment of the present invention is embedded in a card substrate (30), an external interface (31) formed on the main surface of the card substrate (30), and the card substrate (30). The chip (32) of the semiconductor integrated circuit electrically connected to an external interface (31) (see FIG. 9).

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to the present invention, it is possible to easily test for disconnection of a plurality of wirings connected to a plurality of light receiving elements arranged on a chip of a semiconductor integrated circuit in order to protect against an attack caused by spot light irradiation. A semiconductor integrated circuit can be provided. Further, according to the present invention, it is possible to reduce output noise at the time of detecting light irradiation from a plurality of light receiving elements arranged on a chip of a semiconductor integrated circuit in order to protect against attack by spot light irradiation.

≪Configuration of IC card microcomputer≫
FIG. 5 is a circuit diagram showing the bias / drive / sense circuit 11 and photodiodes PD1... PD7 of the IC card microcomputer according to one embodiment of the present invention.

  As shown in the figure, the bias / drive / sense circuit 11 is connected to the first photodiode PD1 and the seventh photodiode PD7 among the seven photodiodes PD1... PD7. Although not shown, five photodiodes PD2 to PD6 from the second to the sixth are connected in the same manner as the bias / drive / sense circuit 11. The bias / drive / sense circuit 11 includes a first drive / sense circuit DR_SN1 and a seventh DR_SN7 of the seven drive / sense circuits DR_SN1... DR_SN7. Although not shown, five drive / sense circuits DR_SN2... DR_SN6 from the second to the sixth are similarly arranged in the bias / drive / sense circuit 11. One common bias circuit Bias_Cirt for supplying a bias voltage to the seven drive / sense circuits DR_SN 1... DR_SN 7 is arranged in the bias / drive / sense circuit 11.

In the common bias circuit Bias_Cirt, the constant current I ₀ from the constant current source is supplied to the P-channel MOS transistor BMP21 which is a diode-connected input transistor of the first current mirrors BMP21 and BMP22, and is generated by the diode-connected input transistor BMP21. The first bias voltage V1 is commonly supplied to the gates of the seven P-channel MOS transistors MP11... MP71 of the seven drive / sense circuits DR_SN1. A diode-connected N-channel MOS transistor BMN21 is connected to the drain of the P-channel MOS transistor BMP23 which is an output transistor of the first current mirrors BMP21 and BMP22, and the second bias voltage V2 generated by the N-channel MOS transistor BMN21 is 7 pieces. Commonly supplied to the gates of the seven N-channel MOS transistors MN11... MN71 of the drive / sense circuits DR_SN1. In the common bias circuit Bias_Cirt, the constant current 2I from the trimmed constant current source is supplied to the P-channel MOS transistor BMP23 which is a diode-connected input transistor of the second current mirrors BMP23 and BMP24, and the diode-connected input transistor BMP23. The generated third bias voltage V3 is commonly supplied to the gates of seven pull-up drive P-channel MOS transistors MP1... MP7 of the seven drive / sense circuits DR_SN1. The drain current of the P-channel MOS transistor BMP24, which is the output transistor of the second current mirrors BMP23 and BMP24, is supplied to the diode-connected N-channel MOS transistor BMN22. The fourth bias voltage V4 generated by the diode-connected N-channel MOS transistor BMN22 is commonly supplied to the gates of the seven pull-down drive N-channel MOS transistors MN1... MN7 of the seven drive / sense circuits DR_SN1. ing. The photodetection signals from the seven photodiodes PD1... PD7 are sensed by the seven CMOS inverters Inv1... Inv7 of the seven drive / sense circuits DR_SN1. The source of the P-channel MOS transistor MP12 of the first CMOS inverter Inv1 is connected to the power supply voltage Vdd via the P-channel MOS transistor MP11, while the source of the N-channel MOS transistor MN12 is grounded via the N-channel MOS transistor MN11. It is connected to the potential Vss. Accordingly, the rush current flowing through the first CMOS inverter Inv1 is limited by the P-channel MOS transistor MP11 and the N-channel MOS transistor MN11. The source of the P-channel MOS transistor MP72 of the seventh CMOS inverter Inv7 is connected to the power supply voltage Vdd via the P-channel MOS transistor MP71, while the source of the N-channel MOS transistor MN72 is grounded via the N-channel MOS transistor MN71. It is connected to the potential Vss. Accordingly, the rush current flowing through the seventh CMOS inverter Inv7 is limited by the P-channel MOS transistor MP71 and the N-channel MOS transistor MN71. The second CMOS inverter Inv2 to the sixth CMOS inverter Inv6 are configured in the same manner as the first CMOS inverter Inv1 and the seventh CMOS inverter Inv7.

  In the bias / drive / sense circuit 11 of FIG. 5, the channel width of the diode-connected N-channel MOS transistor BMN22 of the common bias circuit Bias_Cirt is N channels for seven pull-down drives of the seven drive / sense circuits DR_SN1. It is set to be twice the channel width of the MOS transistors MN1. In addition, the channel width of the diode-connected P-channel MOS transistor BMP23 of the common bias circuit Bias_Cirt is equal to the channel width of the P-channel MOS transistor BMP24 of the common bias circuit Bias_Cirt and the seven drive / sense circuits DR_SN1... DR_SN7. It is equal to the channel width of the pull-up drive P-channel MOS transistors MP1... MP7. As a result, the current sink capability of the seven pull-down drive N-channel MOS transistors MN1... MN7 of the seven drive / sense circuits DR_SN1... DR_SN7 becomes the current I, and the seven drive / sense circuits DR_SN1. The current supply capability of the pull-up drive P-channel MOS transistors MP1... MP7 is the current 2I.

  In the embodiment of the present invention shown in FIG. 5, the seven input terminals In1... In7 of the seven drive / sense amplifier circuits DR & SN_1... DR & SN_7 are connected to the connection points CN1. CN7 is connected to seven pull-down drive signal lines Ldn1... Ldn7. Further, all the anodes of the seven photodiodes PD1... PD7 are connected to the ground voltage Vss, and all the cathodes of the seven photodiodes PD1... PD7 are connected to the seven pull-up drive signal lines Lup1. The pull-down drive signal lines Ldn1... Ldn7 are connected. Also, the wiring distances of the plurality of wirings between the seven input terminals In1... In7 of the driving / sense amplifier circuits DR & SN_1... DR & SN_7 and the connection points CN1. 7 pull-up drive signal lines Lup1... Lup7 between the drains of the drive P-channel MOS transistors MP1... MP7 and the cathodes of the seven photodiodes PD1. It is set sufficiently shorter than the wiring distance of the seven pull-down drive signal lines Ldn1... Ldn7 between the drains of the transistors MN1... MN7 and the cathodes of the seven photodiodes PD1. As a result, the probability of disconnection of the former wiring can be made much lower than the probability of disconnection of the latter wiring due to the difference in wiring distance in the semiconductor manufacturing process.

  Accordingly, when all of the seven photodiodes PD1... PD7 are irradiated with light and the photocurrent Ipd of the seven photodiodes PD1... PD7 has a higher conductivity than the current I, the seven drive / sense amplifier circuits DR & SN_1. The voltages of the seven input terminals In1... In7 of DR & SN_7 become the ground voltage Vss. Also, seven input terminals of seven pull-down drive signal lines Ldn1... Ldn7 to which seven input terminals In1... In7 of seven drive / sense amplifier circuits DR & SN_1. The drive voltage of In1... In7 is also the ground voltage Vss.

  For example, when light Lgt by spot light irradiation is irradiated only to the first photodiode PD1 as the light receiving element, the photocurrent Ipd due to the reverse current of the PN junction of the first photodiode PD1 becomes the ground voltage Vss. The reverse current of the PN junction from the second photodiode PD2 to the seventh photodiode PD7 becomes a negligible minute current. When the photocurrent Ipd of the first photodiode PD1 becomes larger than the current I, the charge charged in the parasitic capacitance of the first photodiode PD1 is discharged. Then, the voltage of the input sense node In1 of the first CMOS inverter Inv1 is lowered from the power supply voltage Vdd to the ground voltage Vss, and the output OUT1 is changed from the low level to the high level. Since the charge charges of the parasitic capacitances of the second photodiode PD2 to the seventh photodiode PD7 are maintained, the outputs OUT2... OUT7 of the second CMOS inverter Inv2 to the seventh CMOS inverter Inv7 are at a low level. Maintained. The outputs OUT1... OUT7 are input to an OR circuit (not shown), and the entire operation of the IC card microcomputer is stopped by the high level output of the OR circuit. Accordingly, when at least one of the seven photodiodes PD1... PD7 is irradiated with light, the entire operation of the IC card microcomputer is stopped.

  For example, in FIG. 5, one of the seven pull-up drive signal lines Lup1... Lup7 and the seven pull-down drive signal lines Ldn1... Ldn7 is disconnected from the drive / sense circuit 11. Assuming that However, the wiring distance between the seven input terminals In1... In7 of the seven drive / sense amplifier circuits DR & SN_1... DR & SN_7 and the seven pull-down drive signal lines Ldn1. Therefore, the electrical connection between both wirings at the plurality of connection points CN1... CN7 is maintained. Then, among the seven input terminals In1... In7 of the seven drive / sense amplifier circuits DR & SN_1... DR & SN_7, one input terminal corresponding to one drive signal line in a disconnected state outside the drive / sense circuit 11 Is driven to the ground voltage Vss by one pull-down drive signal line corresponding to the pull-down drive signal lines Ldn1... Ldn7 in the drive / sense circuit 11. As a result, an abnormality detection signal similar to the abnormality detection signals from the seven photodiodes PD1... PD7 by spot light irradiation can be obtained when the drive signal line is disconnected outside the drive / sense circuit 11.

  In FIG. 5, a trimming circuit Trimm is a constant current supplied to a P-channel MOS transistor BMP23 which is a diode-connected input transistor of the second current mirror BMP23 and BMP24 of the common bias circuit Bias_Cirt of the bias / drive / sense circuit 11. It has a function of trimming a current value of 2I to an accurate value. The P-channel MOS transistor TMP25 as a resistor connected to the power supply by the trimming circuit Trimm exhibits large variations in threshold voltage Vth and conductance gm due to the manufacturing process of the semiconductor integrated circuit. This variation causes variations in the current value of the constant current 2I. Therefore, in the mass production of the IC card microcomputer, while monitoring the current of the constant current 2I supplied to the P-channel MOS transistor BMP23 by the external tester, the on / off information of the plurality of switches SW1. Ask for. This optimum switch on / off information can be stored in a nonvolatile manner in the EEPROM 15 shown in FIG.

  FIG. 6 is a circuit diagram showing a bias / drive / sense circuit 11 and photodiodes PD1... PD7 of an IC card microcomputer according to another embodiment of the present invention.

  The difference between the embodiment of FIG. 5 and the embodiment of FIG. 5 will be described below. In the embodiment of FIG. 6, contrary to the embodiment of FIG. 5, all the cathodes of the seven photodiodes PD1... PD7 are connected to the operating power supply voltage Vdd, and all the anodes of the seven photodiodes PD1. It is connected to seven pull-up drive signal lines Lup1... Lup7 and seven pull-down drive signal lines Ldn1. Also, seven pull-up drive signal lines Lup1 connected to seven input terminals In1 ... In7 of seven drive / sense amplifier circuits DR & SN_1 ... DR & SN_7 at connection points CN1 ... CN7 inside the drive / sense circuit 11. The drive voltages of the seven input terminals In1... In7 by Lup7 are also the operating power supply voltage Vdd. Further, in the bias / drive / sense circuit 11 of FIG. 6, the channel width of the diode-connected N-channel MOS transistor BMN22 of the common bias circuit Bias_Cirt is 7 for the pull-down drive of the 7 drive / sense circuits DR_SN1... DR_SN7. It is set equal to the channel width of the N-channel MOS transistors MN1. The channel width of the diode-connected P-channel MOS transistor BMP23 of the common bias circuit Bias_Cirt and the channel width of the P-channel MOS transistor BMP24 of the common bias circuit Bias_Cirt are seven drive / sense circuits DR_SN1... DR_SN7. Is set to twice the channel width of the pull-up driving P-channel MOS transistors MP1... MP7. As a result, the current sink capability of the seven pull-down drive N-channel MOS transistors MN1... MN7 in the seven drive / sense circuits DR_SN1... DR_SN7 becomes the current 2I, and the seven drive / sense circuits DR_SN1. The current supply capability of the pull-up driving P-channel MOS transistors MP1 to MP7 is the current I.

  For example, when the light Lgt by spot light irradiation is irradiated only to the first photodiode PD1 as the light receiving element, the photocurrent Ipd due to the reverse current of the PN junction of the first photodiode PD1 becomes the operating power supply voltage Vdd. The reverse current of the PN junction from the second photodiode PD2 to the seventh photodiode PD7 becomes a negligible minute current. When the photocurrent Ipd of the first photodiode PD1 becomes larger than the current I, the parasitic capacitance of the first photodiode PD1 is charged from the ground voltage Vss to the operating power supply voltage Vdd. Then, the voltage at the input sense node In1 of the first CMOS inverter Inv1 increases from the ground voltage Vss to the operating power supply voltage Vdd, and the output OUT1 changes from high level to low level. Since the ground voltage Vss of the parasitic capacitance of the second photodiode PD2 to the seventh photodiode PD7 is maintained, the outputs OUT2... OUT7 of the second CMOS inverter Inv2 to the seventh CMOS inverter Inv7 are high. Maintained at level.

  For example, in FIG. 6, one of the seven pull-up drive signal lines Lup1... Lup7 and the seven pull-down drive signal lines Ldn1... Ldn7 is disconnected outside the drive / sense circuit 11. Assuming that Then, among the seven input terminals In1... In7 of the seven drive / sense amplifier circuits DR & SN_1... DR & SN_7, the voltage of one input terminal corresponding to one drive signal line in the disconnected state is the drive / sense circuit 11. Are driven to the operating power supply voltage Vdd by one corresponding pull-up drive signal line Lup1... Lup7. As a result, an abnormality detection signal similar to the abnormality detection signals from the seven photodiodes PD1... PD7 by spot light irradiation can be obtained when the drive signal line is disconnected outside the drive / sense circuit 11.

  FIG. 7 is a diagram showing a chip layout of an IC card microcomputer using the drive / sense circuit 11 according to the embodiment of FIG. 5 or FIG.

  As shown in the figure, on a chip 10 of an IC card microcomputer, a bias / drive / sense circuit 11, a central processing unit (CPU) 12, a read only memory (ROM) 13, and a random access memory (RAM) are provided. 14, an electrically writable / erasable nonvolatile memory (EEPROM) 15, an input / output unit (I / O) 16, and a power supply circuit (Pwr_Spy_Cirt) 17 are arranged. The power supply circuit 17 supplies operating voltages to the CPU 12, ROM 13, RAM 14, EEPROM 15, and input / output unit 16 based on an external power supply voltage Vdd and an external ground voltage Vss supplied from the outside. The input / output unit 16 outputs a data transfer synchronization clock CLK to an external device (not shown). The input / output unit 16 inputs or outputs data DATA from an external device in synchronization with the data transfer synchronization clock CLK. In addition, at least one of the ROM 13 and the EEPROM 15 stores a security processing program such as an authentication application for user identification.

  Photodiodes PD1, PD2, PD3, PD4, PD5, which are light-receiving elements that cause the entire IC card microcomputer to stop operating in the vicinity of weak circuit portions inside the CPU 12, ROM 13, RAM 14, EEPROM 15, I / O 16, and power supply circuit 17. Seven PD6 and PD7 are arranged. The photodiodes PD1, PD2, PD3, PD4, PD5, PD6, and PD7 each have seven pull-up drive signal lines Lup1, Lup2, Lup3, Lup4, Lup5, Lup6, and Lup7 and seven pull-down drive signal lines Ldn1 and Ldn2. , Ldn3, Ldn4, Ldn5, Ldn6, and Ldn7 are connected. The CPU 12 is disposed below the six pull-up drive signal lines Lup2, Lup3, Lup4, Lup5, Lup6, Lup7 and the six pull-down drive signal lines Ldn2, Ldn3, Ldn4, Ldn5, Ldn6, and Ldn7. Yes.

  FIG. 8 is a diagram showing a cross section of a chip of an IC card microcomputer according to one embodiment of the present invention.

  As shown in the figure, the chip of this IC card microcomputer includes, for example, a P-type silicon semiconductor substrate 20, an N-type element isolation region 21, a P-type well region 22, an N-type well region 23, a high impurity concentration N-type region. 24, a high impurity concentration P-type region 25 is included. Either a PN junction between the P-type well region 22 and the high impurity concentration N-type region 24 or a PN junction between the high impurity concentration P-type region 25 and the N-type well region 23 has seven photodiodes PD1. , PD2, PD3, PD4, PD5, PD6, and PD7.

  FIG. 9 is a diagram illustrating an IC card according to an embodiment of the present invention.

  As shown in the figure, this IC card includes a card substrate 30 and an external interface 31 composed of eight contact electrodes formed on the main surface of the card substrate 30. Furthermore, the IC card microcomputer chip 32 shown in FIGS. 7 and 8 is embedded in the card substrate 30 behind the external interface 31, and the chip 32 is electrically connected to the external interface 31. .

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the plurality of light receiving elements are not limited to photodiodes, and for example, phototransistors, photoMOS transistors, and the like can be used.

  5 and 6, seven input terminals In1... In7 and seven pull-ups of seven drive / sense amplifier circuits DR & SN_1... DR & SN_7 at connection points CN1. Drive signal lines Lup1 ... Lup7 or seven pull-down drive signal lines Ldn1 ... Ldn7 are connected. However, the connection points CN1... CN7 can be located near the outside of the drive / sense circuit 11.

  FIG. 10 is a diagram showing a chip layout of an IC card microcomputer according to another embodiment of the present invention using the drive / sense circuit 11 of FIG.

  As shown in the figure, the connection points of seven input terminals In1... In7 and seven pull-down drive signal lines Ldn1... Ldn7 of the drive and sense amplifier circuits DR & SN_1. CN1... CN7 are arranged inside the wiring channel region 18 near the outside of the drive / sense circuit 11. Also in the embodiment of FIG. 10, seven connection points CN1... CN7 arranged in the wiring channel region 18 and seven input terminals In1... In7 of seven drive / sense amplifier circuits DR & SN_1. The wiring distance is 7 pulls between the drains of 7 pull-up drive transistors MP1 ... MP7 of 7 drive / sense amplifier circuits DR & SN_1 ... DR & SN_7 and the cathodes of 7 photodiodes PD1 ... PD7. Up drive signal line Lup1 ... Lup7 wiring distance and seven drive / sense amplifiers DR & SN_1 ... DR & SN_7 seven pull-down drive transistors MN1 ... MN7 drains and seven photodiodes PD1 ... PD7 cathodes 7 pull-down drive signal lines Ldn1... Ldn7 wiring distance It is also set short enough. The seven pull-up drive signal lines Lup1... Lup7 and the seven pull-down drive signal lines Ldn1... Ldn7 having a long wiring distance outside the drive / sense circuit 11 have a high probability of disconnection, but are arranged in the wiring channel region 18. The probability of the disconnection of the wiring having a short wiring distance between the seven connection terminals CN1... CN7 and the seven input terminals In1... In7 of the seven drive / sense amplifier circuits DR & SN_1.

  Therefore, also in FIG. 10, any one of the seven pull-up drive signal lines Lup1 ... Lup7 and the seven pull-down drive signal lines Ldn1 ... Ldn7 is connected to the drive / sense circuit 11 and the wiring channel region 18. Of the seven drive / sense amplifier circuits DR & SN_1... DR & SN_7, the voltage at one input terminal corresponding to one drive signal line in the external disconnection state. Are driven to the ground voltage Vss by one pull-down drive signal line corresponding to the pull-down drive signal lines Ldn 1... Ldn 7 in the drive / sense circuit 11. As a result, an abnormality detection signal similar to the abnormality detection signals from the seven photodiodes PD1... PD7 by spot light irradiation can be obtained when the drive signal line is disconnected outside the drive / sense circuit 11.

  In addition, not only the connection points CN1... CN7 but also data signal lines and address signal lines from the CPU 12 to the peripheral ROM 13, RAM 14, EEPROM 15, and input / output unit 16 are arranged in the wiring channel region 18 of FIG. You can also.

  In addition, a non-volatile large-capacity file memory such as a flash memory chip and a memory controller chip can be arranged in the IC card together with the chip of the IC card microcomputer. The IC card microcomputer of the above-described embodiment exhibits high security performance when performing electronic payment of a usage fee when downloading multimedia information such as music and moving images to the nonvolatile large-capacity file memory.

  Further, the external interface of the IC card microcomputer is not limited to the contact type, and may be a non-contact type external interface using infrared rays or RF signals.

  Further, not only the entire operation of the IC card microcomputer but also the operation of the high security function of the IC card microcomputer may be stopped according to the detection result of the light irradiation.

FIG. 1 is a diagram showing a chip layout of an IC card microcomputer studied by the present inventors prior to the present invention. FIG. 2 is a circuit diagram showing a bias / drive / sense circuit and a photodiode of an IC card microcomputer studied by the present inventors prior to the present invention. FIG. 3 is a circuit diagram showing a bias / drive / sense circuit and a photodiode of another IC card microcomputer studied by the present inventors prior to the present invention. FIG. 4 is a diagram showing a chip layout of another IC card microcomputer studied by the present inventors prior to the present invention. FIG. 5 is a circuit diagram showing a bias / drive / sense circuit and a photodiode of an IC card microcomputer according to one embodiment of the present invention. FIG. 6 is a circuit diagram showing a bias / drive / sense circuit and a photodiode of an IC card microcomputer according to another embodiment of the present invention. FIG. 7 is a diagram showing a chip layout of an IC card microcomputer using the drive / sense circuit according to the embodiment of FIG. 5 or FIG. FIG. 8 is a diagram showing a cross section of a chip of an IC card microcomputer according to one embodiment of the present invention. FIG. 9 is a diagram illustrating an IC card according to an embodiment of the present invention. FIG. 10 is a diagram showing a chip layout of an IC card microcomputer according to another embodiment of the present invention using the drive / sense circuit 11 of FIG.

Explanation of symbols

PD1... PD7 Multiple light receiving elements 11 Drive / sense circuits MP1, MN1... MP7, MN7 Multiple drive circuits MP12, MN12... MP72, MN72 Multiple sense amplifier circuits Vdd Operating power supply voltage MP1. Base voltages MN1... MN7 Plural pull-down driving transistors Lup1... Lup7 Plural pull-up driving signal lines Ldn1.

Claims (12)

A drive / sense circuit including a plurality of light receiving elements, a plurality of drive circuits for driving the plurality of light receiving elements, and a plurality of sense amplifier circuits for amplifying detection signals of light irradiation from the plurality of light receiving elements. And
The plurality of driving circuits include a plurality of pull-up driving transistors connected to an operating power supply voltage and a plurality of pull-down driving transistors connected to a base voltage,
The plurality of output terminals of the plurality of pull-up driving transistors of the plurality of driving circuits are connected to a plurality of one ends of the plurality of light receiving elements via a plurality of pull-up driving signal lines, and A plurality of output terminals of the plurality of pull-down driving transistors are connected to the plurality of one ends of the plurality of light receiving elements via a plurality of pull-down driving signal lines,
The other ends of the plurality of light receiving elements are connected to one of the operating power supply voltage and the base voltage,
The plurality of input terminals of the plurality of sense amplifier circuits are connected to one of the plurality of pull-up drive signal lines and one of the plurality of pull-down drive signal lines in or near the drive / sense circuit. The driving voltage by the plurality of signal lines is set to be substantially equal to the one of the operating power supply voltage and the base voltage to which the other ends of the plurality of light receiving elements are connected. Semiconductor integrated circuit.   The plurality of connection terminals in which the plurality of input terminals of the plurality of sense amplifier circuits are connected to the plurality of signal lines in or near the drive / sense circuit and the plurality of sense amplifier circuits. The wiring distance between the plurality of wirings between the plurality of output terminals of the plurality of pull-up driving transistors of the plurality of driving circuits and the one end of the plurality of light receiving elements. The plurality of pull-downs between the plurality of pull-up driving signal lines and the plurality of output terminals of the plurality of pull-down driving transistors of the plurality of driving circuits and the plurality of one ends of the plurality of light receiving elements. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is set sufficiently shorter than a wiring distance of the drive signal line.   The plurality of other ends of the plurality of light receiving elements are connected to the base voltage, and the plurality of input terminals of the plurality of sense amplifier circuits are connected to the plurality of pull-down drives in or near the drive / sense circuit. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to a signal line.   The plurality of other ends of the plurality of light receiving elements are connected to the operation power supply voltage, and the plurality of input terminals of the plurality of sense amplifier circuits are connected to the plurality of pulls in or near the drive / sense circuit. 3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is connected to an up drive signal line.   The plurality of pull-up drive signal lines supply a plurality of pull-up output currents from the plurality of pull-up drive transistors of the plurality of drive circuits to the plurality of light receiving elements, while the plurality of pull-down drive signal lines are 5. The semiconductor integrated circuit according to claim 3, wherein a plurality of pull-down output currents of the plurality of pull-down driving transistors are supplied from the plurality of light receiving elements.   The driving / sense circuit includes: a first bias element that sets the plurality of pull-up output currents of the plurality of pull-up driving transistors of the plurality of driving circuits; and the plurality of pull-downs of the plurality of pull-down driving transistors. 6. A second bias element for setting an output current, and a trimming circuit capable of setting a first bias current of the first bias element and a second bias current of the second bias element by external adjustment information. The semiconductor integrated circuit as described. Central processing unit for processing user personal information and encryption key for encryption processing, internal memory for storing the personal information or the encryption key for encryption processing, and input / output for data transfer with external devices A chip, and a power supply circuit for supplying an operating voltage to the unit, the central processing unit, the internal memory, and the input / output unit;
7. The semiconductor integrated circuit according to claim 5, wherein the plurality of light receiving elements are distributed in an internal circuit including the central processing unit, the internal memory, the input / output unit, and the power supply circuit. .   The semiconductor integrated circuit according to claim 7, wherein a security processing program is stored in the nonvolatile memory of the internal memory.   The semiconductor integrated circuit according to claim 8, wherein the security processing program is an authentication application for user identification.   The semiconductor integrated circuit according to claim 5, wherein the plurality of pull-up drive signal lines and the plurality of pull-down drive signal lines are formed on at least a part of the internal circuit. .   11. The semiconductor integrated circuit according to claim 5, wherein the plurality of light receiving elements are distributed in the vicinity of a portion vulnerable to attack in the internal circuit.   The card board, an external interface formed on a main surface of the card board, and embedded in the card board and electrically connected to the external interface. An IC card comprising a semiconductor integrated circuit chip.

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