JP2007299909A - Semiconductor wafer imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer imaging apparatus in which variation in precision of alignment can be reduced regardless of the kind of semiconductor wafer and optimal contrast can be obtained. <P>SOLUTION: An amplifying circuit and a controller are provided as a light source control circuit for selecting at least one of light emitting diodes LD1-LD3 having different wavelength, lighting a selected light emitting diode LD, and regulating its quantity of light; and the illumination area of a semiconductor wafer 18 and a mask 40 arranged to be superimposed thereon is irradiated with light emitted from the light emitting diode LD selected by the light source control circuit. Since the semiconductor wafer 18 and the mask 40 can be irradiated with light of different waveform, and the quantity of irradiating light can be regulated; variation in precision of alignment can be reduced regardless of the kind of the semiconductor wafer 18. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention irradiates light to a wafer mark for positioning provided on a semiconductor wafer and a mask mark formed on a mask arranged so as to overlap the semiconductor wafer, and enters the reflected light so that the wafer mark and the mask mark are The present invention relates to a semiconductor wafer image pickup apparatus that picks up an image and processes image pickup data obtained by the image pickup to recognize the position of a wafer mark.

  Conventionally, as a positioning device used in, for example, a semiconductor exposure apparatus, an ion implantation apparatus, an assembly / inspection apparatus, a precision machine tool, etc., a positioning object is placed (held) on a table that can be positioned with high accuracy. Done. In a semiconductor exposure apparatus, an ion implantation apparatus, and the like, a semiconductor wafer which is a positioning object is subjected to a mask having a predetermined pattern for each section (one chip). In such a case, the positioning mark (wafer mark) provided on each section of the semiconductor wafer is usually illuminated with a light emitting element and imaged with an imaging element such as a CCD camera, and the error between the detected position and the reference position Based on the above, positioning is performed.

  By the way, when a silicon wafer is used as the semiconductor wafer, the positioning mark is often composed of a silicon oxide film, and the contrast of the positioning mark is determined by the wavelength of illumination light and the thickness of the silicon oxide film.

  When illuminating a semiconductor wafer using a light emitting element such as an LED, the conventional technique uses a single wavelength LED. For example, the positioning mark thickness varies from lot to lot, and the appearance of the positioning mark ( Even in the same semiconductor wafer, conditions may be different between the middle portion and the peripheral portion, and the alignment accuracy may vary. The present invention has been made in view of the above-described problems of the prior art, and an object thereof is to obtain an optimum contrast regardless of the semiconductor wafer.

  In order to achieve the above object, the present invention provides a semiconductor wafer, an illuminating means for irradiating light to an imaging region of a mask arranged to overlap the semiconductor wafer, and the semiconductor wafer and the mask from the illuminating means. An imaging means for imaging a positioning wafer mark formed on the semiconductor wafer and a mask mark formed on the mask by inputting reflected light of the irradiated light on the semiconductor wafer, and imaging data obtained by imaging by the imaging means Recognizing means for processing and recognizing a relative position of the wafer mark to the mask mark, and the illuminating means includes a plurality of light sources that emit light having different wavelengths, and at least one of the plurality of light sources. And a light source control circuit for turning on the selected light source and adjusting the amount of light.

  According to the above configuration, the imaging regions of the semiconductor wafer and the mask can be irradiated with light having different wavelengths, and the amount of irradiation light can be adjusted. Therefore, the alignment accuracy can be improved regardless of the type of the semiconductor wafer. Variations can be reduced and an optimum contrast can be obtained. In the present invention, the plurality of light sources may be composed of a plurality of LEDs having different wavelengths. In this case, the amount of heat generation is reduced and energy saving can be achieved compared to when a halogen lamp is used as the light source.

  According to the present invention, variations in alignment accuracy can be reduced regardless of the type of semiconductor wafer, and an optimum contrast can be obtained.

  FIG. 1 shows a semiconductor positioning device (hereinafter simply referred to as a positioning device) 10 according to the present embodiment. In the positioning device 10, a support column 14 is erected with respect to the surface plate 12, and a top plate 16 is attached to the upper end of the support column 14 to constitute a housing of the positioning device 10. The positioning device 10 serves to position the semiconductor wafer 18 with respect to the semiconductor wafer 18. A workpiece positioning stage unit 20 and a mask stage unit 22 are installed on the surface plate 12 of the positioning apparatus 10.

  The workpiece positioning stage unit 20 includes a base 24, an X-axis direction sliding device 28 provided on the base 24 and supporting the first slider 26 so as to be slidable in the X-axis direction, and the first slider 26 as the X-axis. And an X-axis direction driving device 29 for driving in the direction. A second slider 30 is provided on the first slider 26, and the second slider 30 is supported by a Y-axis direction sliding device 32 so as to be slidable in the Y-axis direction. Driven in the Y-axis direction by an axial drive device. Further, the second slider 30 supports a work stage 34 as a sample base such as the semiconductor wafer 18 positioned in the X-axis direction and the Y-axis direction. A wafer chuck 36 that holds the semiconductor wafer 18 is attached to the work stage 34.

  The semiconductor wafer 18 is fixed while being supported by the wafer chuck 36. The wafer chuck 36 has a mechanism capable of fine adjustment of the six degrees of freedom (X, Y, Z axis directions and rotations about the respective axes) of the chucked semiconductor wafer 18. With the workpiece positioning stage unit 20 having the above-described configuration, the wafer chuck 36 can perform step feed in the XY plane and fine position and posture adjustment with six degrees of freedom.

  Above the work stage 34, a mask chuck 38 that constitutes a part of the mask stage unit 22 is disposed opposite to the second stage 30. The mask chuck 38 holds the mask 40 on the surface facing the wafer chuck 36. The mask chuck 38 is supported by a mask θ-axis base 42 and can be adjusted in the θ-axis direction.

  The mask θ-axis base 42 is supported by the mask Z-axis direction moving mechanism 44. Further, the mask Z-axis direction moving mechanism 44 is supported by a mask XY table 46. The mask XY table 46 has the same configuration as that of the moving table unit 20, and therefore the description of the configuration is omitted. With this mask stage portion 22, the mask 40 can be adjusted in the respective axial directions of XYZ-θ.

  The top plate 16 constituting the casing of the positioning device 10 is provided with an opening 16A at the center (around the reference axis on which the semiconductor wafer 18 is positioned). An alignment unit 50 for detecting the positioning wafer marks W1 to W3 (see FIG. 2) provided on the semiconductor wafer 18 and adjusting the position of the semiconductor wafer 18 on the work stage 34 is attached to the top plate 16. ing. Although only one set is shown in FIG. 1, a total of three alignment units 50 are arranged corresponding to each wafer mark.

  As shown in FIG. 2, on the surface of a semiconductor wafer 18 that is a silicon substrate, for example, a large number of pattern areas 18A of about 30 mm × 30 mm are arranged in a matrix. For example, isolation regions 18B having a width of several tens of microns are formed in a lattice shape between the pattern regions 18A for subsequent chip cutting. Three wafer marks W1 to W3 per region are formed in advance in a linear shape by silicon oxide films at appropriate locations in the isolation region 18B. In the illustrated example, the wafer marks W1 and W2 are generated in the Y-axis direction, and the wafer mark W3 is generated in the X-axis direction. In FIG. 2, only the wafer marks W1 to W3 corresponding to the hatched central pattern area 18A are shown, but the wafer marks W1 to W3 are similarly arranged around all the patterns.

  Since the silicon oxide film portion has a lower reflectivity than the surrounding silicon portion and is dark, the wafer marks W1 to W3 can be observed. Further, the wafer marks W1 to W3 are not limited to the X-axis direction and the Y-axis direction, and may be provided with marks in a direction of 45 ° with respect to the X-axis and the Y-axis.

  The wafer marks W1, W2, and W3 can be obtained by making the linear silicon oxide film flush with the surrounding portion or slightly raised, but instead, silicon oxide is formed on the semiconductor wafer 18. It is good also as a pattern which makes the linear pattern of a film | membrane project. Or, conversely, the wafer marks W1, W2, and W3 may be made of silicon and surrounded by a silicon oxide film. The alignment unit 50 detects the wafer marks W1, W2, and W3, thereby recognizing the position of the semiconductor wafer 18 and generating data for executing positioning correction.

  FIG. 3 is an explanatory diagram for explaining the mask 40. 3A is a plan view, and FIG. 3B is a cross-sectional view in the AA direction of FIG. 3A. The mask 40 is a stencil mask, and corresponds to a pattern to be formed in a circular shape and a relatively thick peripheral portion 40A, a relatively thin membrane portion 40B in the inner region, and a central portion of the membrane portion 40B. A mask pattern portion 40C having a pattern, mask marks (through holes) M1 to M3 formed at positions corresponding to the wafer marks W1 to W3 of the semiconductor wafer 18 around the mask pattern portion 40C, and the peripheral portion 40A. It has a notch portion 40D for pre-alignment and a global alignment mark 40E for coarse adjustment.

  The mask 40 is made of, for example, silicon and has a diameter of 4 inches, a peripheral portion 40A having a thickness of 0.5 mm, and a membrane portion 40B in the central region having a thickness of 10 μm. Further, the mask marks M1 to M3 of the mask 40 of the present embodiment are constituted by an assembly of a plurality of through holes as shown in FIG.

  FIG. 4 shows an enlarged view of one mask mark (here, mask mark M1) for the visual field area 54A of the CCD camera 54 (see FIG. 1). The visual field area 54 </ b> A of the CCD camera 54 is irradiated with uniform light by illumination from the illumination light source unit 52.

  The first through hole 60 is an area where the wafer mark W1 is positioned by rough adjustment, and the longitudinal dimension is the same as the dimension (vertical dimension) of the left side along the left side of the first through hole 60. A vertically long second through hole 62 is provided. Further, on the right side of the first through hole 60, third to fifth through holes 64, 66, 68 are provided, and these are arranged in a column. The vertical dimension of the third to fifth through holes 64, 66, and 68 and the dimension obtained by adding these gaps are the same as the dimension (vertical dimension) of the first right side. Thereby, the area | region surrounding the 1st thru | or 5th through-holes 60, 62, 64, 66, 68 becomes a rectangular shape (refer the dashed-dotted line area | region M1 (M2, M3) of FIG. 4).

  Here, the second to fifth through holes 62, 64, 66, and 68 are each formed with a partition portion having a line width between the adjacent through holes. As shown in FIG. 4, the partition 72 between the through holes 64 and 66 is set so as to overlap the shadow S portion of the mask 40 in the exposed portion of the semiconductor wafer 18 as viewed from the CCD camera 54.

  Further, the partition part 73 between the through holes 66 and 68 is arranged so that the shadow of the partition part 73 formed on the semiconductor wafer 18 is located in the through hole 68 and viewed from the CCD camera 54. The shadow and the partition 72 are set to be in focus as much as possible at the same time. Since the thickness of the membrane portion 40B of the mask 40 and the mounting angle α (see FIG. 5) of the alignment unit 50 are known, these conditions are satisfied when the gap g between the mask 40 and the semiconductor wafer 18 matches the set value. On the basis of this, by setting the distance between the partition 72 and the partition 73 to a predetermined geometrically determined value, “the state where the shadow of the partition 73 and the partition 72 are in focus as much as possible when viewed from the CCD camera 54 is achieved. Is required.

  The partition part 70 between the first through hole 60 and the second through hole 62 and the partition part 71 between the first through hole 60 and the third through hole 64 are formed on the wafer mark W1 with respect to the mask mark M1. In FIG. 4, it is used as a reference for obtaining the horizontal relative position. In the present embodiment, the partition portion 70 is used to detect a positional shift amount (shift amount) on one side (here, the X-axis direction) of the entire mask mark M1 in the plane direction. When the image is captured by the CCD camera 54, the partition 70 has a low density with a large difference from the density of the first through hole 60 and the second through hole 62 (dark due to the shadow S caused by the mask 40). (Bright) image. Further, the both sides of the thin partition portion 70 are darkened, and this also enables the position of the partition portion 70 to be detected with high accuracy. Therefore, the dimension A from the peripheral edge (left end in FIG. 4) of the visual field area 54A of the CCD camera 54 to the center line of the partition section 70 can be accurately read.

  On the other hand, the partition 72 between the third through-hole 64 and the fourth through-hole 66 is used to obtain the gap g, and in the present embodiment, the entire plane of the mask mark M1. It is also used to detect a positional shift (shift amount) in the other direction (here, the Y-axis direction), and when the image is taken by the CCD camera 54, the partition portion 72 has a third through hole. With respect to the density of 64 and the fourth through-hole 66 (dark due to the shadow S caused by the mask 54), the image has a low density (bright) with a large difference. Further, the both sides of the thin partition portion 72 are darkened, and this also enables the position of the partition portion 72 to be detected with high accuracy. Therefore, the dimension B from the peripheral edge (left end in FIG. 4) of the visual field area 54A of the CCD camera 54 to the center line of the partition portion 72 can be accurately read.

  By detecting the dimension A and the dimension B, the relative positional relationship between the visual field area 54A of the CCD camera 54 and the mask mark M1 can be recognized. By performing the adjustment, the relative positional relationship can be always maintained constant.

  The position adjustment is executed by moving the CCD camera 54. Therefore, as shown in FIG. 1, the imaging unit 56 on the top plate 16 is supported by a camera XY table 74. The camera XY table 74 has the same configuration as that of the positioning stage unit 20 (see FIG. 1) described above, and a description of the configuration is omitted.

  As shown in FIG. 1, the alignment unit 50 includes an illumination light source unit 52 using a plurality of light emitting diodes (LEDs) LD1 to LD3 as a light source, an imaging optical system 53 including a plurality of lenses, and a CCD camera 54. Part 56. As shown in FIG. 6, the illumination light source unit 52 is a light source having three different light emitting diodes LD1 to LD3 that emit light of three primary colors, for example, and a light emitting element having different wavelengths. And amplifying circuit 52a for adjusting the amount of light, and at least one of the three types of light emitting diodes LD1 to LD3 is selected for the amplifying circuit 52a, and the amount of light of the selected light emitting diode is adjusted. And a control device (for example, a personal computer) 52b that outputs a digital signal including information for the purpose.

 In this case, the amplifying circuit 52a and the control device 52b function as a light source control circuit that selects at least one of the three types of light emitting diodes LD1 to LD3, turns on the selected light emitting diode LD, and adjusts the amount of light. The illumination light source unit 52 including three types of light sources and a light source control circuit is provided for the imaging region (illumination area) of the semiconductor wafer 18 and the imaging region (illumination area) of the mask 40 arranged so as to overlap the semiconductor wafer 18. Thus, the illumination means for irradiating light is configured. A plurality of laser diodes having different wavelengths may be used instead of the plurality of light emitting diodes LD1 to LD3. Further, when adjusting the light quantity of each of the light emitting diodes LED1 to LD3, a plurality of volumes are provided between each of the light emitting diodes LD1 to LD3 and a plurality of drive circuits that drive and drive the light emitting diodes LD1 to LD3. By manually operating the volume, the light amounts of the light emitting diodes LD1 to LD3 can be individually adjusted.

  Note that the sensor is not limited to the CCD, and may be replaced by any camera provided with a sensor that can obtain imaging data capable of performing known image processing. Illumination light emitted from the illumination light source unit 52 by arranging the optical axis of the illumination light source unit 52 and the optical axis of the CCD camera 54 of the imaging unit 56 so as to be symmetric with respect to the normal of the surface of the wafer mark W1. Is reflected by the wafer mark W1 and becomes incident light of the CCD camera 54 of the imaging unit 56. Since wafer marks W2 and W3 have the same configuration as described above (that is, a total of three alignment units 50 are arranged on top plate 16), description of the configuration is omitted.

  The position of the mask 40 is coarsely adjusted in advance by observing the global alignment mark 40E (see FIG. 3), and the position of the work stage 34 is coarsely adjusted using a predetermined reference on the semiconductor wafer 18. Accordingly, when the mask pattern portion 40C is positioned so as to face the position where the pattern of the semiconductor wafer 18 is transferred by step feed, the wafer mark W1 of the semiconductor wafer 18 is positioned in the through hole 60 of the mask pattern M1. Adjust as follows. Further, with the pattern portion 40C of the mask 40 facing one pattern region 18A on the semiconductor wafer 18, the mask mark M1 of the mask 40 and the wafer mark W1 are simultaneously observed by the CCD camera 54. For example, the mask mark The wafer mark W1 of the semiconductor wafer 18 is present at the center of M1 (specifically, the center of the first through hole 60 in the horizontal direction in FIG. 4), that is, the wafer mark W1 is separated from the partitions 70 and 71. The work stage 34 is finely adjusted so as to be positioned at an equal distance.

  As shown in FIG. 1, the illumination light source unit 52 that constitutes a part of the alignment unit 50 is housed in a casing 76 and fixedly arranged on the top plate 16. The casing 76 is provided with a holder (not shown) that holds the light emitting diodes LD1 to LD3, and maintains the optical axis to the mask 40 as described above.

  As shown in FIGS. 1 and 5, light (usually diffused light) emitted from a light emitting diode LD selected from among the light emitting diodes LD1 to LD3 is appropriately reflected by means for guiding the light onto a common optical orbit ( (Not shown) and a plurality of lenses arranged in the common optical axis direction, a glass rod for illuminating a wider range with uniform brightness, etc. The area including the mask mark M1 (illumination area in FIG. 4) is illuminated almost uniformly with the light quantity adjusted.

According to this embodiment, the imaging regions (illumination areas) of the semiconductor wafer 18 and the mask 40 can be irradiated with light having different wavelengths, and the amount of irradiation light can be adjusted. Variations in alignment accuracy can be reduced regardless of the type of the image, and an optimum contrast can be obtained.
For example, if there is a difference in the darkness (density) of the wafer mark W1 for each lot of the semiconductor wafers 18, even if there is a difference in brightness depending on the position on the semiconductor wafer 18, the irradiation light as described above can be obtained. By adjustment, the wafer mark W1 can always be detected with the optimum contrast. As the light source, a two-color light emitting LED may be used instead of the light emitting diodes LD1 to LD3.

  Further, a halogen lamp (bulb) can be used as the light source instead of the light emitting diodes LD1 to LD3. However, in order to irradiate a semiconductor wafer with light having different wavelengths using a halogen lamp, an optical filter corresponding to the wavelength is required, and the optical filter must be replaced according to the wavelength, and the replacement work becomes troublesome. . Moreover, it is impossible to prepare a large number of optical filters according to the wavelength. In addition, since the halogen bulb has a larger light loss than light emitting elements such as LEDs, a large bulb is required to emit the same amount of light, and energy is consumed as the amount of heat generated increases.

  On the other hand, if the light emitting diodes LD1 to LD3, which are light emitting elements, are used as the light source, the designated light emitting diode LD can be selected by digital control, and energy saving can be achieved because it is compact and generates a small amount of heat. In addition, an arbitrary color can be selected from a large number of colors.

It is an illumination figure which shows the positioning device which concerns on embodiment of this invention. It is a top view of a semiconductor wafer, and is a top view which shows the position of the division for every chip, and the wafer mark for every chip. (A) is a top view of a mask, (b) is the sectional view on the AA line of Fig.3 (a). It is an enlarged plan view of a mask mark showing a relative relationship between the illumination area and the visual field area of the CCD camera. It is a front view of an alignment unit. It is a block block diagram for demonstrating the connection relation of a light source control circuit and a light emitting diode.

Explanation of symbols

W1 to W3 Wafer mark M1 to M3 Mask mark LD Light emitting diode (LED)
DESCRIPTION OF SYMBOLS 10 Semiconductor positioning device 12 Surface plate 14 Support | pillar 16 Top plate 16A Opening 18 Semiconductor wafer 20 Moving stage part 22 Work stage part 24 Base 26 1st slider 28 X-axis direction sliding device 30 2nd slider 32 Y-axis direction sliding Moving device 34 Work stage 36 Wafer chuck 38 Mask chuck 40 Mask 40A Peripheral part 40B Membrane part 40C Mask pattern part 40D Notch part 40E Global alignment mark 42 Mask θ axis base 44 Mask Z axis direction moving mechanism 46 XY table 50 for mask Alignment unit 52 Illumination light source 52a Amplifying circuit 52b Control device 54 CCD camera 54A Field of view 60 First through hole (main through hole)
62 Second through hole (sub through hole)
64 Third through hole (sub through hole)
66 Fourth through hole (sub through hole)
68 Fifth through hole (sub through hole)
70 partition (first partition)
72 Partition (second partition)
74 XY table for camera (table for image sensor)
76 Housing 78 Illumination optical system 80 Condensing lens

Claims (2)

  An illuminating means for irradiating light onto an imaging region of a mask arranged to overlap the semiconductor wafer and the semiconductor wafer, and a reflected light of the light irradiated to the semiconductor wafer and the mask from the illuminating means is incident , A positioning wafer mark formed on the semiconductor wafer, an imaging means for imaging the mask mark formed on the mask, and imaging data by imaging of the imaging means to process the wafer mark relative to the mask mark Recognizing means for recognizing a position, wherein the illuminating means selects at least one of a plurality of light sources emitting light having different wavelengths and the plurality of light sources, turns on the selected light source and emits the light quantity A semiconductor wafer imaging device comprising: a light source control circuit for adjusting the light source.   The semiconductor wafer imaging device according to claim 1, wherein the plurality of light sources are configured by a plurality of LEDs having different wavelengths.

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