JP2007266858A - Switch control circuit - Google Patents

Switch control circuit Download PDF

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JP2007266858A
JP2007266858A JP2006087547A JP2006087547A JP2007266858A JP 2007266858 A JP2007266858 A JP 2007266858A JP 2006087547 A JP2006087547 A JP 2006087547A JP 2006087547 A JP2006087547 A JP 2006087547A JP 2007266858 A JP2007266858 A JP 2007266858A
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output
switch
input
number
link
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Hitoshi Obara
仁 小原
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Akita Univ
国立大学法人秋田大学
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Abstract

PROBLEM TO BE SOLVED: To realize matching processing between input / output control elements with a simple configuration.
A connection request number calculating means for calculating a connection request number for each output switch from an output terminal number requested for connection, and a first indicating a use state of an output link corresponding to the number of intermediate switches for each input switch. A first register holding second usage status data, a second register holding second usage status data indicating the usage status of the input link corresponding to the number of intermediate switches for each output switch, and one input Between the switch and one output switch, the first use state data and the second use state data are read in parallel from each register and collated, and the output link is within the range of the number of connection requests corresponding to the output switch. And a processing module that calculates a free link common to the input links and uses the free link as a path inside the multistage switch.
[Selection] Figure 2

Description

  The present invention is a switch control circuit used for a multistage switch that is completely non-blocking, and in particular, when a pair of input terminal number and output terminal number of a switch to be connected is given, the path inside the multistage switch is changed. The present invention relates to a switch control circuit to be calculated.

  In this specification, a typical Clos switch will be described as an example of a complete non-blocking multistage switch, but the switch control circuit of the present invention is not limited to the Clos switch. In addition, the Clos switch basically has a three-stage configuration, but a multi-stage switch of five or more stages can be configured by further disassembling the second stage of the three-stage configuration into a three-stage configuration. The explanation is centered.

  The control method of the Clos switch is roughly divided into two in principle. The first control method is “sequential control” in which when a plurality of pairs of input terminal numbers and output terminal numbers of switches are given as connection requests, the pairs are sequentially processed one by one. The Clos switch has a completely non-blocking property, and there is always a path inside the multistage switch that connects the unused input terminal and output terminal, so the connection requests may be processed in order.

The second control method is “parallel control” in which when a plurality of connection requests are given, they are collectively processed at the same time. As a specific control method, a control method in which a parallel control method proposed for a Benes network of multistage switches is applied to a Clos network is known (Non-Patent Document 1).
TTLee and SYLiew, "Parallel routing algorithms in Benes-Clos networks", IEEE Transaction on Communication, vol.50, no.11, pp.1841-1847, 2002

  When a plurality of connection requests are given, the “sequential control” by the first control method is simple. However, if the parallel requests are simply parallelized, the following problem (double booking) may occur.

  Here, a three-stage (3-7-3) Clos switch circuit shown in FIG. 1 will be described as an example. In FIG. 1, the first-stage switch circuits (input switches) 11, 12, and 13 have four input terminals 101 to 104, 105 to 108, and 109 to 112, respectively. The input switches 11, 12, 13 and the second-stage switch circuits (intermediate switches) 21-27 are connected in a mesh form via seven output links 121-123, respectively. For example, the input switch 11 is connected to the intermediate switches 21 to 27 via seven output links 121. The intermediate switches 21 to 27 and the third stage switch circuits (output switches) 31, 32, and 33 are connected via seven input links 124 to 126, respectively. For example, the output switch 31 is connected to the intermediate switches 21 to 27 via the seven input links 124. The output switches 31, 32, and 33 have four output terminals 131 to 134, 135 to 138, and 139 to 142, respectively.

  Here, a basic processing procedure when the input terminal 102 and the output terminal 131 are connected will be described. First, the input switch 11 having the input terminal 102 searches the output link 121 for an unused state. At the same time, the output switch 31 having the output terminal 131 searches for an unused input link 124. The seven positions of the output link 121 and the input link 124 correspond to the positions of the intermediate switches 21 to 27, respectively. Therefore, if the output link 121 and the input link 124 are at the same position (the link number counted from the top is i) and both are not in use, the i-th intermediate switch passes through the i-th intermediate switch. A route (route inside the multistage switch) can be set.

  Such a control operation is realized by a switch control circuit as shown in FIG. 2 corresponding to the switch circuit of FIG. 2, input control elements 11e, 12e, and 13e are installed corresponding to the input switches 11, 12, and 13 in FIG. The output control elements 31e, 32e, 33e are installed corresponding to the output switches 31, 32, 33 in FIG. The input control elements 11e to 13e have four input terminals 101e to 104e, 105e to 108e, and 109e to 112e corresponding to the input terminals 101 to 104, 105 to 108, and 109 to 112 in FIG. The output terminal number to be input is input. Similarly, the output control elements 31e to 33e have four output terminals 131e to 142e corresponding to the output terminals 131 to 142 in FIG. The input control elements 11e to 13e and the output control elements 31e to 33e are connected via mesh control links 151 to 159.

  Here, it is assumed that the input control elements 11e and 12e have usage state data (0010111) and (01011111) indicating usage states of the output links 121 and 122 of the input switches 11 and 12, and the output control element 31e includes It is assumed that there is usage status data (0100000) indicating the usage status of the input link 124 of the output switch 31. “0” indicates an unused state, and “1” indicates a used state. For example, the usage status data (0010111) of the input control element 11e indicates that the first, second and fourth from the top of the output link 121 are unused, and the third, fifth and subsequent are used. In this case, in order to route a new connection request, the first, second, and fourth intermediate switches 21, 22, and 24 are passed.

When the input terminal 102 and the output terminal 131 in FIG. 1 are connected, between the input control element 11e and the output control element 31e corresponding to the output switch 31 and the output switch 31 in which the respective input / output terminals are accommodated, the following Thus, the operation based on the usage state data is performed. First, the input control element 11 e requests the connection destination output control element 31 e to refer to the usage state data (0100000) via the control link 151. Next, the input control element 11e uses its own usage state data (0010111).
And the usage status data of the referenced output control element 31e (0100000)
And whether or not there is a common position where both are “0” is checked. Hereinafter, this process is referred to as a matching process. Here, since the first and fourth from the top of the use state data correspond, for example, the route via the first intermediate switch 21 corresponding to the position can be used. As routes for connecting the input terminal 102 and the output terminal 131 selected in this way, each path in the input switch 11, the intermediate switch 21, and the output switch 31 in FIG. When a plurality of routes are candidates by the matching process, one route is arbitrarily selected as described above.

  Next, a case where two sets of input terminals and output terminals are requested to be processed in parallel at the same time will be described. FIG. 1 shows an example in which two sets of an input terminal 102 and an output terminal 131, and further an input terminal 107 and an output terminal 133 are connected simultaneously. As described above, it can be easily understood that the connection can be made without problems if the processing is performed one by one in order. Assume that these two sets of connection requests are simply operated in parallel.

Similarly to the above processing procedure, in order to connect the input terminal 102 and the output terminal 131, matching processing of use state data is performed by the input control element 11e and the output control element 31e. Similarly, in order to connect the input terminal 107 and the output terminal 133, matching processing of use state data is performed by the input control element 12e and the output control element 31e. In this example, the usage state data (0100000) of the output control element 31e is referred to by the two input control elements 11e and 12e in parallel. Here, the usage state data of the input control elements 11e and 12e are (0010111) and (01011111), respectively.
11e: (0010111)
12e: (01011111)
31e: (0100000)
Thus, the first and fourth are both “0” when viewed from the input control element 11e, and the first and third are both “0” when viewed from the input control element 12e. At this time, if the input control element 11e selects the first, the input control element 12e selects the third, or the input control element 11e selects the fourth, the input control element 12e selects the first or third, A route corresponding to the connection request can be determined.

  However, in simple parallel control, the first may be selected by both the input control elements 11e and 12e, and in this case, double booking is performed. As a result, blocking occurs in the control link between the intermediate switch 21 and the output switch 31, and normal control operation cannot be realized. The above is the problem of double booking that occurs when the first control method is simply parallelized.

  On the other hand, the parallel control circuit of the multi-stage switch based on the second control method can perform high-speed processing by parallel processing compared to sequential control, and can avoid the double booking as described above. The control is complicated, and conventionally, there is a problem that the processing time becomes long depending on the switch scale (number of input switches and output switches) for software processing.

  Further, in the conventional switch control circuit, it is necessary to arrange one input control element and one output control element corresponding to one input switch and one output switch as shown in FIG. There is a problem that the number of wires increases according to the switch scale (number of input switches and output switches).

  An object of the present invention is to provide a switch control circuit capable of realizing matching processing between input / output control elements with a simple configuration. In addition, the present invention avoids the occurrence of internal blocking due to parallel connection control of completely non-blocking multistage switches with a simple configuration, and further, wiring caused by wiring between input / output control elements in a mesh shape An object of the present invention is to provide a switch control circuit capable of avoiding an increase in amount.

  In the present invention, the required number is determined according to a plurality of input switches each having a plurality of input terminals, a plurality of output switches each having a plurality of output terminals, the number of input terminals of the input switches, and the number of output terminals of the output switches. For a multistage switch having a plurality of intermediate switches, each input switch and each intermediate switch being connected via an output link, and each output switch and each intermediate switch being connected via an input link. In the switch control circuit that calculates the path inside the multistage switch when a pair of input terminal number of the input switch and output terminal number of the output switch is given as a connection request, connection for each output switch from the requested output terminal number The connection request count calculation means for calculating the request count and the number of intermediate switches for each input switch A first register that holds first usage status data that indicates the usage status of the output link, and second usage status data that indicates the usage status of the input link corresponding to the number of intermediate switches for each output switch Between the second register, one input switch, and one output switch, the first usage state data and the second usage state data are read in parallel from each register and collated to correspond to the output switch. And a processing module that calculates a free link common to the output link and the input link within the range of the number of connection requests and uses the free link as a path inside the multistage switch.

  In addition, the switch control circuit of the present invention circulates the first usage state data corresponding to each of the plurality of input switches in a ring shape, or the second usage state data corresponding to each of the plurality of output switches in a ring shape. The processing module has a configuration common to the output link and the input link between the input switch and the output switch corresponding to the first usage state data or the second usage state data that has been circulated. It is assumed that the processing for calculating the link is performed.

  The switch control circuit according to the present invention performs, in parallel, a process of matching use state data in an input / output link with each intermediate switch between one input switch and one output switch, and the number of connection requests to the output switch. By calculating the free links within the range, it is possible to easily calculate the route inside the multistage switch for the connection request.

  In addition, the switch control circuit of the present invention circulates the input switch usage status data or the output switch usage status data, and performs a matching process between the one-to-one input / output switches, thereby allowing a plurality of output switches to have a plurality of output switches. Since access from the input switch does not occur, occurrence of internal blocking can be avoided. Further, the mesh wiring for exchanging data used for the matching process between the input / output switches is not required, and the increase in the wiring amount in the switch control circuit can be suppressed even when the switch scale is increased.

  The switch control circuit of the present invention corresponds to the switch control circuit of FIG. 2 corresponding to, for example, the three-stage (3-7-3) Clos switch circuit of FIG. 1, but first, the input control elements 11e to 13e in FIG. Description will be made in association with one (here, 11e) and one of the output control elements 31e to 31e (here, 31e). However, the configuration corresponding to the connection request number calculation means, the first and second registers, and the processing module, which are elements of the switch control circuit of the present invention, will be described separately for the input control element and the output control element for convenience. The configuration including the arrangement is not limited to the following configuration examples. The functions of the input control element and the output control element can be realized by hardware, software, or a combination thereof. Hereinafter, a configuration when each input / output control element is realized by hardware will be described.

(First configuration example of input control element)
FIG. 3 shows a first configuration example of the input control element (11e) in the switch control circuit of the present invention.

  In FIG. 3, the determination circuits 41-1 to 41-4 input the output terminal numbers of the connection destinations as connection requests from the input terminals 101e to 104e of the input control element 11e, and output switch numbers corresponding to the output terminal numbers, respectively. Determine. The output switch numbers 411 to 414 output from each determination circuit are input to the decoder circuits 42-1 to 42-4, the output link (1 bit) at the position corresponding to the output switch number is “1”, and the other output links Is “0”. The output link 421 of the decoder circuit 42-1 is connected to the adder circuits 43-1 to 43-3 installed corresponding to the output control elements (FIG. 2: 31e to 33e), and similarly, the other decoder circuit 42- The output links 422 to 424 of 2 to 43-4 are also connected to the adding circuits 43-1 to 43-3, respectively. The adder circuits 43-1 to 43-3 are configured to calculate the number of “1” s of the output links 421 to 424 of the decoder circuits 42-1 to 42-4, respectively, and each addition result is for each destination output switch. Indicates the number of connection requests. The connection request numbers 431 to 433 output from the adder circuits 43-1 to 43-3 are input to the selector circuit 44, and one of them is selected and output to the output control element 31e as the connection request number 441 for the corresponding output switch. Is done. A control signal for driving the selector circuit 44 is omitted.

  The memory circuit 45 holds 7-bit usage state data corresponding to the output link (FIG. 1: 121) of the input switch and the reservation data returned from the output control element 31e. Here, the connection request number 441 output from the selector circuit 44, the use state data 442 output from the memory circuit 45, and the reservation data 443 returned from the output control element 31e are the input control element 11e shown in FIG. And the output control element 31e via a control link 151.

  The operation of such an input control element will be described separately from the first phase to the third phase. In the first phase, the output terminal number of the connection destination is input as binary data from the input terminals 101e to 104e. The determination circuits 41-1 to 41-4 calculate the output switch number that accommodates the output terminal from the input output terminal number. For example, when the number of output terminals accommodated in one output switch is a power of 2, a process of extracting the upper bits of the output terminal number is performed. Generally, it is composed of a modulo arithmetic circuit. The decoder circuits 42-1 to 42-4 receive the output switch numbers 411 to 414 displayed in binary, and output "1" to one of the output links at the corresponding positions. For example, if the output switch number 411 input to the decoder circuit 42-1 is “10”, the second output link from the top of the output link 421 is set to “1”, and the other output links are reset to “0”. Keep it. When there is no connection request, all of the output links 421 remain reset to “0”. Therefore, since “1” corresponding to each connection request is input to the adder circuits 43-1 to 43-3 corresponding to each output switch, the total number of connection requests (binary) is obtained by adding them. Display) and is output as connection request numbers 431 to 433.

  In the second phase, the selector circuit 44 first selects the connection request number 431 and transmits it as the connection request number 441 to the corresponding output control element 31e. At the same time, the connection state data 442 of the input control element 11e is read from the memory circuit 45 and transmitted to the corresponding output control element 31e.

  In the third phase, reservation data (connection state data in which the unused state is changed to the used state) 443 is returned from the corresponding output control element 31 e and is held in the memory circuit 45. The input control element updates the connection status data of the input switch using the returned reservation data.

  When the above series of cycles is completed, the process returns to the second phase, and the selector circuit 44 switches the connection request number 431 to the connection request number 432 (or 433) corresponding to the next output switch, and the corresponding output control element 32e (or 33e). ) As the number of connection requests 441, and the operations of the second to third phases are repeated as in the previous time.

(Configuration example of output control element)
FIG. 4 shows a configuration example of the output control element (31e) in the switch control circuit of the present invention.

  In FIG. 4, the connection request number 441 for the output control element 31e (output switch 31) output from the selector circuit (FIG. 3:44) of the input control element (FIG. 3: 11e) is input to the register 51 and held. The Here, the connection request number 441 is 2 (binary number “10”). Also, the connection state data 442-1 to 442-7 output from the memory circuit (FIG. 3:45) of the input control element (FIG. 3: 11e) are input to the registers 52-1 to 52-7, respectively, and held. Is done. Here, the connection state data 442-1 to 442-7 correspond to the output links 121 of the input switch 11 shown in FIG. 1, and “0” is an unused state and “1” is a used state. Indicates.

  The registers 53-1 to 53-7 hold connection state data of the input link 124 of the output switch 31 shown in FIG. The processing modules 54-1 to 54-7 correspond to the connection request count 501 read from the register 51 and the input switch connection status data 511 to 517 read from the corresponding registers 52-1 to 52-7, respectively. Output switch connection state data 521 to 527 read from the registers 53-1 to 53-7 are inputted. Further, the processing modules 54-2 to 54-7 input all of the flags 531 to 536 output from the processing modules located in the preceding stage, respectively. Further, the processing modules 54-1 to 54-7 perform predetermined matching processing (details will be described later) based on the above inputs, and rewrite signals 541 to 547 for the connection state data of the input switch and the output switch, respectively. Are output to the corresponding registers 52-1 to 52-7 and registers 53-1 to 53-7, respectively. Each register updates connection state data according to the rewrite signals 541 to 547. Also, the registers 52-1 to 52-7 that hold the connection state data of the input switches are the memory circuits of the input control elements corresponding to the updated connection state data of the input switches as reserved data 443-1 to 443-7 ( Reply to FIG. 3:45).

  FIG. 5 shows a configuration example of the processing module 54. Here, the processing module 54-3 will be described as an example, but the processing modules have the same configuration except that the number of inputs of the flags 531 to 536 of the processing module located in the preceding stage is different.

  In FIG. 5, connection state data 513 of the input switch output from the register 52-3 and connection state data 523 of the output switch output from the register 53-3 are input to the NOR circuit 61, and the NOR output is flagged. This is output to the next processing modules 54-4 to 54-7 as 533 and also input to the adder circuit 62 and the AND circuit 63. This flag 533 is “1 (available)” only when the connection status data 513 of the input switch and the connection status data 523 of the output switch are both “0 (unused)”. The addition circuit 62 receives the flags 531 and 532 output from the processing modules 54-1 and 54-2 in the preceding stage, and performs addition processing of the flags 531 and 532 and 533. This addition result indicates the total number of switch paths that have been usable so far. The size comparison circuit 64 compares the connection request number 501 for the output switch with the addition result of the adder circuit 62, and gives “1” to the AND circuit 63 when the addition result is less than the connection request number 501. The AND circuit 63 calculates the logical product of the comparison result of the magnitude comparison circuit 64 and the flag 533, and if the total number of usable switch paths is equal to or less than the number of connection requests, the AND circuit 63 activates the flag 533 of "1" If the total number of paths exceeds the number of connection requests, the “1” flag 533 is disabled. The control signal 543 in which the “1” flag 533 is activated is input to the register 52-3 and the register 53-3, and the connection state data is rewritten.

  The operation of such an output control element will be described in association with the first to third phases of the input control element. In the first phase, the connection request number 441 and the connection status data 442-1 to 442-7 of the input switch are input from the input control element, and the registers 51 and 52-1 to 52-7 hold respectively. The connection request number 501 and the input switch connection state data 511 to 517 read from each register are input to the processing modules 54-1 to 54-7.

  In the second phase, the processing modules 54-1 to 54-7 match the input switch connection state data 511 to 517 with the output switch connection state data 521 to 527 read from the registers 53-1 to 53-7. Perform processing in parallel. If both facing connection state data are both “0”, it can be used as a switch path, and “1 (usable)” is output as the flags 531 to 537. Here, the number of switch paths that can be used (the number of flags that become “1”) is calculated, and the connection status data of the corresponding input switch and output switch with the flag “1” equal to or less than the number of connection requests set as active. Is rewritten from “0” to “1”. In other words, if the number of switch paths already available in the upper processing module exceeds the number of connection requests, the flag “1” is disabled in the AND circuit 63 and rewritten from “0” to “1”. The connection state data that is obtained does not exceed the number of connection requests.

  In the third phase, the rewritten input switch connection state data is transferred from the registers 52-1 to 52-7 to the memory circuit (FIG. 3:45) of the corresponding input control element as reserved data 443-1 to 443-7. I will reply.

(Second configuration example of input control element)
The configurations of the input control element and the output control element described above are merely examples, and different circuit configurations that perform the same function may be used. Here, a second configuration example of the input control element (11e) will be described with reference to FIG.

  The feature of this configuration example is that four sets of comparison circuits 46-1 to 46-3 are used instead of the decoder circuits 42-1 to 42-4 of the input control element 11e shown in FIG. ~ 41-4 are connected in parallel. For example, the output switch numbers 411 to 414 output from the determination circuits 41-1 to 41-4 are input to the four comparison circuits 46-1, and output switches corresponding to the output switches (FIG. 1:31). If the number matches or does not match, “1” is output when the numbers match. Therefore, by adding the coincidence detection output of the comparison circuit 46-1 in the adder circuit 43-1, the connection request number 431 for the output switch (FIG. 1:31) is obtained. The same applies to the comparison circuits 46-2 and 46-3.

  The input control element 11e and the output control element 31e configured as described above are connected via the control link 151 shown in FIG. 2, and the connection state data of the input switch 11 within the range of the number of connection requests from the input switch 11 to the output switch 31. By performing the matching process of the connection state data of the output switch 31, it is possible to calculate a switch path that can be easily connected (path within the multistage switch). Further, by performing the above matching processing in order via the control links 151 to 159 between the input control elements 11e to 13e and the output control elements 31e to 33e shown in FIG. Can be calculated.

(Modification of the switch control circuit of the present invention)
Next, a modification of the switch control circuit of the present invention that facilitates matching processing performed in order between the input control elements 11e to 13e and the output control elements 31e to 33e shown in FIG. 2 will be described with reference to FIG. explain.

  In FIG. 7, the input control elements 11e to 13e and the output control elements 31e to 33e are installed corresponding to the input switch and the output switch in the same manner as the switch control circuit shown in FIG. It has a function to hold the current usage status data of the input link. Output terminal numbers, which are connection request destinations, are input to the input terminals 101 to 112e of the input control elements 31e to 33e, respectively. The input control elements 11e to 13e and the output control elements 31e to 33e are connected on a one-to-one basis via control links 151, 155, and 159, respectively. The control link code corresponds to the control link code shown in FIG. The output control elements 31e to 33e are connected in a ring shape via control links 161 to 163 for shifting use state data held therein to adjacent output control elements.

  Next, the processing procedure of the switch control circuit of this embodiment will be described separately from the first phase to the third phase. The processing in each phase is the same as that in the pair of input control elements and output control elements described with reference to FIGS.

  In the first phase, connection requests (output terminal numbers) are input from the input terminals 101e to 112e, and the input control elements 11e to 13e are connected to which output switch (output control element) how many based on those connection requests. Calculate if there is a connection request.

  In the second phase, the input control elements 11e to 13e send the connection request number and the input switch usage state data to the output control elements 31e to 33e connected via the control links 151, 155, and 159, respectively. Send. The output control elements 31e to 33e that have received these control data perform matching processing between the input switch usage status data and the output switch usage status data originally held in the output control element. As a result, link positions that can be connected between the input / output switches corresponding to the input control elements 11e to 13e and the output control elements 31e to 33e are obtained. From the links extracted in this way, links corresponding to the number of connection requests are selected, and reservation processing such as updating the usage status data of the output switch is performed.

  In the third phase, the output control elements 31e to 33e transmit matching processing results (reservation data) to the input control elements 11e to 13e, respectively. The input control elements 11e to 13e update the usage state data of the input switch based on the received reservation data.

  When the above series of processing ends, the output control elements 31e to 33e then shift the use state data held therein to the adjacent output control elements via the links 161 to 163. That is, the combination of the input control elements 11e to 13e and the output control elements 31e to 33e is changed from the previous one to the next one. For example, the output control element 33e is connected to the input control element 11e in FIG. 2 via the control link 153, and the number of connection requests to the output control element 33e as the number of connection requests 441 in FIGS. 433 is transmitted. Thereafter, the operations from the first phase to the third phase are repeated. From the viewpoint of the input control elements 11e to 13e, the processing contents are exactly the same as the connection destination output control elements 31e to 33e are shifted by one.

  By repeating the above control operation for the number of times corresponding to the number of input / output switches (input / output control elements), combinations between all input / output control elements are realized, and the control operation is terminated.

  In the above description, the input control elements 11e to 13e and the output control elements 31e to 33e are configured to be independent. However, they can be configured integrally. In that case, the control links 151, 155, and 159 shown in FIG. 7 are not necessary. Further, an equivalent function can be realized by ring-connecting the input control element side instead of ring-connecting the output control element side. Since this can be easily inferred, its details are omitted.

  The switch control circuit of the present invention can be applied to a system to which a completely non-blocking multistage switch is applied, such as a telephone switching system, a digital cross-connect system, an optical cross-connect system, and a parallel network of parallel computers.

The figure which shows the structure of a three-stage (3-7-3) Clos switch circuit. The figure which shows the structure of the switch control circuit corresponding to a three-stage (3-7-3) Clos switch circuit. The figure which shows the 1st structural example of the input control element (11e) in the switch control circuit of this invention. The figure which shows the structural example of the output control element (31e) in the switch control circuit of this invention. The figure which shows the structural example of the processing module. The figure which shows the 2nd structural example of the input control element (11e) in the switch control circuit of this invention. The figure which shows the structural example of the switch control circuit of this invention.

Explanation of symbols

11, 12, 13 Input switch 21, 22, 23 Intermediate switch 31, 32, 33 Output switch 11e, 12e, 13e Input control element 31e, 32e, 33e Output control element 41 Judgment circuit 42 Decoder circuit 43 Adder circuit 44 Selector 45 Memory Circuit 46 Comparison circuit 51, 52, 53 Register 54 Processing module 61 NOR circuit 62 Addition circuit 63 AND circuit 64 Comparison circuit 101-112 Input terminal 121-123 Output link 124-126 Input link 131-142 Output terminal 151-159 Control link

Claims (2)

  1. A plurality of input switches each having a plurality of input terminals, a plurality of output switches each having a plurality of output terminals, and a plurality of intermediate switches whose required number is determined according to the number of input terminals of the input switch and the number of output terminals of the output switch Input switch input to a fully non-blocking multi-stage switch in which each input switch and each intermediate switch are connected via an output link, and each output switch and each intermediate switch are connected via an input link. In a switch control circuit that calculates a path inside a multistage switch when a pair of a terminal number and an output terminal number of an output switch is given as a connection request,
    Connection request number calculating means for calculating the connection request number for each output switch from the output terminal number requested for connection;
    For each input switch, a first register holding first usage state data indicating a usage state of the output link corresponding to the number of the intermediate switches;
    A second register holding second usage state data indicating a usage state of the input link corresponding to the number of the intermediate switches for each of the output switches;
    Between one input switch and one output switch, the first use state data and the second use state data are read in parallel from each register and collated, and the number of connection requests corresponding to the output switch A switch control circuit comprising: a processing module that calculates a free link that is common to the output link and the input link in a range and uses the free link as a path inside the multistage switch.
  2. The switch control circuit according to claim 1,
    The first usage status data corresponding to each of the plurality of input switches is circulated in a ring shape, or the second usage status data respectively corresponding to the plurality of output switches is circulated in a ring shape. And
    The processing module calculates a free link common to the output link and the input link between the input switch and the output switch corresponding to the first usage state data or the second usage state data that has been circulated. A switch control circuit, characterized in that it is configured to perform processing.
JP2006087547A 2006-03-28 2006-03-28 Switch control circuit Withdrawn JP2007266858A (en)

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Cited By (1)

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JP2014096795A (en) * 2012-11-01 2014-05-22 Boeing Co Satellite communications data processing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014096795A (en) * 2012-11-01 2014-05-22 Boeing Co Satellite communications data processing
US9954602B2 (en) 2012-11-01 2018-04-24 The Boeing Company Satellite communications data processing

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