JP2007266290A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2007266290A
JP2007266290A JP2006089088A JP2006089088A JP2007266290A JP 2007266290 A JP2007266290 A JP 2007266290A JP 2006089088 A JP2006089088 A JP 2006089088A JP 2006089088 A JP2006089088 A JP 2006089088A JP 2007266290 A JP2007266290 A JP 2007266290A
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gate electrode
semiconductor device
silicide
gate
insulating film
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JP4957040B2 (en
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Kimihiko Hosaka
公彦 保坂
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Fujitsu Ltd
富士通株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To form a nickel full silicide gate having much Si composition. <P>SOLUTION: First and second processes are used. In the first process, the upper portion of a first gate electrode is subjected to cobalt silicification. In the second process, the first and second gate electrodes are subjected to nickel full silicification. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  For miniaturization and higher performance of semiconductor devices, it is essential to reduce the thickness of the gate insulating film. However, the thickness of the silicon oxynitride film, which is a conventionally used gate insulating film, has been reduced to 1 nm in recent years, and the physical limit is approaching. Therefore, it has been proposed to use a metal gate that can improve gate depletion without changing the physical film thickness and can be expected to improve the performance of the gate electrode. One of the metal gates, nickel fully silicided gate (hereinafter referred to as Ni-FUSI gate) is promising as a technology for next-generation semiconductor devices because of its good compatibility with conventional silicon processes. Has been.

  In recent silicon processes, silicidation is generally applied for the purpose of reducing the sheet resistance, gate electrode resistance, and contact resistance of the source / drain regions. This silicidation is realized by performing heat treatment after depositing a metal for forming a silicide layer on the entire surface of a substrate or the like. The FUSI gate that has been attracting attention in recent years is that all of the gate electrode up to the interface with the gate insulating film is silicided, and a technique for forming a gate electrode using a metal itself, metal nitride, or the like (for example, Compared with the conventional silicon process, the compatibility with the conventional silicon process is good from the viewpoint of the contamination of the manufacturing apparatus used for manufacturing the semiconductor device.

  By the way, the problem of the silicide gate including the FUSI gate is the threshold voltage control of the MOS transistor. By simply siliciding the gate electrode, the threshold voltage of the transistor is significantly different from the threshold voltage of polysilicon currently used as the gate electrode material, and cannot be used as an actual LSI.

Currently proposed methods for controlling the threshold voltage of a MOS transistor having a FUSI gate are introduction of impurities into gate polysilicon (see, for example, Non-Patent Document 1), composition change of gate nickel silicide, It is two points. From the viewpoint of changing the composition of the gate nickel silicide, for example, in order to form a silicide layer having a large Si composition ratio such as NiSi 2 , a heat treatment at a high temperature of about 650 ° C. is required (for example, Non-Patent Document 2). See).

Also, a step of depositing a cobalt interface layer between the silicon layer and the nickel layer prior to nickel silicidation includes epitaxial nickel silicide on (100) plane Si or stable nickel silicide on amorphous Si And a manufacturing method are known (for example, see Patent Document 2).
Japanese Patent Application Laid-Open No. 2004-207481. JP 2002-343742 A. Jakub Kedzierski, et al, "Threshold Voltage Control in NiSi-Gate MOSFETs Through SIIS", IEEE Trans. on Electron Devices, Vol. 52, no. 1, pp39-46 (2005) Kensuke Takahashi, et al, "Dual Workfunction Ni-Silicide / HfSiON Gate Stacks by Phase-Controlled Full-SilidationPt. Electron Devices Meeting (IEDM), IEDM2004 Tech. Digest, pp. 91-94, Dec. 2004

  The problem to be solved by the present invention is that it is difficult to uniformly form a silicide layer having a large Si composition ratio in a nickel full silicide gate (hereinafter referred to as Ni-FUSI gate).

  The present invention includes a first step of forming a cobalt silicide on the first gate electrode, and a second step of forming a nickel full silicide on the first gate electrode and the second gate electrode. And

  According to the present invention, it is possible to form a Ni-FUSI gate having a large Si composition.

  FIG. 1 is a finding obtained by the inventor's research on threshold voltage shift of a MOS transistor having a nickel fully silicided gate (hereinafter referred to as Ni-FUSI gate). By explaining these experimental data, it will be easier to understand the present invention.

  FIG. 1 shows changes in the flat band voltage of a Ni silicide gate in which the Ni content is changed by simultaneous sputtering of Ni and Si. The horizontal axis in FIG. 1 indicates the Ni content. The Ni content of 50% means that the composition ratio of Ni and Si is Ni: Si = 1: 1. Further, the vertical axis of FIG. 1 indicates a flat band voltage. Here, 0.2 volts is the flat band voltage of p-type polysilicon, and -0.8 volts is the flat band voltage of n-type polysilicon. A circle is an experimental value, and a line shown together with the experimental value is an approximate curve for the experimental value.

  As can be seen from FIG. 1, the flat band voltage is shifted to the flat band voltage side of p-type polysilicon as the Ni content increases. It can also be seen that the flat band voltage shifts to the flat band voltage side on the n-type polysilicon side as the Ni content decreases. That is, when the threshold voltage is controlled by the silicide composition, a composition having a high Ni content is suitable for the p-type MOS. On the other hand, a composition having a large Si content is suitable for an n-type MOS.

In general, high-temperature heat treatment is required to form a silicide (eg, NiSi 2 or the like) having a large Si composition ratio.

  However, according to an experiment by the present inventor, for example, when Ni having a film thickness of 40 nm is deposited on polysilicon having a film thickness of 100 nm and high-temperature heat treatment at 700 ° C. is performed, the polysilicon is It is divided into polysilicon parts, and a uniform FUSI gate is not formed. This is because Ni agglomerates at a temperature of about 700 ° C. and becomes unstable. That is, when it is considered that the n-type MOS gate electrode is nickel fully silicided, there is a need for a method of forming a Ni-FUSI gate having a high Si composition ratio without using high-temperature heat treatment.

  From here, embodiments of the present invention will be described in detail with reference to FIGS. 2 to 7, taking as an example the formation of a semiconductor device including an n-type MOS and a p-type MOS.

  FIG. 2 shows a region where n-type MOS and p-type MOS are formed (hereinafter referred to as “nMOS formation region” and “pMOS formation region”), silicon substrate 1, gate oxide film 2a and 2b, gate electrodes 3a and 3b, silicon nitride hard masks 4a and 4b, extension regions 5a and 5b, sidewalls 6a and 6b, source / drain regions 7a and 7b, and silicided source / drain Regions 8a and 8b are shown.

  An example for forming the structure shown in FIG. 2 will be described. First, an element isolation region is formed in a predetermined region of the silicon substrate 1 using a LOCOS (Local Oxidation of Silicon) method or an STI (Shallow Trench Isolation) method, and the surface of the silicon substrate 1 is thermally oxidized. Next, polysilicon is deposited on the thermally oxidized silicon substrate 1 using a CVD (Chemical Vapor Deposition) method or the like. Next, an n-type impurity for n-type MOS and a p-type impurity for p-type MOS are implanted into this polysilicon, and a silicon nitride (SiN) film is formed thereon. Next, the three layers of the silicon nitride film, the polysilicon, and the thermal oxide film are etched using the photolithography technique while leaving the gate electrode portions of the n-type MOS and the p-type MOS. Through these steps, the gate electrodes 3a and 3b made of polysilicon and the gate electrodes 3a and 3b are formed in the nMOS formation region and the pMOS formation region on the silicon substrate 1 through the gate insulating films 2a and 2b. Upper silicon nitride hard masks 4a and 4b are formed. In addition to the thermal oxide film, a high-k insulating film or the like can be used for the gate insulating films 2a and 2b.

  Next, one of the nMOS formation region and the pMOS formation region is covered with a resist or the like. For example, when the pMOS formation region is covered with a resist, ion implantation is performed on the nMOS formation region under a predetermined condition using the stacked structure as a mask. On the other hand, the nMOS formation region is covered with a resist or the like, and ion implantation is performed on the pMOS formation region using the stacked structure as a mask under predetermined conditions. Thereafter, annealing is performed under predetermined conditions. Thereby, extension regions 5a and 5b are formed in the nMOS formation region and the pMOS formation region, respectively.

  In carrying out the present invention, either of the extension regions 5a and 5b may be formed first. Further, when the extension regions 5a and 5b are formed, ion implantation and annealing may be performed after forming a thin sidewall on the side wall of the laminated structure serving as an ion implantation mask. Further, together with the extension regions 5a and 5b, a pocket region of a predetermined conductivity type adjacent to them may be formed.

  Next, a silicon oxide film is formed on the entire surface of the element formation region using a CVD method or the like. Next, anisotropic etching is performed to form side walls 6a and 6b on the side walls of the gate insulating films 2a and 2b, the gate electrodes 3a and 3b, and the hard masks 4a and 4b.

  When forming the sidewalls 6a and 6b, a thin silicon oxide film is first formed on the entire surface of the element formation region, and then a thick silicon nitride film is formed on the silicon oxide film. Etching may be performed. At this time, the sidewalls 6a and 6b are double-structured sidewalls having silicon oxide on the inside and silicon nitride on the outside.

Next, the pMOS formation region is covered with a resist or the like, and ion implantation is performed on the nMOS formation region using the hard mask 4a and the sidewall 6a as a mask under predetermined conditions. Next, the nMOS formation region is covered with a resist or the like, and ion implantation is performed on the pMOS formation region using the hard mask 4b and the sidewall 6b as a mask under predetermined conditions. Next, annealing is performed under predetermined conditions. Thus, source / drain regions 7a and 7b are formed in the nMOS formation region and the pMOS formation region. In practicing the present invention, either the source / drain region 7a or 7b may be formed first.
Next, silicide is formed in the source / drain regions 7a and 7b in a self-aligning manner. In this formation method, a metal film such as a cobalt film resistant to a high-temperature heat treatment is deposited on the entire surface by using a CVD method or a sputtering method, and then a heat treatment at about 700 ° C. is performed to silicide the source / drain regions. . Next, the unreacted metal film is selectively removed by a chemical treatment such as sulfuric acid / hydrogen peroxide. As a result, source / drain regions 8a and 8b that are silicided in a self-aligned manner are formed in the source / drain regions 7a and 7b. At this time, since the silicon nitride hard masks 4a and 4b are present on the gate electrodes 3a and 3b, the upper portions of the gate electrodes 3a and 3b are not silicided.

  FIG. 3 shows stopper films 9a and 9b and silicon oxide films 10a and 10b in addition to the configuration of FIG.

  An example for forming the structure shown in FIG. 3 will be described. First, following the formation of the structure of FIG. 2, silicon nitride films 9a and 9b and silicon oxide films 10a and 10b are formed on the entire surface of the element formation region by using a CVD method or the like. The silicon nitride films 9a and 9b are thicker than the polysilicon film forming the gate electrodes 3a and 3b, and the silicon film forming the gate electrodes 3a and 3b and the silicon nitride forming the silicon nitride hard masks 4a and 4b. Desirably less than the total thickness with the membrane. This is because in the cueing process of the gate electrodes 3a and 3b, the polysilicon of the gate electrodes 3a and 3b is exposed when a chemical mechanical polishing method (hereinafter referred to as CMP) is performed. This is to prevent it. If the polysilicon of the gate electrodes 3a and 3b is exposed, there is a concern that the polysilicon film thickness of the gate electrodes 3a and 3b may vary greatly in the direction perpendicular to the surface of the silicon substrate 1.

  An example for forming the structure shown in FIG. 4 will be described. First, following the structure of FIG. 3, CMP for cueing the gate electrodes 3a and 3b is performed by setting the flat portions of the silicon nitride films 9a and 9b as stop positions. At this time, part of the hard masks 4a and 4b remains on the gate electrodes 3a and 3b. Next, the hard masks 4a and 4b on the polysilicon 3a and 3b of the gate electrode are removed using phosphoric acid or the like.

FIG. 5 shows a silicon oxide film 11 and a cobalt silicide (hereinafter referred to as CoSi 2 ) layer 12 in addition to the configuration of FIG.

An example for forming the structure shown in FIG. 5 will be described. First, after the structure shown in FIG. 4, a silicon oxide film 11 is deposited by CVD, and then the pMOS formation region is covered with a resist, and the nMOS formation region is exposed by photolithography. Next, after depositing a cobalt (hereinafter referred to as Co) film with a film thickness of the gate electrode 3a by using a CVD method or a sputtering method so that only the upper part of the gate electrode 3a is silicided, the temperature is 700 ° C. Heat treatment to the extent. Next, unreacted Co is selectively removed by treatment with a chemical solution such as sulfuric acid. Thus, the CoSi 2 layer 12 is formed on the gate electrode 3a in the nMOS formation region.

  The structure shown in FIG. 6 is a structure in which the silicon oxide film 11 of the cover film is removed after the structure of FIG.

  FIG. 7 shows a Ni-FUSI gate electrode 13 and a Ni-FUSI gate electrode 14 having a large Si composition ratio in addition to the configuration of FIG.

An example for forming the structure shown in FIG. 7 will be described. First, following the structure of FIG. 6, a Ni film is deposited on the entire surface of the element formation region by CVD or sputtering, and heat treatment is performed at about 400 ° C. to 500 ° C. At this time, NiSi 2 having a large Si composition ratio is formed on the gate electrode 3a shown in FIG. 6 due to the crystallinity of the CoSi 2 layer 12. That is, the Ni-FUSI gate electrode 13 having a large Si composition ratio shown in FIG. 7 is formed. On the other hand, in the pMOS formation region, a Ni-FUSI gate electrode 14 made of NiSi that is stably formed in this temperature range is formed.

  The structure having the Ni-FUSI gate 13 described with reference to FIGS. 2 to 7 is based on the principle that when Co is deposited on Si and heat-treated, Si becomes a diffusion species and diffuses into the Co region. When deposited and heat-treated, it is formed by the principle that Ni becomes a diffusion species and diffuses into the Si region.

  In the embodiment of the present invention shown in FIG. 7 and subsequent figures, an interlayer insulating film, contacts, wirings, and the like are formed according to a conventionally known method to complete a semiconductor device.

  The present invention can be applied to a semiconductor integrated circuit having a silicide gate electrode.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1) A method of manufacturing a semiconductor device in which a gate electrode is made of silicide,
A first step of converting the upper portion of the first gate electrode into a cobalt silicide;
A method of manufacturing a semiconductor device, comprising: a second step of converting the first gate electrode and the second gate electrode into nickel full silicide. (1)
(Appendix 2) A method of manufacturing a semiconductor device according to Appendix 1,
A third insulating film is formed by covering a stacked body in which a first insulating film, a polysilicon layer on which the first gate electrode or the second gate electrode is formed, and a mask layer are stacked in this order with a second insulating film. Process,
A fourth step of covering the second insulating film with a third insulating film having a predetermined etching selectivity with respect to the second insulating film;
A fifth step of removing the third insulating film, the second insulating film, and a part of the mask layer to a position where the polysilicon layer is not exposed by a planarization method;
And a sixth step of exposing the polysilicon layer by removing the mask layer. (2)
(Appendix 3) A method of manufacturing a semiconductor device according to appendix 2,
A method of manufacturing a semiconductor device, wherein the second insulating film is thicker than the polysilicon layer. (3)
(Supplementary note 4) a first nickel full silicide gate electrode whose upper part is cobalt silicide;
A semiconductor device having a second nickel full silicide gate electrode in which all gate electrodes are nickel silicide. (4)
(Supplementary note 5) The semiconductor device according to supplementary note 4, wherein
2. The semiconductor device according to claim 1, wherein the first nickel full silicide gate electrode is an n-type MOS gate electrode, and the second nickel full silicide gate electrode is a p-type MOS gate electrode. (5)
(Appendix 6) A method of manufacturing a semiconductor device according to appendix 1,
A method of manufacturing a semiconductor device, wherein the first gate electrode is an n-type MOS gate electrode, and the second gate electrode is a p-type MOS gate electrode.

(Appendix 7) A method of manufacturing a semiconductor device according to Appendix 2,
Prior to the third step, a seventh step of forming a gate side wall at a portion in contact with the side walls of the first gate electrode and the second gate electrode;
A method of manufacturing a semiconductor device comprising: an eighth step of silicidizing portions corresponding to a source region and a drain region using the mask layer and the gate sidewall as a mask.

(Appendix 8) A method of manufacturing a semiconductor device according to appendix 7,
A method of manufacturing a semiconductor device, wherein the silicidation in the eighth step is cobalt silicidation.

It is a figure which shows the change of the flat band voltage of the Ni silicide gate which changed the content rate of Ni by simultaneous sputtering of Ni and Si. It is a figure which shows the Example of this invention. It is a figure which shows the Example of this invention. It is a figure which shows the Example of this invention. It is a figure which shows the Example of this invention. It is a figure which shows the Example of this invention. It is a figure which shows the Example of this invention.

Explanation of symbols

1: silicon substrate 2a, 2b: gate oxide film 3a, 3b: polysilicon gate electrode 4a, 4b: hard mask 5a, 5b: extension region 6a, 6b: sidewall 7a, 7b: source / drain region 8a, 8b: silicide Source / drain regions 9a, 9b: stopper films 10a, 10b, 11: silicon oxide film 12: cobalt silicide layer 13: nickel full silicide gate electrode 14 having a large silicon composition ratio: silicon: nickel = 1: 1 Nickel full silicide gate electrode

Claims (5)

  1. A method of manufacturing a semiconductor device in which a gate electrode is made of silicide,
    A first step of converting the upper portion of the first gate electrode into a cobalt silicide;
    A method of manufacturing a semiconductor device, comprising: a second step of converting the first gate electrode and the second gate electrode into nickel full silicide.
  2. A method of manufacturing a semiconductor device according to claim 1,
    A third step of covering the stacked body in which the first insulating film, the polysilicon layer on which the first gate electrode or the second gate electrode is formed, and the mask layer are stacked in this order with the second insulating film; ,
    A fourth step of covering the second insulating film with a third insulating film having a predetermined etching selectivity with respect to the second insulating film;
    A fifth step of removing the third insulating film, the second insulating film, and a part of the mask layer to a position where the polysilicon layer is not exposed by a planarization method;
    And a sixth step of exposing the polysilicon layer by removing the mask layer.
  3. A method of manufacturing a semiconductor device according to claim 2,
    A method of manufacturing a semiconductor device, wherein the second insulating film is thicker than the polysilicon layer.
  4. A first nickel full silicide gate electrode, the upper part being cobalt silicide;
    A semiconductor device having a second nickel full silicide gate electrode in which all gate electrodes are nickel silicide.
  5. The semiconductor device according to claim 4,
    2. The semiconductor device according to claim 1, wherein the first nickel full silicide gate electrode is an n-type MOS gate electrode, and the second nickel full silicide gate electrode is a p-type MOS gate electrode.
JP2006089088A 2006-03-28 2006-03-28 Semiconductor device and manufacturing method of semiconductor device. Expired - Fee Related JP4957040B2 (en)

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Citations (7)

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US20040094804A1 (en) * 2002-11-20 2004-05-20 International Business Machines Corporation Method and process to make multiple-threshold metal gates CMOS technology
JP2005228868A (en) * 2004-02-12 2005-08-25 Sony Corp Semiconductor device and its manufacturing method
WO2006001271A1 (en) * 2004-06-23 2006-01-05 Nec Corporation Semiconductor device and manufacturing method thereof
JP2006013270A (en) * 2004-06-29 2006-01-12 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2006165435A (en) * 2004-12-10 2006-06-22 Toshiba Corp Semiconductor device and manufacturing method therefor
JP2007157744A (en) * 2005-11-30 2007-06-21 Toshiba Corp Semiconductor device, and process for fabricating same
JP2007251030A (en) * 2006-03-17 2007-09-27 Renesas Technology Corp Semiconductor device and method of manufacturing the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040094804A1 (en) * 2002-11-20 2004-05-20 International Business Machines Corporation Method and process to make multiple-threshold metal gates CMOS technology
JP2005228868A (en) * 2004-02-12 2005-08-25 Sony Corp Semiconductor device and its manufacturing method
WO2006001271A1 (en) * 2004-06-23 2006-01-05 Nec Corporation Semiconductor device and manufacturing method thereof
JP2006013270A (en) * 2004-06-29 2006-01-12 Renesas Technology Corp Semiconductor device and its manufacturing method
JP2006165435A (en) * 2004-12-10 2006-06-22 Toshiba Corp Semiconductor device and manufacturing method therefor
JP2007157744A (en) * 2005-11-30 2007-06-21 Toshiba Corp Semiconductor device, and process for fabricating same
JP2007251030A (en) * 2006-03-17 2007-09-27 Renesas Technology Corp Semiconductor device and method of manufacturing the same

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