JP2007258533A - Semiconductor memory device and its driving system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which is a fast nonvolatile work memory and can be initialized fast to a desirable state, and to provide its driving method. <P>SOLUTION: The semiconductor memory device has a resistance storage element R<SB>R</SB>which has a resistance storage layer between a pair of electrodes, is composed of a resistance storage material for storing a high resistive state and a low resistive state, and switches the high resistive state and the low resistive state by application of a voltage or current; and a laminate which is formed between the pair of electrodes and laminates a fixed magnetization layer, a nonmagnetic layer, and a free magnetization layer. Further, the semiconductor memory device has a magnetoresistance effect element R<SB>M</SB>in which a resistance value changes in accordance with a relationship between a magnetization direction of the fixed magnetization layer and the magnetization direction of the free magnetization layer, and one electrode of the resistance storage element R<SB>R</SB>is connected to one electrode of the magnetoresistance effect element R<SB>M</SB>. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a driving method thereof, and more particularly to a semiconductor memory device including a nonvolatile memory element and a driving method thereof.

  In recent years, a magnetic random access memory (hereinafter referred to as MRAM: Magnetic Random Access Memory) in which magnetoresistive effect elements are arranged in a matrix is drawing attention as a rewritable nonvolatile memory. The MRAM stores information using a combination of magnetization directions in two magnetic layers, and changes in resistance (that is, changes in current or voltage) when the magnetization directions between these magnetic layers are parallel and antiparallel. The stored information is read by detecting this.

  As magnetoresistive elements that constitute the MRAM, GMR (Giant Magnetoresistive) elements and TMR (Tunneling Magnetoresistive) elements have been studied. In particular, a TMR element that can obtain a large resistance change has attracted attention as a magnetoresistive effect element used in MRAM.

  A TMR element has two ferromagnetic layers stacked via a tunnel insulating film, and the tunnel current flowing between the magnetic layers changes via the tunnel insulating film based on the relationship between the magnetization directions of the two ferromagnetic layers. This is a phenomenon that uses the phenomenon. That is, the TMR element has a low element resistance when the magnetization directions of the two ferromagnetic layers are parallel, and has a high element resistance when the two ferromagnetic layers are antiparallel. By associating these two states with data “0” and data “1”, it can be used as a memory element.

In recent years, a nonvolatile semiconductor memory device called RRAM (Resistance Random Access Memory) has attracted attention as a new memory element. The RRAM uses a resistance memory element that has a plurality of resistance states having different resistance values and changes its resistance state by applying an electrical stimulus from the outside. By associating with "0" and "1", the memory element is used. The future of RRAM is expected because of its high potential such as high speed, large capacity, and low power consumption.
Japanese Patent Laid-Open No. 11-317071 JP 2002-359212 A JP 2004-158766 A

  The MRAM and RRAM are nonvolatile semiconductor memory devices, and can retain stored information even after the power is turned off. On the other hand, when MRAM or RRAM is used as a work memory, in order to initialize the contents after rewriting the contents, the information is read from a read-only memory (ROM) or a storage memory such as a hard disk device and written again. There is a need. However, such an initialization method must be performed for each cell or for each specific block, and initialization at high speed is difficult.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of high-speed initialization into a desired state and a driving method thereof, as well as a work memory having high speed and non-volatility.

  According to one aspect of the present invention, a pair of electrodes and a resistance memory layer made of a resistance memory material formed between the pair of electrodes, the high resistance state and the low resistance state are stored, the voltage or A resistive memory element that switches between the high resistance state and the low resistance state by applying a current, a pair of electrodes, and a pair of electrodes, and a fixed magnetic layer, a nonmagnetic layer, and a free magnetic layer are stacked. A magnetoresistive effect element whose resistance value changes according to the relationship between the magnetization direction of the fixed magnetization layer and the magnetization direction of the free magnetization layer, and the pair of the resistance memory elements. One of the electrodes is connected to one of the pair of electrodes of the magnetoresistive effect element. A semiconductor memory device is provided.

  Further, according to another aspect of the present invention, a pair of electrodes and a resistance memory layer made of a resistance memory material formed between the pair of electrodes are stored, and a high resistance state and a low resistance state are memorized. A resistance memory element that switches between the high resistance state and the low resistance state by application of voltage or current, a pair of electrodes, and a pair of electrodes, and a fixed magnetic layer, a nonmagnetic layer, and a free magnetic layer, A magnetoresistive effect element whose resistance value changes in accordance with the relationship between the magnetization direction of the fixed magnetization layer and the magnetization direction of the free magnetization layer. A method of driving a semiconductor memory device in which one of the pair of electrodes and one of the pair of electrodes of the magnetoresistive effect element are connected, wherein information recorded in the magnetoresistive effect element is initially stored The one of the resistance memory elements A voltage is applied between the other of the electrodes of the magnetoresistive effect element and the other of the pair of electrodes of the magnetoresistive effect element, and a current corresponding to the resistance state of the resistance memory element is caused to flow through the magnetoresistive effect element Thus, there is provided a method for driving a semiconductor memory device, wherein information recorded in the resistance memory element is transferred to the magnetoresistive element.

  According to the present invention, a magnetoresistive effect element and a resistance memory element are connected in series to constitute one memory cell, the magnetoresistive effect element is used as a work memory, and the resistance memory element is used as a storage memory. A non-volatile work memory can be configured. In addition, since the transfer of information from the resistance memory element to the magnetoresistive effect element can be performed only by applying a predetermined drive voltage to the serial connection body of the resistance memory element and the magnetoresistive effect element, the magnetoresistive effect element is desired. It is possible to initialize to the state at high speed.

  A semiconductor memory device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS.

  1 is a circuit diagram showing the basic structure of the semiconductor memory device according to the present embodiment, FIG. 2 is a schematic sectional view showing the basic structure of the semiconductor memory device according to the present embodiment, and FIG. 3 shows the structure of the semiconductor memory device according to the present embodiment. FIG. 4 is a plan view showing the structure of the semiconductor memory device according to the present embodiment, FIG. 5 is a schematic cross-sectional view showing the structure of the semiconductor memory device according to the present embodiment, and FIG. 6 shows the semiconductor memory device according to the present embodiment. FIG. 7 to FIG. 12 are process cross-sectional views illustrating the method of manufacturing the semiconductor memory device according to the present embodiment.

  First, the basic structure of the semiconductor memory device according to the present embodiment will be explained with reference to FIGS.

The semiconductor memory device according to the present embodiment, as shown in FIG. 1, the resistance memory element unit cell by the series connection of the R _R and the magnetoresistive element R _M is one configured. Configuration resistance memory element R _R is a variable resistive element used as a unit storage element RRAM, and an insulating resistance memory material whose resistance value changes by application of current or voltage by a pair of electrodes which sandwich this Is done. The magnetoresistive element R _M is a variable resistive element used as a unit storage element MRAM, for example, a fixed magnetization layer in which a magnetization direction is fixed, a free magnetic layer which changes its magnetization direction, between the A spin injection type TMR element constituted by a barrier layer sandwiched between two layers.

The resistance memory element R _R and the magnetoresistive element R _M, and one terminal are connected to each other, and to be able to apply a driving voltage to the connection terminal V2. The magnetoresistive element R _M and the other terminal V1 and the resistance memory element R other terminal V0 _R's are adapted to each be applying a predetermined driving voltage.

  The circuit configuration shown in FIG. 1 can be realized by the element structure shown in FIG.

  A resistance memory layer 12 made of a resistance memory material is formed on the electrode 10. An electrode 14 is formed on the resistance memory layer 12. An antiferromagnetic layer 18 is formed on the electrode 14. A fixed magnetization layer 20 is formed on the antiferromagnetic layer 18. A barrier layer 22 is formed on the fixed magnetization layer 20. A free magnetic layer 24 is formed on the barrier layer 22. An electrode 26 is formed on the free magnetic layer 24. Thus, the magnetoresistive effect including the resistance memory element 16 including the electrode 10, the resistance memory layer 12, and the electrode 14, and the electrode 14, the antiferromagnetic layer 18, the fixed magnetization layer 20, the barrier layer 22, the free magnetization layer 24, and the electrode 26. A unit element structure in which the resistance memory element 16 and the magnetoresistive effect element 28 are connected in series by the electrode 14 is formed.

The device parameter of the resistance memory element R _R and the magnetoresistive element R _M, upon application of a voltage lower than either of the set voltage and the reset voltage of the resistance memory element R _R between the terminals V0 and the terminal V1, the resistance memory element R _R is only to be able to flow a write current of the magnetic reversal current density above the current density of the magnetoresistive element R _M in the case of low-resistance state, appropriately set.

For example, the resistance memory element R _R, the resistance value when the high resistance state 400 kilohms, the resistance value when the low-resistance state 40 k.OMEGA, as set voltage and the reset voltage becomes larger than 4V, to design the device. Also, the magnetoresistive element R _M is the element area of 0.1 × 0.1 [mu] m ^2, the resistance value when the high resistance state 40 k.OMEGA, when the resistance value when the low resistance state has a high resistance 1 / 3 (13.3 kΩ), the magnetization reversal current density is 5 × 10 ⁵ A / cm ² (magnetization reversal current Ic = 0.05 mA), the read current (Ic / 5) is 0.01 mA, and the breakdown voltage due to the pulse current is 2V. The device is designed so that These parameters are within the general ranges of the resistance memory element and the magnetoresistive effect element, and it is not necessary to adopt a special material or structure when configuring the semiconductor memory device of the present invention.

  Next, the method for driving the semiconductor memory device according to the present embodiment will be explained with reference to FIG.

In the semiconductor memory device according to the present embodiment, the magnetoresistive element _RM is a memory element used as a work memory. Resistance memory element R _R is a storage element used as a storage memory for storing predetermined information for initializing the working memory. Information stored in the resistive memory element R _R is optionally written to the magneto-resistive element R _M, is used to initialize the magneto-resistive element R _M.

First, the resistance memory element R _R, writing initial information. Writing to the resistance memory element R _R is performed by applying a predetermined write voltage between the terminals V0 and the terminal V2. The writing to the resistance memory element R _R, is a reset for writing a high resistance state, a set of writing the low resistance state. Usually, the set voltage required for writing in the low resistance state is higher than the reset voltage required for writing in the high resistance state. Here, both of the set and reset voltages of the resistance memory element R _R is assumed to be higher than 4V voltage. The resistance value of the high resistance state of the resistance memory element R _R is 400 kilohms, the resistance value in the low resistance state is assumed to be 40 k.OMEGA.

Incidentally, the writing of initial information to the resistance memory element R _R may be carried out according to need, it is not necessarily performed each time.

Then, reset the recorded information of the magnetoresistive element R _M. Reset of the recording information of the magnetoresistive element R _M is performed by passing a predetermined write current to the magnetoresistive element R _M. Here, the current density (magnetization reversal current density) of the write current necessary for magnetization switching of the magnetoresistive element R _M Jc is assumed at 5 × 10 5 ^{A /} cm ² or more. Further, the element area of the magnetoresistive element _{R M} is a 0.1 × 0.1 [mu] m ^2, the element resistance in the initial state is assumed to be 13.3Keiomega (low resistance state).

Is applied to the terminal V1 to 0V for example, is applied to the terminal V2, for example, 0.7V voltage, from the terminal V2 to the terminal V1 direction to the magnetoresistive element _{R M,} the current density of about 5.3 × ¹⁰ 5 A / A write current I _{1 of} cm ² flows. As a result, in the magnetoresistive effect element _RM , the magnetization reversal of the free magnetic layer occurs so that the magnetization direction with respect to the fixed magnetic layer is antiparallel, and the resistance state changes from the low resistance state to the high resistance state. Accordingly, the element resistance of the magnetoresistive element R _M is increased to 40 k.OMEGA, reset to the high resistance state of the magnetoresistive element R _M is completed.

Then, the information recorded to the resistance memory element R _R, are transferred to the magnetoresistive element R _M. Transfer of information to the magnetoresistive element R _M is performed by applying a predetermined drive voltage between the terminals V0 and the terminal V1. Here, between the terminals V0 and the terminal V1, a voltage lower than either of the set voltage and the reset voltage of the resistance memory element R _R, magnetic reversal current only when the resistance memory element R _R is in the low resistance state A voltage at which a write current having a current density equal to or higher than the density (5 × 10 ⁵ A / cm ² ) flows, for example, 4 V is applied. That is, for example, 0V is applied to the terminal V0, and 4V is applied to the terminal V1, for example.

At this time, when the resistance memory element R _R is in the low resistance state (40 k.OMEGA) is the magnetoresistive element R _M is the applied voltage of approximately 2V is, the magnetization reversal current density above the current density ⁽⁵ × 10 5 A / Cm ² ), the write current I ₂ flows from the terminal V1 toward the terminal V0. Thereby, in the magnetoresistive effect element _RM , the magnetization reversal of the free magnetic layer occurs so that the magnetization direction with respect to the fixed magnetic layer is parallel, and the resistance state changes from the high resistance state to the low resistance state.

On the other hand, if the resistance memory element R _R has a high resistance (400 kilohms), the voltage applied to the magnetoresistive element R _M is about 0.4V, the current density of the current flowing through the magnetoresistive element R _M Is about 1 × 10 ⁵ A / cm ^2, which is lower than the magnetization reversal current density. Thereby, in the magnetoresistive effect element _RM , the magnetization reversal of the free magnetic layer does not occur, and the magnetoresistive effect element _RM is maintained in the high resistance state.

Thus, when information recorded in the resistance memory element R _R is any resistance state can also be directly transfers the information to the magnetoresistive element R _M.

Thereafter, the magnetoresistive element R _M the transfer of the information recorded in the resistance memory element R _R is used as a work memory.

Reading information from the magnetoresistance effect element R _M is flowed predetermined read current between the terminal V1 and the terminal V2, by detecting the potential difference between the terminals V1 and the terminal V2. When the read current value is, for example 0.01mA to flow between the terminal V1 and the terminal V2, when the magnetoresistive element _{R M} is in the low resistance state (13.3kΩ), between the terminal V1 and the terminal V2 0 A read voltage of 133 V is output. Moreover, when the magnetoresistive element _{R M} has a high resistance (40 k.OMEGA), a read voltage of 0.4V is outputted between the terminals V1 and the terminal V2. Therefore, a magnetic resistance effect element R _M is in the case of the high-resistance state in the case of the low-resistance state, to secure a sufficient read voltage margin of approximately 0.266V.

Rewriting of information recorded on the magnetoresistive element R _M is carried out by passing a write current of the magnetization reversal current density above the current density by applying a predetermined drive voltage between the terminals V1 and the terminal V2.

Then, if necessary initialization of working memory, by the same procedure as described above, again performing the transfer of information from the reset and the resistance memory element R _R information of the magnetoresistive element R _M.

In the above procedure has been reset the record information of the magnetoresistive element R _M to the high resistance state can also be reset to a low resistance state.

To reset the magnetoresistive element R _M in the low resistance state, 0V is applied to, for example, in the terminal V2, is applied, for example, 2V voltage terminal V1. Thus, the magnetoresistive element _{R M} from the terminal V1 to the terminal V2 direction, a current density of about 5 × ¹⁰ 5 A / cm ² of the write current flows. Thereby, in the magnetoresistive effect element _RM , the magnetization reversal of the free magnetic layer occurs so that the magnetization direction with respect to the fixed magnetic layer is parallel, and the resistance state changes from the high resistance state to the low resistance state. Accordingly, the element resistance of the magnetoresistive element R _M is reduced to 13.3Keiomega, reset to the low resistance state of the magnetoresistive element R _M is completed.

Transfer of information to the magnetoresistive element R _M is performed by applying a predetermined drive voltage between the terminals V0 and the terminal V1. Here, between the terminals V0 and the terminal V1, the resistance memory element R and a set voltage and a voltage lower than any of the reset voltage of the _R, the resistance memory element R _R only magnetization reversal current when the low resistance state A voltage at which a write current having a current density equal to or higher than the density (5 × 10 ⁵ A / cm ² ) flows, for example, 2.7 V is applied. That is, for example, 2.7 V is applied to the terminal V0, and 0 V is applied to the terminal V1, for example.

At this time, when the resistance memory element R _R is in the low resistance state (40 k.OMEGA), the voltage of about 0.7V is applied to the magnetoresistive element R _M, the magnetization reversal current density above the current density (5 × 10 ⁵ A / cm ² ) flows from the terminal V0 toward the terminal V1. As a result, in the magnetoresistive effect element _RM , the magnetization reversal of the free magnetic layer occurs so that the magnetization direction with respect to the fixed magnetic layer becomes antiparallel, and the resistance state changes from the low resistance state to the high resistance state.

On the other hand, if the resistance memory element R _R has a high resistance (400 kilohms), the voltage applied to the magnetoresistive element R _M is about 0.1 V, the current density of the current flowing through the magnetoresistive element R _M Is about 0.6 × 10 ⁵ A / cm ^2, which is lower than the magnetization reversal current density. Thereby, in the magnetoresistive effect element _RM , the magnetization reversal of the free magnetic layer does not occur, and the magnetoresistive effect element _RM is maintained in the low resistance state.

In this case, although contrary to transcribed resistance state to the resistive state and the magnetoresistive element R _M of the resistance memory element R _R, information "0", "1" and the resistance memory element R _R and the magnetoresistive element R _If the correspondence relationship with the resistance state of _M is defined in advance, there is no problem in use.

  Next, the specific structure of the semiconductor memory device according to the present embodiment will be explained with reference to FIGS.

FIG. 3 is a circuit diagram showing an example of a memory cell array configured using the unit element structure of FIG. As shown in FIG. 3, one memory cell MC has a one cell selection transistor Tr, a resistance memory element R _R, and a magneto-resistive element R _M. The source terminal of the cell selection transistor Tr is connected to the source line SL (SL1), and the gate terminal is connected to the word line WL (WL1). One end of the resistance memory element R _R and the magnetoresistive element R _M is connected to the drain terminal of the cell selection transistor Tr. The other end of the resistance memory element _{R R} and the magnetoresistive element _{R M} are connected to each separate bit line BL (BL11, BL12). Such memory cells MC are formed adjacent to each other in the column direction (vertical direction in the drawing) and the row direction (horizontal direction in the drawing).

  A plurality of word lines WL1, WL2, WL3,... Are arranged in the column direction, and constitute a common signal line for the memory cells MC arranged in the column direction. Further, source lines SL1, SL2,... Are arranged in the column direction, and constitute a common signal line for the memory cells MC arranged in the column direction.

  In the row direction (horizontal direction in the drawing), a plurality of bit lines BL11, BL12, BL21, BL22, BL31, BL32... Are arranged to constitute a common signal line for the memory cells MC arranged in the row direction.

  4 and 5 are a plan view and a schematic sectional view showing a specific element structure for realizing the circuit configuration of FIG. 5A is a cross-sectional view taken along the line AA ′ in FIG. 4, and FIG. 5B is a cross-sectional view taken along the line BB ′ in FIG.

  An element isolation film 32 that defines an element region is formed on the silicon substrate 30. A cell selection transistor having a gate electrode 34 and source / drain regions 36 and 38 is formed in the element region of the silicon substrate 30.

  As shown in FIG. 4, the gate electrode 34 also functions as a word line WL that commonly connects the gate electrodes 34 of cell selection transistors adjacent in the column direction (vertical direction in the drawing).

  On the silicon substrate 10 on which the cell selection transistor is formed, an interlayer insulating film 40 in which a contact plug 44 electrically connected to the source / drain region 36 is embedded is formed.

  A source line 46 electrically connected to the source / drain region 36 via the contact plug 44 is formed on the interlayer insulating film 40 in which the contact plug 44 is embedded.

  An interlayer insulating film 48 is formed on the interlayer insulating film 40 on which the source line 42 is formed. A bit line 50 extending in the row direction (the horizontal direction in the drawing) is formed on the interlayer insulating film 48. On the interlayer insulating film 48 on which the bit line 50 is formed, an interlayer insulating film 52 in which a contact plug 56 electrically connected to the bit line 50 is embedded is formed.

  On the interlayer insulating film 52 in which the contact plug 56 is embedded, a lower electrode 58 electrically connected to the bit line 50 through the contact plug 56, and a resistance memory material layer 60 formed on the lower electrode 58, A resistance memory element 64 having an upper electrode 62 formed on the resistance memory material layer 60 is formed.

  On the interlayer insulating film 52 on which the resistance memory element 64 is formed, an interlayer insulating film 66 in which a contact plug 74 electrically connected to the upper electrode 62 of the resistance memory element 64 is embedded is formed. Contact plugs 72 electrically connected to the source / drain regions 38 are embedded in the interlayer insulating films 66, 52, 48 and 40.

  On the interlayer insulating film 66 in which the contact plugs 72 and 74 are embedded, a lower electrode layer 76 that electrically connects the contact plugs 72 and 74 is formed. A magnetoresistive element 90 is formed on the lower electrode layer 72. As shown in FIG. 6, the magnetoresistive effect element 90 includes a base layer 78 formed on the lower electrode layer 76, an antiferromagnetic layer 80 formed on the base layer 78, and the antiferromagnetic layer 80. The pinned magnetic layer 82 is formed of a ferromagnetic layer 82c / nonmagnetic layer 82b / ferromagnetic layer 82a laminated ferrimagnetic structure, the barrier layer 84 is formed on the pinned magnetic layer 82, and is formed on the barrier layer 84. The free magnetic layer 86 and a cap layer 88 formed on the free magnetic layer 86.

  An interlayer insulating film 92 in which a contact plug 96 electrically connected to the magnetoresistive effect element 90 is embedded is formed on the interlayer insulating film 66 on which the lower electrode layer 76 and the magnetoresistive effect element 90 are formed. .

  On the interlayer insulating film 92, a bit line 98 is formed which is electrically connected to the magnetoresistive effect element 90 via a contact plug 96 and extends in the row direction (lateral direction in the drawing).

  Thus, the semiconductor memory device having the circuit configuration shown in FIG. 3 is configured.

  Next, the method for fabricating the semiconductor memory device according to the present embodiment will be explained with reference to FIGS. 7 to 9 are process cross-sectional views taken along the line AA 'in FIG. 4, and FIGS. 10 to 12 are process cross-sectional views taken along the line BB' in FIG.

  First, an element isolation film 32 that defines an element region is formed in the silicon substrate 30 by, for example, STI (Shallow Trench Isolation).

  Next, a cell selection transistor having a gate electrode 34 and source / drain regions 36 and 38 is formed on the element region of the silicon substrate 30 in the same manner as in a normal MOS transistor manufacturing method (FIG. 7A). 10 (a)).

  Next, on the silicon substrate 30 on which the cell selection transistor is formed, a silicon oxide film is deposited by, for example, a CVD method to form an interlayer insulating film 40 made of the silicon oxide film.

  Next, contact holes 42 reaching the source / drain regions 36 are formed in the interlayer insulating film 40 by lithography and dry etching.

  Next, after depositing a barrier metal and a tungsten film by, for example, a CVD method, these conductive films are etched back to form contact plugs 44 electrically connected to the source / drain regions 36 in the contact holes 42.

  Next, a source line 46 electrically connected to the source / drain region 36 through the contact plug 44 is formed on the interlayer insulating film 40 in which the contact plug 44 is embedded (FIG. 7B, FIG. 10). b)).

  Next, a silicon oxide film is deposited on the interlayer insulating film 40 on which the source line 46 is formed by, for example, a CVD method, and an interlayer insulating film 48 made of a silicon oxide film is formed.

  Next, the bit line 50 is formed on the interlayer insulating film 48 (FIGS. 7C and 10C).

  Next, a silicon oxide film is deposited on the interlayer insulating film 48 on which the bit line 50 is formed by, for example, a CVD method, and an interlayer insulating film 52 made of a silicon oxide film is formed.

  Next, a contact hole 54 reaching the bit line 50 is formed in the interlayer insulating film 52 by lithography and dry etching.

  Next, after depositing a barrier metal and a tungsten film by, for example, the CVD method, the conductive film is etched back to form a contact plug 56 electrically connected to the bit line 50 in the contact hole 54 (FIG. 8A). ), FIG. 11 (a)).

Next, on the interlayer insulating film 52 in which the contact plugs 56 are embedded, for example, a lower electrode 58 made of platinum, a resistance memory material layer 60 made of Pr _1-x Ca _x MnO ₃ , and an upper electrode 62 made of platinum, for example. The resistance memory element 64 having the following is formed (FIG. 11B). Platinum constituting the lower electrode 58 and the upper electrode 62 can be formed by, for example, sputtering. The resistance memory material layer 60 made of Pr _1-x Ca _x MnO ₃ can be formed by a laser ablation method, a sol-gel method, a sputtering method, an MOCVD method, or the like.

The lower electrode 58 and the upper electrode 62 are made of, for example, Ir, W, Ni, Au, Cu, Ag, Pd, Zn, Cr, Al, Mn, Ta, Si, TaN, TiN, Ru, ITO, NiO, in addition to platinum. _IrO, can be formed _{SrRuO, CoSi 2, WSi 2,} NiSi, MoSi 2, TiSi 2, Al-Si, Al-Cu, the Al-Si-Cu or the like. In addition to Pr _1-x Ca _x MnO ₃ , the resistance memory material layer 60 includes TiO _x , NiO _x , YO _x , CeO _x , MgO _x , ZnO _x , ZrO _x , HfO _x , WO _x , NbO _x , Including TaO _x , CrO _x , MnO _x , AlO _x , VO _x , SiO _x, etc., La _1-x Ca _x MnO ₃ , SrTiO ₃ , YBa ₂ Cu ₃ O _y , LaNiO and other metals and semiconductor atoms It can be formed of an oxide material.

  Next, a silicon oxide film is deposited on the interlayer insulating film 52 on which the resistance memory element 64 is formed by, for example, a CVD method to form an interlayer insulating film 66 made of a silicon oxide film.

  Next, a contact hole 68 reaching the source / drain region 38 and a contact hole 70 reaching the upper electrode 62 of the resistance memory element 64 are formed in the interlayer insulating film 66 by lithography and dry etching.

  Next, after depositing a barrier metal and a tungsten film by, for example, a CVD method, the conductive film is etched back, and contact plugs 72 electrically connected to the source / drain regions 38 are formed in the contact holes 68 and 70, and resistance memory. Contact plugs 74 electrically connected to the upper electrode 62 of the element 64 are respectively formed (FIGS. 8B and 11C).

  Next, on the interlayer insulating film 66 in which the contact plugs 72 and 74 are embedded, a lower electrode layer 76 made of, for example, Ta and electrically connecting the plug 72 and the plug 74 to the source / drain region 38, and a lower electrode layer The magnetoresistive effect element 90 formed on 76 is formed (FIGS. 9A and 12A).

  For example, as shown in FIG. 6, the magnetoresistive element 90 includes an underlayer 78 made of NiFe formed on the lower electrode layer 76, an antiferromagnetic layer 80 made of IrMn formed on the underlayer 78, and A pinned magnetization layer 82 having a laminated ferri structure formed of a ferromagnetic layer 82a made of CoFe, a nonmagnetic layer 82b made of Ru, and a ferromagnetic layer 82c made of CoFeB, formed on the antiferromagnetic layer 80, and fixed magnetization A barrier layer 84 made of MgO formed on the layer 82, a free magnetic layer 86 made of CoFeB formed on the barrier layer 84, and a cap layer (upper electrode layer made of Ta formed on the free magnetic layer 86) 88).

  Next, a silicon oxide film is deposited on the interlayer insulating film 66 on which the lower electrode layer 76 and the magnetoresistive effect element 90 are formed by, for example, a CVD method to form an interlayer insulating film 92 made of a silicon oxide film.

  Next, a contact hole 94 reaching the magnetoresistive effect element 90 is formed in the interlayer insulating film 92 by lithography and dry etching.

  Next, after depositing a barrier metal and a tungsten film by, for example, the CVD method, the conductive film is etched back, and a contact plug 96 electrically connected to the magnetoresistive effect element 90 is formed in the contact hole 94.

Next, a bit line 98 electrically connected to the magnetoresistive effect element 90 through the contact plug 96 is formed on the interlayer insulating film 92 in which the contact plug 96 is embedded.
(FIG. 9B, FIG. 12B).

  Thereafter, if necessary, an upper wiring layer is formed, and the semiconductor memory device according to the present embodiment is completed.

  As described above, according to the present embodiment, one memory cell includes a magnetoresistive effect element and a resistance memory element, the magnetoresistive effect element is used as a work memory, and the resistance memory element is used as a storage memory. In addition, a non-volatile work memory can be configured. In addition, since the transfer of information from the resistance memory element to the magnetoresistive effect element can be performed only by applying a predetermined drive voltage to the serial connection body of the resistance memory element and the magnetoresistive effect element, the magnetoresistive effect element is desired. It is possible to initialize to the state at high speed.

  In addition, the resistance memory element and the magnetoresistive effect element can be stacked in the vertical direction. Thereby, the floor area required for the unit memory cell can be significantly reduced, and the degree of integration of the semiconductor memory device can be improved.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the above-described embodiment, the resistance memory element 64 and the magnetoresistive effect element 90 are stacked on the silicon substrate 10. However, these elements are not necessarily stacked. The semiconductor memory device of the present invention is based on the circuit configuration shown in FIG. 3, and the arrangement of each element is not limited to the structure shown in FIG. For example, in FIG. 5, the resistance memory element 64 and the magnetoresistive effect element 90 can be formed on the lower electrode layer 76, and the bit lines 50 and 98 can be formed on the interlayer insulating film 92.

  In the above embodiment, the stored information of the magnetoresistive effect element 90 is reset by spin injection, but the stored information is reset by applying a magnetic field in a predetermined direction to the magnetoresistive effect element 90 to reverse the magnetization of the free magnetic layer. May be. In this case, it is possible to reset all or a specific block of magnetoresistive elements at once.

  In the above-described embodiment, the case where the TMR type spin injection magnetization reversal element configured by sandwiching the tunnel insulating film between the two ferromagnetic layers is applied as the magnetoresistive effect element has been described. Further, the present invention can be similarly applied to a GMR type spin injection magnetization reversal element configured by sandwiching a nonmagnetic metal intermediate layer such as Cu, Ag, Au, or Ru.

  As described above in detail, the features of the present invention are summarized as follows.

(Additional remark 1) It has a pair of electrodes and a resistance memory layer made of a resistance memory material formed between the pair of electrodes, stores a high resistance state and a low resistance state, and applies the voltage or current to A resistance memory element that switches between a high resistance state and the low resistance state;
A pair of electrodes and a laminate formed by laminating a fixed magnetic layer, a nonmagnetic layer, and a free magnetic layer formed between the pair of electrodes, the magnetization direction of the fixed magnetic layer and the magnetization of the free magnetic layer A magnetoresistive effect element whose resistance value changes according to the relationship with the direction,
One of the pair of electrodes of the resistance memory element is connected to one of the pair of electrodes of the magnetoresistive effect element. A semiconductor memory device, wherein:

(Supplementary note 2) In the semiconductor memory device according to claim 1,
When initializing information recorded in the magnetoresistive effect element, a voltage is applied between the other of the pair of electrodes of the resistance memory element and the other of the pair of electrodes of the magnetoresistive effect element. And an information initialization means for transferring the information recorded in the resistance memory element to the magnetoresistive effect element by applying a current corresponding to the resistance state of the resistance memory element to the magnetoresistive effect element. A semiconductor memory device comprising:

(Appendix 3) In the semiconductor memory device according to claim 1 or 2,
The semiconductor memory device, wherein the magnetoresistive effect element is a spin injection magnetization reversal element that performs magnetization reversal of the free magnetic layer by spin injection.

(Appendix 4) In the semiconductor memory device according to any one of claims 1 to 3,
The semiconductor further comprising a cell selection transistor connected to a connection portion between the one of the pair of electrodes of the resistance memory element and the one of the pair of electrodes of the magnetoresistive effect element. Storage device.

(Additional remark 5) It has a resistance memory layer which consists of a pair of electrodes and the resistance memory material formed between the pair of electrodes, memorizes a high resistance state and a low resistance state, and applies the voltage or current to A resistance memory element that switches between a high-resistance state and the low-resistance state; a pair of electrodes; and a stacked body that is formed between the pair of electrodes and includes a fixed magnetic layer, a nonmagnetic layer, and a free magnetic layer. And a magnetoresistive effect element whose resistance value changes in accordance with the relationship between the magnetization direction of the fixed magnetization layer and the magnetization direction of the free magnetization layer, and one of the pair of electrodes of the resistance memory element And a driving method of a semiconductor memory device in which one of the pair of electrodes of the magnetoresistive effect element is connected,
When initializing information recorded in the magnetoresistive effect element, a voltage is applied between the other of the pair of electrodes of the resistance memory element and the other of the pair of electrodes of the magnetoresistive effect element. The information recorded in the resistive memory element is transferred to the magnetoresistive effect element by applying a current corresponding to the resistance state of the resistive memory element to the magnetoresistive effect element. A method for driving a storage device.

(Supplementary Note 6) In the semiconductor memory device driving method according to claim 5,
The voltage applied between the other of the pair of electrodes of the resistance memory element and the other of the pair of electrodes of the magnetoresistive element is such that the resistance memory element is in the low resistance state. The semiconductor is characterized in that a current that is equal to or higher than a magnetization reversal current density at which the free magnetic layer undergoes magnetization reversal sometimes flows, and a current that is smaller than the magnetization reversal current density flows when the resistance memory element is in the high resistance state. A method for driving a storage device.

(Supplementary note 7) In the driving method of the semiconductor device according to claim 5 or 6,
A method of driving a semiconductor memory device, comprising: resetting information recorded in the magnetoresistive effect element before transferring the information recorded in the resistive memory element to the magnetoresistive effect element.

1 is a circuit diagram showing a basic structure of a semiconductor memory device according to an embodiment of the present invention. 1 is a schematic cross-sectional view showing a basic structure of a semiconductor memory device according to an embodiment of the present invention. 1 is a circuit diagram showing a structure of a semiconductor memory device according to an embodiment of the present invention. 1 is a plan view showing a structure of a semiconductor memory device according to an embodiment of the present invention. It is a schematic sectional drawing which shows the structure of the semiconductor memory device by one Embodiment of this invention. It is a schematic sectional drawing which shows the structure of the magnetoresistive effect element in the semiconductor memory device by one Embodiment of this invention. FIG. 6 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor memory device according to the embodiment of the present invention; It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor memory device by one Embodiment of this invention. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor memory device by one Embodiment of this invention. It is process sectional drawing (the 4) which shows the manufacturing method of the semiconductor memory device by one Embodiment of this invention. It is process sectional drawing (the 5) which shows the manufacturing method of the semiconductor memory device by one Embodiment of this invention. It is process sectional drawing (the 6) which shows the manufacturing method of the semiconductor memory device by one Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 14, 26 ... Electrode 12 ... Resistance memory material layer 16 ... Resistance memory element 18 ... Antiferromagnetic layer 20 ... Fixed magnetization layer 22 ... Barrier layer 24 ... Free magnetization layer 28 ... Magnetoresistive effect element 30 ... Silicon substrate 32 ... Element isolation film 34 ... gate electrodes 36, 38 ... source / drain regions 40, 48, 52, 66, 92 ... interlayer insulating films 42, 54, 68, 70, 94 ... contact holes 44, 56, 72, 74, 96 ... Contact plug 46 ... Source line 50, 98 ... Bit line 58 ... Lower electrode 60 ... Resistance memory material layer 62 ... Upper electrode 64 ... Resistance memory element 76 ... Lower electrode layer 78 ... Underlayer 80 ... Antiferromagnetic layer 82 ... Fixed magnetization Layers 82a, 82c ... Ferromagnetic layer 82b ... Nonmagnetic layer 84 ... Barrier layer 86 ... Free magnetic layer 88 ... Cap layer 90 ... Magnetoresistive effect element

Claims (5)

A resistance memory layer made of a resistance memory material formed between the pair of electrodes, storing a high resistance state and a low resistance state, and applying the voltage or current to the high resistance state; A resistance memory element that switches between the low resistance states;
A pair of electrodes and a laminate formed by laminating a fixed magnetic layer, a nonmagnetic layer, and a free magnetic layer formed between the pair of electrodes, the magnetization direction of the fixed magnetic layer and the magnetization of the free magnetic layer A magnetoresistive effect element whose resistance value changes according to the relationship with the direction,
One of the pair of electrodes of the resistance memory element is connected to one of the pair of electrodes of the magnetoresistive effect element. A semiconductor memory device, wherein: The semiconductor memory device according to claim 1.
When initializing information recorded in the magnetoresistive effect element, a voltage is applied between the other of the pair of electrodes of the resistance memory element and the other of the pair of electrodes of the magnetoresistive effect element. And an information initialization means for transferring the information recorded in the resistance memory element to the magnetoresistive effect element by applying a current corresponding to the resistance state of the resistance memory element to the magnetoresistive effect element. A semiconductor memory device comprising: A resistance memory layer made of a resistance memory material formed between the pair of electrodes, storing a high resistance state and a low resistance state, and applying the voltage or current to the high resistance state; A resistance memory element that switches between the low resistance state, a pair of electrodes, and a stacked body that is formed between the pair of electrodes and includes a fixed magnetic layer, a nonmagnetic layer, and a free magnetic layer, and A magnetoresistive effect element whose resistance value changes in accordance with the relationship between the magnetization direction of the magnetization layer and the magnetization direction of the free magnetization layer, and one of the pair of electrodes of the resistance memory element and the magnetoresistance A method of driving a semiconductor memory device in which one of the pair of electrodes of an effect element is connected,
When initializing information recorded in the magnetoresistive effect element, a voltage is applied between the other of the pair of electrodes of the resistance memory element and the other of the pair of electrodes of the magnetoresistive effect element. The information recorded in the resistive memory element is transferred to the magnetoresistive effect element by applying a current corresponding to the resistance state of the resistive memory element to the magnetoresistive effect element. A method for driving a storage device. The method of driving a semiconductor memory device according to claim 3.
The voltage applied between the other of the pair of electrodes of the resistance memory element and the other of the pair of electrodes of the magnetoresistive element is such that the resistance memory element is in the low resistance state. The semiconductor is characterized in that a current that is equal to or higher than a magnetization reversal current density at which the free magnetic layer undergoes magnetization reversal sometimes flows, and a current that is smaller than the magnetization reversal current density flows when the resistance memory element is in the high resistance state. A method for driving a storage device. The method for driving a semiconductor device according to claim 3 or 4,
A method of driving a semiconductor memory device, comprising: resetting information recorded in the magnetoresistive effect element before transferring the information recorded in the resistive memory element to the magnetoresistive effect element.

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