JP2007251571A - Phase synchronization circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To apply appropriate loop filter characteristics according to only jitter of an input signal. <P>SOLUTION: A phase synchronization circuit which outputs an oscillation signal for phase synchronization with the input signal is provided with a phase comparator 11 which detects a phase difference between an input signal IN and an oscillation output OUT; a loop filter 12 which integrates the comparison output of the phase comparator; and an oscillation circuit 13 which creates the oscillation output of a frequency corresponding to the loop filter output. It is also provided with a PLL circuit 21 which creates a reference signal PL which establishes phase synchronization with the input signal, and whose phase noise is sufficiently small; a phase comparator 22 which detects a phase difference between the input signal and the reference signal; a low pass filter 23 which integrates the comparison output of the phase comparator; and a filter control unit 24 which calculates a first frequency f1 based on a frequency component which is obtained by performing frequency analysis of output of the low pass filter, and simultaneously controls a bandwidth of the loop filter 12 by a second frequency f2 which is lower and in a fixed relation of the first frequency. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a phase synchronization circuit, and more specifically, integrates a first phase comparator that detects a phase difference between an input signal and a first oscillation output, and a comparison output of the first phase comparator. A first loop filter; and a first oscillation circuit that generates the first oscillation output having a frequency corresponding to the output of the first loop filter; and a phase that outputs an oscillation signal that is phase-synchronized with an input signal The present invention relates to a synchronization circuit.

  The phase synchronization circuit is used for the purpose of suppressing jitter of an input signal (clock signal) in a communication device or the like and changing the clock frequency. The jitter of the input signal is suppressed by the loop filter in the phase locked loop, but the cutoff frequency (bandwidth) of the loop filter is changed appropriately according to the environment (communication system characteristics, etc.) in which the phase locked loop is used. There is a need to.

Conventionally, a loop filter having a plurality of types of bands is provided in advance, the phase difference between the input reference signal and the output signal of the VCO is compared to monitor the jitter component of the comparison signal, and the detected jitter component There is known a PLL synchronization circuit that selects a loop filter suitable for reducing the noise (Patent Document 1).
JP 04-096514 (Summary, FIG. 1)

  However, when the phase difference between the input signal and the VCO output is monitored as in the above prior art, the jitter to be monitored affects not only the jitter of the input signal but also the jitter of the VCO output at the same time. Therefore, the loop filter cannot be switched appropriately.

  The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide a phase locked loop circuit to which an appropriate loop filter characteristic can be applied in accordance with only the jitter of an input signal.

  The above problem is solved by the configuration of FIG. That is, the phase locked loop circuit of the present invention (1) is a comparison between the first phase comparator 11 that detects the phase difference between the input signal IN and the first oscillation output OUT, and the first phase comparator. A first loop filter that integrates the output; and a first oscillation circuit that generates the first oscillation output having a frequency corresponding to the output of the first loop filter, and is phase-synchronized with the input signal. A phase synchronization circuit for outputting an oscillation signal, which is phase-synchronized with the input signal and generates a reference signal PL with sufficiently less phase noise than the input signal; and between the input signal and the reference signal Based on the frequency component obtained by frequency analysis of the output of the low-pass filter, the second phase comparator 22 for detecting the phase difference of the second phase comparator 22, the low-pass filter 23 for integrating the comparison output of the second phase comparator. The first frequency f1 And a filter control unit 24 for controlling the bandwidth (cut-off frequency) of the first loop filter 12 with a second frequency f2 having a certain relationship lower than the first frequency. is there.

In the present invention (1), the PLL circuit 21 generates the low-jitter reference signal PL and can extract the jitter component from only the input signal IN, thereby quickly following the phase and frequency of the input signal IN. It is possible to easily set a loop filter characteristic capable of sufficiently suppressing the jitter component. Therefore, it is possible to always generate a stable output signal OUT with appropriate response characteristics regardless of various communication environments in which the phase synchronization circuit is used.

  The above problem is solved by the configuration of FIG. 4, for example. That is, the phase synchronization circuit of the present invention (2) includes a first phase comparator 11 for detecting a phase difference between the input signal IN and the first oscillation output OUT, and a comparison between the first phase comparator. A first loop filter that integrates the output; and a first oscillation circuit that generates the first oscillation output having a frequency corresponding to the output of the first loop filter, and is phase-synchronized with the input signal. A phase synchronization circuit for outputting an oscillation signal, a delay circuit 31 for outputting a delay signal DL obtained by delaying the input signal for a predetermined time, and a second phase comparison for detecting a phase difference between the input signal and the delay signal A first frequency f1 based on a frequency component obtained by frequency analysis of the output of the low-pass filter, the low-pass filter 23 for integrating the comparison output of the second phase comparator, and the second phase comparator; Lower than 1 frequency In which and a filter control unit 24 for controlling the first bandwidth of the loop filter 12 (cut-off frequency) by a second frequency f2 which is in a fixed relationship.

  In the present invention (2), the phase synchronization circuit can be provided at low cost by using the delay circuit 31 for generating the reference signal (reference phase) to be compared with the input signal.

  In the present invention (3), in the above-mentioned present invention (1) or (2), the filter control unit corresponds to one having the maximum amplitude among one or more frequency components obtained by frequency analysis of the low-pass filter output. The frequency within the range of 1/10 to 1/100 with respect to the first frequency f1 is set as the second frequency f2. Therefore, an appropriate loop filter corresponding to the main component of input jitter can be set.

  In the present invention (4), in the above-mentioned present invention (1) or (2), the filter control unit is the lowest frequency among one or more frequency components exceeding a predetermined threshold obtained by frequency analysis of the low pass filter output. The frequency in the range of 1/10 to 1/100 with respect to the first frequency f1 corresponding to the first frequency f1 is set as the second frequency f2. Accordingly, an appropriate loop filter can be set in consideration of the low frequency component of input jitter.

  In the present invention (5), in the present invention (1) to (4), the first loop filter 12 is constituted by a digital filter.

  As described above, according to the present invention, it is possible to always generate a stable output signal OUT with appropriate response characteristics regardless of various communication environments in which the phase synchronization circuit is used, which contributes to improving the reliability of the phase synchronization circuit. There is a lot to do.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. Note that the same reference numerals denote the same or corresponding parts throughout the drawings.

FIG. 1 is a block diagram of a phase synchronization circuit according to the first embodiment, and shows a case where a PLL circuit is used as a jitter measurement circuit for an input clock signal. In the figure, 11 is a phase comparator for detecting the phase difference between the input clock signal IN and the oscillation output OUT of the VCO 13, 12 is a loop filter for integrating the comparison output (phase error) E1 of the phase comparator 11, 13 Is a voltage controlled oscillator (VCO) that generates a clock signal OUT having a frequency corresponding to the output signal V1 of the loop filter 12, 20 is a jitter measuring circuit that detects a jitter component of the input signal IN, and 22 is a clock signal IN and PLL of the input clock signal IN. A phase comparator that detects a phase difference from the oscillation output PL of the circuit 21; 23, a low-pass filter that integrates the comparison output of the phase comparator 22; 24, frequency analysis of the output signal of the low-pass filter; It is a filter control part which switches the response characteristic of the loop filter 12 according to it.

  The PLL circuit 21 is phase-synchronized with the input signal IN, and generates a reference clock signal PL with sufficiently less phase noise than the input signal. The configuration of the PLL circuit 21 is shown in the inset (a). In the figure, 41 is a phase comparator that compares the phase between the input signal IN and the oscillation output PL of the VCO 43, 42 is a loop filter that integrates the comparison output E3 of the phase comparator 41, and 43 is an output signal of the loop filter 42. A voltage controlled oscillator (VCO) that generates a clock signal PL having a frequency corresponding to V3.

  The PLL circuit 21 includes the VCO 43 having excellent phase noise characteristics, and the cut-off frequency (band) of the loop filter 42 is set sufficiently lower than the expected jitter of the input signal IN. The reference clock signal PL with little jitter and phase-synchronized with the input signal IN is obtained.

  FIG. 3 shows an operation timing chart of the jitter measuring circuit according to the first embodiment. The input clock signal IN includes jitter, and the relative delay phase (when the period is long) is −1 and the reference phase is 0, with reference to the period corresponding to the nominal frequency of the clock signal IN. The phase (when the period is short) is represented by +1. On the other hand, the reference signal PL output from the PLL circuit 21 is phase-synchronized with the input signal IN and contains almost no jitter component. In this state, the phase comparator 22 compares the phase between the input signal IN and the reference signal PL. When the phase of the input signal IN is delayed, the error signal E2 = + 1, and when the phase is the same, E2 = When 0, the comparison result signal of error signal E2 = -1 is output. The low-pass filter 23 integrates the comparison signal (phase error signal) E2 and outputs an integration signal V2. This integrated signal V2 reflects the jitter component of the input signal IN.

  In FIG. 1, the filter control unit 24 analyzes the frequency of the output signal V2 of the low-pass filter 23 using an FFT calculator (not shown) or the like, and based on the obtained one or more frequency components (sequential), the output signal V2 The first frequency f1 representing the frequency is obtained, and the bandwidth (cut-off frequency) f2 of the loop filter 12 is controlled by the second frequency f2 having a constant relationship lower than the first frequency f1. .

  FIG. 2A shows a configuration of an example loop filter 12. This loop filter 12 is composed of a lag / lead type active filter, and R11, R21, C11 and the like are added / deleted by the switch circuits S1 to S3 on the basis of the values of the respective elements R1, R2 and C. Thus, the closed-loop transfer function of the phase locked loop can be changed.

  That is, according to a reference document (“PLL frequency synthesizer / circuit design method” written by Toshiyuki Ozawa: Soken Publishing Co., Ltd.), a closed-loop transfer function M (s) = OUT (s) / OUT of a phase locked loop using an active filter 12 IN (s) can be expressed by the absolute | M (jω) |

Given in. Here, the natural angular frequency ωn is

And the damping factor ζ is

Given in. Here, the loop gain K is given by the product of the phase comparator gain Kp and the VCO sensitivity Kv.

  FIG. 2B shows the frequency characteristics of the transfer function | M (jω) | of the phase locked loop. The cutoff frequency (bandwidth) f2 of the phase locked loop circuit is expressed by the following equation (4) by solving | M (jω) | = 1 / √2 (−3 dB):

Given in. That is, the cutoff frequency f2 of the phase synchronization circuit is a function of the damping factor ζ, and in this embodiment, for example, ζ = 0.707 is selected in consideration of the response speed and overshoot of the circuit. .

  Therefore, the values of R1, R2, and C for obtaining a desired cutoff frequency f2 can be determined from the above equation (3). In the present embodiment, a set of R11, R12, R21, R22, C11, and C12 for obtaining the desired cut-off frequency f2 is preliminarily tabulated (not shown), and the filter control unit 24 uses the following method. The characteristics of the loop filter 12 are switched with reference to the table at the obtained cutoff frequency f2.

Specifically, if the frequency component dominant in the jitter of the input signal IN is now f1, the loop filter 12 is controlled so that the cutoff frequency f2 of the phase locked loop circuit becomes f2 << f1. However, if the cut-off frequency f2 is too small, the followability to the input signal IN is impaired. Therefore, the cutoff frequency f2 is set as high as possible while satisfying the relationship of f2 << f1. For example, f2 is determined within a range of 1/10 to 1/100 of f1.

  In this case, as the dominant frequency component f1 of the input jitter, for example, the frequency corresponding to the one having the maximum amplitude among one or two or more frequency components obtained by frequency analysis of the output of the low pass filter 23 is the first. Frequency f1. Alternatively, the frequency corresponding to the lowest frequency or the highest frequency among the one or two or more frequency components exceeding the predetermined threshold obtained by frequency analysis of the low-pass filter output is set as the first frequency f1. With the above configuration, it is possible to appropriately output the oscillation signal OUT that is phase-synchronized with the input clock signal IN.

  FIG. 4 is a block diagram of a phase locked loop circuit according to the second embodiment, and shows a case where a delay circuit is used as a jitter measurement circuit for an input signal. In the figure, 30 is a jitter measurement circuit, and 31 is a delay circuit that delays the input signal IN by a predetermined time (one period corresponding to the nominal frequency). Other configurations may be the same as those described in FIG. In the second embodiment, since the reference clock signal is not provided, the input jitter detection accuracy is inferior. However, since the oscillator 43 having excellent phase noise characteristics as used in the PLL 21 is not required, the cost can be reduced. .

  FIG. 5 shows an operation timing chart of the jitter measuring circuit according to the second embodiment. The input clock signal IN includes jitter similar to that described in FIG. The delay circuit 31 delays the input signal IN by a predetermined time (one period corresponding to the nominal frequency). In this state, the phase comparator 22 compares the phase between the input signal IN and the delay signal DL, and the error signal E2 = −1 when the phase of the input signal IN advances, and E2 when the phase is the same. = 0, and when delayed, a comparison result signal of error signal E2 = + 1 is output. The low-pass filter 23 integrates the comparison signal (phase error signal) E2 and outputs an integration signal V2. This integrated signal V2 reflects the jitter component of the input signal IN. The operations for other configurations may be the same as those described in the first embodiment.

  In the above embodiment, a lag / lead type active filter is used as the loop filter 12, but the present invention is not limited to this. A normal lag filter, lag lead filter, or the like may be used. Further, if the loop filter 12 is constituted by a digital filter and is made into an LSI, the characteristics of the loop filter 12 can be changed only by changing the filter coefficient inside the LSI.

  Moreover, although several embodiment suitable for the said invention was described, it cannot be overemphasized that the structure of each part, control, a process, and these combination can be variously changed within the range which does not deviate from this invention. .

1 is a block diagram of a phase synchronization circuit according to a first embodiment. FIG. It is a figure explaining the loop filter by embodiment. 4 is an operation timing chart of the jitter measurement circuit according to the first embodiment. It is a block diagram of the phase locked loop circuit by 2nd Embodiment. It is an operation | movement timing chart of the jitter measuring circuit by 2nd Embodiment.

Explanation of symbols

11 Phase comparator 12 Loop filter 13 Voltage controlled oscillator (VCO)
20 Jitter Measurement Circuit 21 PLL Circuit 22 Phase Comparator 23 Low Pass Filter 24 Filter Control Unit 31 Delay Circuit

Claims (5)

A first phase comparator for detecting a phase difference between an input signal and a first oscillation output; a first loop filter for integrating a comparison output of the first phase comparator; and the first loop A first synchronization circuit that generates the first oscillation output having a frequency corresponding to the output of the filter, and outputs an oscillation signal that is phase-synchronized with an input signal,
A PLL circuit that is phase-synchronized with the input signal and generates a reference signal with sufficiently less phase noise than the input signal;
A second phase comparator for detecting a phase difference between the input signal and a reference signal;
A low-pass filter for integrating the comparison output of the second phase comparator;
A first frequency is obtained based on a frequency component obtained by frequency analysis of the output of the low-pass filter, and the second loop having a certain relationship lower than the first frequency uses the second frequency of the first loop filter. A phase synchronization circuit comprising: a filter control unit that controls a bandwidth. A first phase comparator for detecting a phase difference between an input signal and a first oscillation output; a first loop filter for integrating a comparison output of the first phase comparator; and the first loop A first synchronization circuit that generates the first oscillation output having a frequency corresponding to the output of the filter, and outputs an oscillation signal that is phase-synchronized with an input signal,
A delay circuit for outputting a delayed signal obtained by delaying the input signal for a predetermined time;
A second phase comparator for detecting a phase difference between the input signal and the delayed signal;
A low-pass filter for integrating the comparison output of the second phase comparator;
A first frequency is obtained based on a frequency component obtained by frequency analysis of the output of the low-pass filter, and the second loop having a certain relationship lower than the first frequency uses the second frequency of the first loop filter. A phase synchronization circuit comprising: a filter control unit that controls a bandwidth. The filter control unit is within a range of 1/10 to 1/100 with respect to the first frequency corresponding to the maximum amplitude among one or more frequency components obtained by frequency analysis of the low-pass filter output. 3. The phase locked loop according to claim 1, wherein the frequency is a second frequency. The filter control unit 1/10 to 1/100 with respect to the first frequency corresponding to the lowest frequency among one or more frequency components exceeding a predetermined threshold obtained by frequency analysis of the low-pass filter output. The phase synchronization circuit according to claim 1, wherein a frequency within the range is set as a second frequency. 5. The phase locked loop circuit according to claim 1, wherein the first loop filter is a digital filter.

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