JP2007218972A - Plasma display device - Google Patents

Plasma display device Download PDF

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JP2007218972A
JP2007218972A JP2006036342A JP2006036342A JP2007218972A JP 2007218972 A JP2007218972 A JP 2007218972A JP 2006036342 A JP2006036342 A JP 2006036342A JP 2006036342 A JP2006036342 A JP 2006036342A JP 2007218972 A JP2007218972 A JP 2007218972A
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voltage
plasma display
scan electrode
electrode
potential
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JP2006036342A
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Japanese (ja)
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Yasunori Uchida
保実 内田
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Matsushita Electric Ind Co Ltd
松下電器産業株式会社
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Abstract

There is provided a plasma display device capable of generating and outputting a potential (Vset2) for determining the end of a decrease in voltage applied to a scan electrode in a stable and arbitrarily wide range.
A scan electrode driver 113 for applying a drive voltage to a scan electrode 122 of a plasma display panel 100 includes a resistance (R623) and a constant voltage between a ground potential and a minimum potential. A voltage (Vset2) that determines the timing at which the drive voltage applied to the scan electrode 122 changes from falling to rising from the connection point between the resistance of the series circuit and the constant voltage unit. Is configured to output. A shunt regulator (Q611) is used as the constant voltage unit.
[Selection] Figure 5

Description

  The present invention relates to a plasma display device which is an image display device using a plasma display panel.

  A plasma display panel (hereinafter abbreviated as “panel”) is a display device with excellent visibility characterized by a large screen, a thin shape, and a light weight. Many plasma display devices using this panel have been proposed.

  A panel used in such a conventional plasma display device includes a front glass substrate on which a scan electrode, a sustain electrode, a dielectric layer, and a protective layer are formed, a data electrode, an insulator layer, a barrier rib, and a phosphor layer. The formed rear glass substrate is disposed so as to be opposed to each other, the periphery is sealed, and a discharge gas is sealed therebetween to form a discharge space.

  A drive signal for displaying an image by causing discharge in the discharge space by driving each electrode is input to the scan electrode, the sustain electrode, and the data electrode.

  FIG. 6 shows a driving voltage waveform applied to each electrode in a conventional plasma display device.

  In this conventional plasma display device, a so-called subfield method is used as a method of displaying gradation according to an image. The subfield method is a method in which one field period is divided into a plurality of subfields having different display luminances, and gradation is displayed by a combination of these subfields.

  Each subfield has an initialization period, an address period, and a sustain period. FIG. 6 shows drive voltage waveforms for two subfields (first subfield and second subfield), but the drive waveforms in the other subfields are substantially the same.

  In the initializing period of the first subfield, 0 V is applied to the sustain electrode. At the same time, a ramp voltage that gradually rises from the voltage Vsus toward the voltage (Vset + Vsus) is applied to the scan electrodes.

  Next, a voltage Ve is applied to the sustain electrode, and a ramp voltage that gradually decreases from the voltage Vi3 toward the voltage Vset2 is applied to the scan electrode. As a result, a weak initializing discharge is generated in each discharge cell, and wall charges necessary for the subsequent address operation are formed on the electrodes.

  When the voltage applied to the scan electrode reaches Vset2, the voltage drop ends. The potential Vset2 for determining the end of the fall of the voltage applied to the scan electrode is generated by a shunt regulator from a control voltage of about 15V generated with reference to the lowest voltage Va.

An example of a plasma display device that applies an initializing voltage by such a subfield method is described in Patent Document 1 below.
Japanese Patent Laid-Open No. 2001-236035

  However, in the conventional plasma display device as described above, when the Vset2 voltage increases to near 15V, it is difficult to generate a stable Vset2 voltage from the control voltage unless the control voltage is increased.

  The present invention has been made to solve the above-described problems, and for this purpose, the following configuration is employed.

  The plasma display apparatus according to claim 1, further comprising a scan electrode driver that applies a drive voltage to the scan electrodes of the plasma display panel, wherein the scan electrode driver has a resistance and a constant voltage between a ground potential and a minimum potential. A series circuit composed of a plurality of sections is connected, and a voltage that determines the timing at which the drive voltage applied to the scan electrode changes from falling to rising is output from the connection point between the resistance of the series circuit and the constant voltage section. .

  By adopting such a configuration, it is possible to stably output the potential Vset2 for determining the end of the fall of the voltage applied to the scan electrode.

  In the invention according to claim 2, the constant voltage section is constituted by a shunt regulator.

  By adopting such a configuration, a sufficient current can be supplied to the shunt regulator, and the potential Vset2 can be stably output.

  According to the present invention, it is possible to provide a plasma display device that can stably output the potential Vset2 for determining the end of the drop of the voltage applied to the scan electrode with a simple and simple configuration.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing a structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention. The panel 100 is configured such that a glass front substrate 121 and a rear substrate 131 are arranged to face each other, and a large number of discharge cells 136 (see FIG. 2) are formed therebetween.

  On the front substrate 121, a plurality of scanning electrodes 122 and sustaining electrodes 123 constituting a display electrode pair are formed in parallel with each other. A dielectric layer 124 is formed so as to cover the scan electrode 122 and the sustain electrode 123, and a protective layer 125 is formed on the dielectric layer 124.

  The back substrate 131 is provided with a plurality of data electrodes 132 covered with an insulator layer 133, and a grid-like partition wall 134 is provided on the insulator layer 133. On the surface of the insulator layer 133 and the side surface of the partition wall 134, a phosphor layer 135 is provided in which phosphors emitting red, blue, and green are alternately applied.

  The front substrate 121 and the rear substrate 131 are arranged to face each other so that the scan electrode 122, the sustain electrode 123, and the data electrode 132 intersect, and discharge cells 136 are formed at respective positions where the electrodes intersect. For example, a mixed gas of neon and xenon is sealed in the discharge cell as a discharge gas.

  Note that the structure of the panel 100 is not necessarily limited to that described above. For example, a striped partition may be provided instead of the cross-shaped partition 134.

  FIG. 2 is an electrode array diagram of panel 100 used in the exemplary embodiment of the present invention. N scan electrodes 122 (SCN1 to SCNn) and n sustain electrodes 123 (SUS1 to SUSn) are arranged in the row direction, and m data electrodes 132 (D1 to Dm) are arranged in the column direction.

  Then, a discharge occurs at a portion where a pair of scan electrode 122 (SCNi) and sustain electrode 123 (SUSi) (i = 1 to n) and one data electrode 132 (Dj) (j = 1 to m) intersect. Cells 136 are formed, and m × n discharge cells 136 are formed in the discharge space.

  FIG. 3 is a circuit block diagram of the plasma display device in accordance with the exemplary embodiment of the present invention. The plasma display device includes a panel 100, an image signal processing unit 117, a data electrode driving unit 112, a scan electrode driving unit 113, a sustain electrode driving unit 114, a timing generation unit 115, and a power source that supplies power necessary for each circuit block. Part (not shown).

  This plasma display device has many other parts, but those that are not directly related to the essence of the present invention will be omitted from the illustration and description in order to avoid the complexity and clarification of the essence.

  The image signal processing unit 117 converts the image signal sig into image data indicating light emission / non-light emission for each subfield of each discharge cell.

  The data electrode driver 112 converts the image data for each subfield into a signal corresponding to each data electrode 132 (D1 to Dm), and drives each data electrode 132.

  Scan electrode driver 113 supplies a predetermined drive voltage waveform to each scan electrode 122 (SCN1 to SCNn). The sustain electrode driver 114 supplies a predetermined drive voltage waveform to each sustain electrode 123 (SUS1 to SUSn).

  The timing generator 115 generates various timing signals necessary for each electrode driver to control the drive voltage waveform based on the horizontal synchronizing signal H and the vertical synchronizing signal V, and supplies the timing signals to each electrode driver. .

  FIG. 4 shows a schematic circuit diagram of scan electrode driving unit 113 that generates a drive voltage waveform to be applied to scan electrode 122 of panel 100 used in the plasma display apparatus according to the embodiment of the present invention. The scan electrode driving unit 113 has many parts other than those shown in FIG. 4, but those not directly related to the essence of the present invention are shown in FIG. Description is omitted.

  Since the drive voltage waveform generated by the scan electrode driving unit 113 and applied to each electrode is the same as that of the conventional plasma display device, the description will be given with reference to FIG.

  In this plasma display device, a so-called subfield method is used as a method of displaying gradation according to an image. The subfield method is a method in which one field period is divided into a plurality of subfields having different display luminances, and gradation is displayed by a combination of these subfields.

  Each subfield has an initialization period, an address period, and a sustain period. FIG. 6 shows drive voltage waveforms for two subfields (first subfield and second subfield), but the drive waveforms in the other subfields are substantially the same.

  In the initializing period of the first subfield, 0 V is applied to the sustain electrodes 123 (SUS1 to SUSn). At the same time, a ramp voltage that gradually increases from the voltage Vsus toward the voltage (Vset + Vsus) is applied to the scan electrodes 122 (SCN1 to SCNn). Specifically, an up-ramp waveform is generated for the Vset voltage charged in the capacitor C419 using a Miller integrating circuit of the switch 416. At this time, since the MOS switch on the power supply Vsus side of the sustain pulse generation circuit 412 is turned on, the power supply Vsus is superimposed on C419.

  As a result, a ramp voltage that gradually increases from the voltage Vsus toward the voltage (Vset + Vsus) is applied to the scan electrodes 122 (SCN1 to SCNn).

  Next, the voltage Ve is applied to the sustain electrodes 123 (SUS1 to SUSn), and the ramp voltage gradually decreasing from the voltage Vi3 to the voltage Vi4 is scanned using the Miller integration circuit 426 of the scan electrode driver 113. Applied to the electrodes 122 (SCN1 to SCNn). As a result, a weak initializing discharge is generated in each discharge cell 136, and wall charges necessary for the subsequent address operation are formed on each electrode.

  As the operation in the initialization period, as shown in the initialization period of the second subfield in FIG. 6, the voltage Vi3 ′ gradually decreases from the voltage Vi3 ′ toward the voltage Vi4 with respect to the scan electrodes 122 (SCN1 to SCNn). Sometimes it is just applying the ramp voltage.

  In the next address period, the switches 427 and 428 of the scan pulse generation circuit 413 of the scan electrode driver 113 are turned on, and the potentials on both sides of the switching circuit 422 are guided to Va and Va + Vscn.

  Then, the scanning control circuit 423 controls so that the MOS switch on the potential (Vscn + Va) side of the switching circuit 422 is turned on and the MOS switch on the reference potential A side is turned off. As a result, a voltage (Vscn + Va) is applied to each scan electrode 122 (SCN1 to SCNn).

  Next, the MOS switch on the potential (Vscn + Va) side of the switching circuit 422 corresponding to the scan electrode 122 (SCN1) in the first row is controlled to be turned off, and the MOS switch on the reference potential A side is turned on. A negative scan pulse Va is applied to the scan electrode 122 (SCN1). At this time, a positive address pulse Vd is applied to the data electrode 132 corresponding to the discharge cell 136 to emit light by using the data electrode driver 112.

  As a result, address discharge occurs in the discharge cells 136 in the first row to which the scan pulse Va and the address pulse Vd are simultaneously applied, and wall charges are accumulated in the scan electrode 122 (SCN1) and the sustain electrode 123 (SUS1). A write operation is performed.

  Next, the MOS switch on the potential (Vscn + Va) side of the switching circuit 422 corresponding to the scan electrode 122 (SCN1) on the first row is turned on, the MOS switch on the reference potential A side is turned off, and the second row scan is performed. Control is performed so that the MOS switch on the potential (Vscn + Va) side of the switching circuit 422 corresponding to the electrode 122 (SCN2) is turned off and the MOS switch on the reference potential A side is turned on, so that the scanning electrode 122 (SCN2) in the second row is turned on. ) Is applied with a negative scanning pulse Va. At this time, a positive address pulse Vd is applied to the data electrode 132 corresponding to the discharge cell 136 to emit light.

  As a result, address discharge occurs in the discharge cells 136 in the second row to which the scan pulse Va and the address pulse Vd are simultaneously applied, and an address operation is performed. The above address operation is repeated until reaching the discharge cell 136 in the n-th row, and an address discharge is selectively generated in the discharge cells 136 to emit light to form wall charges.

  In the next sustain period, first, 0 V is applied to the sustain electrode 123.

  At the same time, the switches 415 and 417 are turned on to guide the output of the sustain pulse generation circuit 412 to the scan electrodes 122 (SCN1 to SCNn).

  Then, the MOS switch on the power supply Vsus side and the MOS switch on the GND side of the sustain pulse generation circuit 412 are alternately turned on and off as necessary. In this way, when a sustain pulse is applied to scan electrode 122 (SCN1 to SCNn), sustain discharge occurs in discharge cell 136 where address discharge has occurred, and light is emitted.

  In FIG. 5, it is determined that when the ramp voltage gradually decreasing from the voltage Vi3 to the voltage Vi4 is applied to the scan electrodes 122 (SCN1 to SCNn) in the initialization period described above, the voltage reaches Vset2. Then, a circuit diagram for creating the voltage Vset2 which is a reference voltage for increasing and inverting the voltage is shown.

  The purpose of this circuit is to stably and accurately generate and output a voltage having a potential of Vset2.

  For this purpose, a shunt regulator Q611, which is one specific example of the constant voltage unit, is used, and its anode terminal is connected to Va, which is a negative reference potential.

  The cathode terminal of the shunt regulator Q611 is connected to the GND level via the resistor 623.

  The negative reference potential Va and the cathode terminal of the shunt regulator Q611 are divided by resistors R621 and R622, and the midpoint is input to the reference terminal of the shunt regulator Q611.

  This makes it possible to stably generate and output Vset2, which is a potential between Va, which is a negative reference potential, and the GND level.

  The potential Vset2 thus generated is input to one input terminal of the comparator COMP631, and the potential of the scanning electrode 122 is input to the other input terminal of the comparator COMP631.

  Based on the output of the comparator COMP631, it is determined that the potential of the scanning electrode 122 has dropped to the potential Vset2, and the output is led to a circuit that inverts the switch 427. As a result, the potential of the scan electrode 122 can be increased to a potential of (Va + Vscn).

  In this way, it is determined that the voltage of the scan electrode 122 has reached Vset2, and the potential Vset2 serving as a reference for reversing and raising the voltage is generated stably and arbitrarily in a wide range. Is possible.

  According to the present invention, there is provided a plasma display device capable of generating and outputting a potential Vset2 for determining the end of a drop in the voltage applied to a scan electrode stably and arbitrarily in a wide range with a simple and simple configuration. And its industrial applicability is extremely high.

1 is an exploded perspective view showing a structure of a panel used in a plasma display device according to an embodiment of the present invention. FIG. 1 is an electrode array diagram of a panel used in a plasma display device according to an embodiment of the present invention. The circuit block diagram of the plasma display apparatus which is embodiment of this invention Schematic circuit diagram of a scan electrode driving unit of a plasma display device according to an embodiment of the present invention Circuit diagram of reference potential Vset2 generation circuit in plasma display apparatus according to an embodiment of the present invention The figure which shows the drive voltage waveform applied to each electrode of the panel in the conventional plasma display apparatus

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Panel 112 Data electrode drive part 113 Scan electrode drive part 114 Sustain electrode drive part 115 Timing generation part 117 Image signal processing part 121 Back glass substrate 122 Scan electrode 123 Sustain electrode 124 Dielectric layer 125 Protective layer 131 Back glass board 132 Data electrode 133 Insulator layer 134 Partition 135 Phosphor layer 136 Discharge cell 412 Sustain pulse generation circuit 413 Scan pulse generation circuit 415, 417, 427, 428 Switch 416, 426 Miller integration circuit 422 Switching circuit 423 Scan control circuit

Claims (2)

  1. A scan electrode driver that applies a drive voltage to the scan electrodes of the plasma display panel, wherein a series circuit including a resistor and a constant voltage unit is connected between the ground potential and the lowest potential in the scan electrode driver; A plasma display device configured to output a voltage for determining a timing at which a drive voltage applied to a scan electrode changes from a drop to an increase from a connection point between a resistance of a series circuit and a constant voltage unit.
  2. The plasma display apparatus according to claim 1, wherein the constant voltage unit is configured by a shunt regulator.
JP2006036342A 2006-02-14 2006-02-14 Plasma display device Pending JP2007218972A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09311655A (en) * 1996-05-21 1997-12-02 Paloma Ind Ltd Electric power source circuit for fluorescent display tube
JP2002032055A (en) * 2000-07-14 2002-01-31 Matsushita Electric Ind Co Ltd Driving device and driving method for ac type plasma display panel
JP2003015602A (en) * 2001-06-29 2003-01-17 Fujitsu Ltd Method for driving ac type pdp and device therefor
JP2006018148A (en) * 2004-07-05 2006-01-19 Funai Electric Co Ltd Liquid crystal driving apparatus

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09311655A (en) * 1996-05-21 1997-12-02 Paloma Ind Ltd Electric power source circuit for fluorescent display tube
JP2002032055A (en) * 2000-07-14 2002-01-31 Matsushita Electric Ind Co Ltd Driving device and driving method for ac type plasma display panel
JP2003015602A (en) * 2001-06-29 2003-01-17 Fujitsu Ltd Method for driving ac type pdp and device therefor
JP2006018148A (en) * 2004-07-05 2006-01-19 Funai Electric Co Ltd Liquid crystal driving apparatus

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