JP2007194476A - Method for manufacturing multilayer wiring board - Google Patents

Method for manufacturing multilayer wiring board Download PDF

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Publication number
JP2007194476A
JP2007194476A JP2006012580A JP2006012580A JP2007194476A JP 2007194476 A JP2007194476 A JP 2007194476A JP 2006012580 A JP2006012580 A JP 2006012580A JP 2006012580 A JP2006012580 A JP 2006012580A JP 2007194476 A JP2007194476 A JP 2007194476A
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Japan
Prior art keywords
layer
wiring pattern
metal
formed
wiring
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Pending
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JP2006012580A
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Japanese (ja)
Inventor
Makoto Yanagisawa
信 柳沢
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Shinko Electric Ind Co Ltd
新光電気工業株式会社
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Priority to JP2006012580A priority Critical patent/JP2007194476A/en
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Application status is Pending legal-status Critical

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Abstract

A method for manufacturing a multilayer wiring board capable of reducing the thickness of the multilayer wiring board and reducing the manufacturing cost is provided.
A wiring groove is formed in the insulating layer covering the first wiring pattern on the substrate side along the second wiring pattern to be formed, and then the surface of the insulating layer including the inner wall surface of the groove is formed. A metal thin film layer 20 is formed on the second wiring pattern 22 formed by filling the wiring groove 18 with a plating metal by electrolytic plating using the metal thin film layer 20 as a power feeding layer and on a flat surface of the metal thin film 20. After the plating metal layer is formed, the resist layer 26 formed on the plating metal layer is patterned, and then exposed by electrolytic plating using the metal thin film layer 20 and the metal layer 24 composed of the plating metal layer as a power feeding layer. After the plated metal layer is filled with the plated metal to form the third wiring pattern 28, the portion of the metal layer 24 between the second wiring pattern 22 and the third wiring pattern 28 is removed. Characterized in that it.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a multilayer wiring board, and more particularly to a method for manufacturing a multilayer wiring board in which a plurality of wiring patterns are laminated in multiple layers via an insulating layer on at least one side of a support plate.

As a multilayer wiring board on which a semiconductor element is mounted, for example, a multilayer wiring board shown in FIG. 5 is used. In the multilayer wiring board on which the semiconductor element 136 shown in FIG. 5 is mounted, wiring patterns 146, 146... Are laminated on both sides of the core substrate 130 via a resin layer 140 as an insulating layer. Solder balls 134, 134,... As connection terminals connected to the electrode terminals of the mounted semiconductor element 136 are mounted on the pads of the wiring pattern 146 formed on the one surface side of the multilayer wiring board. Solder balls 132, 132,... As external connection terminals are attached to pads formed on the other side of the wiring board.
Further, solder resists 138 and 138 are applied to both surfaces of the multilayer wiring board except for the portions of the solder balls attached to the pads.

As a method for manufacturing the multilayer wiring board shown in FIG. 5, the following Patent Document 1 proposes a method for manufacturing a multilayer wiring board using press working.
In this method of manufacturing a multilayer wiring board using press working, as shown in FIG. 4, a via recess is formed on the resin layer 140 as an insulating layer formed on both sides of the core board 130 by pressing using a molding die. After forming the wiring pattern groove, the via recess and the wiring pattern groove are filled with plating metal by plating, and a metal layer having a predetermined thickness is formed on the flat surface of the resin layer 140. The layer is polished to expose the surface of the via formed in the via recess and the wiring pattern groove 146 formed in the wiring pattern groove on the same surface as the surface of the resin layer. Thereafter, the resin layer 140 is formed, pressed, and plated. , And repeating the polishing to obtain a multilayer wiring board.
JP 2002-171048 A

According to the method for manufacturing a multilayer wiring board proposed in Patent Document 1, a CO 2 laser, an excimer laser, or the like is known as compared with an additive method or a semi-additive method known as a conventional multilayer wiring substrate manufacturing method. Since no laser equipment is required and the manufacturing process can be omitted, the manufacturing cost of the finally obtained multilayer wiring board can be reduced.
However, with respect to multilayer wiring boards, there is a demand for further thinner layers and lower manufacturing costs, and it is necessary to meet such demands.
Accordingly, an object of the present invention is to provide a method for manufacturing a multilayer wiring board capable of further reducing the thickness of the multilayer wiring board and reducing the manufacturing cost.

In order to solve the above problems, the present inventor can manufacture a conventional multilayer wiring board in which a single wiring pattern is formed in a single resin layer if a two-layer wiring pattern can be formed in a single resin layer as an insulating layer. As a result of considering that the manufacturing process can be omitted and the resulting multilayer wiring board can be thinned as compared with the method, the present invention has been achieved.
That is, the present invention provides an insulating layer that covers the first wiring pattern on the support plate side when manufacturing a multilayer wiring substrate in which a plurality of wiring patterns are laminated in multiple layers via an insulating layer on at least one surface side of the support plate. After forming a wiring groove following the second wiring pattern to be formed, a metal thin film layer covering the surface of the insulating layer including the inner wall surface of the wiring groove is formed, and then the metal thin film layer is used as a power feeding layer After electrolytic plating, the second wiring pattern formed by filling the wiring groove with plating metal and the third wiring pattern formed of the plating metal on the flat surface of the insulating layer are sequentially or simultaneously formed, In the method of manufacturing a multilayer wiring board, the surface of the insulating layer between the second wiring pattern and the third wiring pattern is exposed.

In the present invention, after the plating metal layer is formed on the second wiring pattern formed by filling the plating groove with the plating metal by electrolytic plating using the metal thin film layer as the power feeding layer and on the flat surface of the metal thin film. The resist layer formed on the plated metal layer is patterned so that the surface of the plated metal layer is exposed following the third wiring pattern to be formed, and then a metal layer composed of the metal thin film layer and the plated metal layer is formed. After the plating metal is filled on the exposed plating metal layer to form a third wiring pattern by electrolytic plating as a power feeding layer, between the second wiring pattern and the third wiring pattern among the metal layers. By removing the portion, two wiring patterns can be reliably formed in one insulating layer, and the manufacturing process can be omitted.
Further, the resist layer formed on the metal thin film layer is patterned so that the surface of the metal thin film layer is exposed following the wiring groove and the third wiring pattern to be formed, and then the metal thin film layer is used as a power feeding layer. By electrolytic plating, the wiring groove is filled with plating metal to form a second wiring pattern, while the exposed metal thin film layer is filled with plating metal to form a third wiring pattern, and then the second wiring pattern is formed. By removing the metal thin film layer between the wiring pattern and the third wiring pattern, the manufacturing process of the multilayer wiring board can be further omitted.
Furthermore, the wiring groove can be easily formed by forming the wiring groove by press working using a mold.
In addition, a board | substrate can be used suitably as a support plate.

According to the present invention, a two-layer wiring pattern can be formed in one insulating layer, and the manufacturing process is omitted as compared with a conventional method for manufacturing a multilayer wiring board in which one wiring pattern is formed in one resin layer. The resulting multilayer wiring board can be thinned.
Furthermore, in the present invention, a two-layer wiring pattern can be formed by using a metal thin film layer formed on the surface of one insulating layer, so that further manufacturing steps can be omitted.

(First embodiment)
An example of a method for manufacturing a multilayer wiring board according to the present invention is shown in FIG. In the manufacturing method shown in FIG. 1, first, as shown in FIG. 1A, a resin layer 14 as an insulating layer covering the first wiring patterns 12, 12... Formed on one surface side of the substrate 10 as a support plate. Form. The resin layer 14 is preferably formed of a thermosetting resin such as an epoxy resin or a polyimide resin, and is in a cured state at room temperature but is not completely cured (B stage state). The first wiring patterns 12, 12,... Can be formed by a known wiring pattern forming method, for example, a subtractive method.
As shown in FIG. 1A, wiring grooves 18, 18... Are formed in the resin layer 14 by press working using a molding die 16. In this pressing process, heating the resin layer 14 to a softened state can easily form the wiring grooves 18, 18... By the mold 16 and release the mold 16. preferable. The resin layer 14 in which the wiring grooves 18, 18,... Are formed is further heated as necessary to complete the curing of the thermosetting resin that forms the resin layer 14.

As shown in FIG. 1B, a metal thin film layer 20 is formed on the entire surface of the resin layer 14 including the inner wall surfaces of the formed wiring grooves 18, 18,. The metal thin film layer 20 can be formed by electroless plating or vapor deposition. The metal thin film layer 20 is preferably formed of the same metal as that of the wiring pattern to be formed, but is usually formed of copper.
Next, as shown in FIG. 1C, the wiring grooves 18, 18,... Are filled with plating metal by electrolytic plating using the metal thin film layer 20 as a power feeding layer, and the second wiring patterns 22, 22,. While forming, a plated metal layer is formed on the second wiring pattern 22 and on the flat surface of the metal thin film layer 20. Copper can be suitably used as the plating metal.
In FIG. 1C, a metal layer composed of the metal thin film layer 20 and the plated metal layer is shown as a metal layer 24.

Next, the resist layer 26 formed so as to cover the surface of the metal layer 24 is patterned so that the surface of the metal layer 24 is exposed following the third wiring pattern to be formed. By electroplating using the metal layer 24 as a power feeding layer, as shown in FIG. 1D, the portion where the surface of the metal layer 24 is exposed is filled with a plating metal to form a third wiring pattern 28.
Further, as shown in FIG. 1E, when the resist layer 26 is removed, the third wiring pattern 28 is exposed. The third wiring pattern 28 is electrically connected by the metal layer 24 formed between the second wiring pattern 22. Therefore, by removing the metal layer 24 between the second wiring pattern 22 and the third wiring pattern 28 by etching, the second wiring pattern 22 and the third wiring pattern 28 as shown in FIG. Can be formed in an insulated state.
Here, the via for electrically connecting the first wiring pattern 12 and the second wiring pattern 22 is formed with a laser or the like at a predetermined position of the wiring groove 18 after forming the wiring groove 18 shown in FIG. Can be formed by forming a recess in which the first wiring pattern 12 is exposed, and then performing the steps shown in FIGS. 1B to 1F.
In addition, the via for electrically connecting the first wiring pattern 12 and the third wiring pattern 28 is also formed with the wiring groove 18 of the resin layer 14 after the wiring groove 18 shown in FIG. 1A is formed. A concave portion where the first wiring pattern 12 is exposed by a laser or the like is formed in a predetermined portion of the flat surface that is not formed, and then the steps shown in FIGS. 1B to 1F are performed.

Incidentally, in order to remove the metal layer 24 formed between the third wiring pattern 28 and the second wiring pattern 22 shown in FIG. 1E by etching, a third wiring pattern in which a part is etched by this etching. Compared to 28, the metal layer 24 needs to be sufficiently thin.
Therefore, as shown in FIG. 2A, when the metal layer 24 is formed thick with respect to the third wiring pattern 28 to be formed, the metal layer 24 is polished as shown in FIG. It is preferable to make it sufficiently thin. As this polishing, chemical polishing or mechanical polishing can be used.

(Second Embodiment)
In the manufacturing method shown in FIG. 1, after the metal layer 24 is formed by electrolytic plating, a resist layer 26 covering the metal layer 24 is formed, and the resist layer 26 is patterned.
After the resist layer 26 is directly formed on the metal thin film layer 20 formed on the entire surface of the resin layer 14 including the inner wall surfaces of the wiring grooves 18, 18..., As shown in FIG. Patterning for exposing the surface of the metal thin film layer 20 is performed following the grooves 18, 18... And the third wiring pattern to be formed. The resist layer 26 is preferably formed by directly laminating a resist film on the metal thin film layer 20.
Next, as shown in FIG. 3B, the wiring grooves 18, 18,... Are filled with plating metal by electrolytic plating using the metal thin film layer 20 as a power feeding layer, and the second wiring patterns 22, 22,. While being formed, the exposed metal thin film layer 20 is filled with a plating metal to form third wiring patterns 28, 28,.
Further, as shown in FIG. 3C, when the resist layer 26 is removed, the third wiring pattern 28 is exposed. The third wiring pattern 28 is electrically connected by the metal thin film layer 20 formed between the second wiring pattern 22. Therefore, by removing the metal thin film layer 20 between the second wiring pattern 22 and the third wiring pattern 28 by etching, the second wiring pattern 22 and the third wiring pattern as shown in FIG. 28 can be formed in an insulated state.
According to the manufacturing method shown in FIG. 3, the manufacturing process of the multilayer wiring board can be further omitted as compared with the manufacturing method shown in FIGS.

In the manufacturing method of the multilayer wiring board shown in FIGS. 1 to 3, a plurality of wiring patterns are laminated on one surface side of the substrate 10 as a support plate via the resin layer 14. Even in the case of manufacturing the multilayer wiring board shown in FIG. 5 by using the core board formed on both sides and laminating the wiring pattern on both sides of the core board via the resin layer, A manufacturing method can be applied.
Further, a metal plate such as a copper plate may be used as the support plate, and a plurality of wiring patterns may be laminated via the resin layer 14, and then the metal plate may be removed by etching or the like.
In the manufacturing method shown in FIGS. 1 to 3, the wiring grooves 18, 18... Are formed in the resin layer 14 by the molding die 16, but the first wiring patterns 12, .. Can be formed by injection molding using a molding die in which portions corresponding to the wiring grooves 18, 18... To be formed are formed in a convex shape.

In contrast to the manufacturing method of the multilayer wiring board shown in FIGS. 1 to 3, the manufacturing method of the multilayer wiring board shown in FIG. 4 described in Patent Document 1 described above is a core board in which wiring patterns and vias are formed. In this manufacturing method, wiring patterns are formed on both sides of 130. However, FIG. 4 shows a procedure for forming a wiring pattern formed on one surface side of the core substrate 130, and a procedure for forming a wiring pattern formed on the other surface side of the core substrate 130 at the same time is omitted because it has the same contents. did.
In the manufacturing method of the multilayer wiring board shown in FIG. 4, first, as shown in FIG. 4A, after forming the resin layer 140 on each of both surfaces of the core substrate 130, as shown in FIG. The via recesses 142, 142... And the wiring pattern grooves 161, 161... Are formed by pressing with a pair of molds 150, 150 (only one of the molds 150, 150 is shown in FIG. 4). .

Next, as shown in FIG. 4C, a thin metal thin film layer 152 formed by electroless plating or the like is formed on the entire surface of the resin layer 140 including the inner wall surfaces of the via recess 142 and the wiring pattern groove 161. .
Furthermore, electrolytic plating using the metal thin film layer 152 as a power feeding layer is performed, and as shown in FIG. 4D, the via recess 142 and the wiring pattern groove 161 are filled with plating metal, and the metal layer 154 having a predetermined thickness is formed. Form. The metal layer 154 is also formed on the surface of the resin layer 140 where the via recess 142 and the wiring pattern groove 161 are not formed. The metal layer 154 electrically short-circuits the via and the wiring pattern formed by filling the via recess 142 and the wiring pattern groove 161 with the plating metal.
Therefore, the metal layer 152 deposited on the surface of the resin layer 140 excluding the inner wall surfaces of the wiring pattern grooves 161, 161... And the via recesses 142, 142... Is polished as shown in FIG. In addition, the surfaces of the vias 156, 156,... And the wiring patterns 146, 146,.
Thereafter, the resin layer 140 is formed again on the resin layer 140 on which the wiring pattern 146 and the via 156 are formed, and a multilayer wiring board can be formed by repeating the steps of FIGS.
As described above, in the method for manufacturing a multilayer wiring board described in Patent Document 1 shown in FIG. 4, one wiring pattern 146 is formed on one resin layer 140, so that the present invention shown in FIGS. Compared to the method of manufacturing a multilayer wiring board, the number of steps is increased. Moreover, the thickness of the obtained multilayer wiring board is also thicker than that of the multilayer wiring board obtained by the method for manufacturing a multilayer wiring board according to the present invention shown in FIGS.

It is process drawing explaining an example of the manufacturing method of the multilayer wiring board which concerns on this invention. It is a partial process figure explaining other examples about the manufacturing method of the multilayer wiring board concerning the present invention. It is a partial process figure explaining other examples about the manufacturing method of the multilayer wiring board concerning the present invention. It is process drawing explaining the manufacturing method of the conventional multilayer wiring board. It is a longitudinal cross-sectional view for demonstrating an example of a multilayer wiring board.

Explanation of symbols

10 Substrate 12 First Wiring Pattern 14 Resin Layer 16 Mold 18 Wiring Groove 20 Metal Thin Film Layer 22 Second Wiring Pattern 24 Metal Layer 26 Resist Layer 28 Third Wiring Pattern 50 Mold

Claims (5)

  1. When manufacturing a multilayer wiring board in which a plurality of wiring patterns are laminated in multiple layers via an insulating layer on at least one side of the support plate,
    A metal thin film layer covering a surface of the insulating layer including an inner wall surface of the wiring groove after forming a wiring groove following the second wiring pattern to be formed in the insulating layer covering the first wiring pattern on the support plate side Form the
    Next, by electrolytic plating using the metal thin film layer as a power feeding layer, a second wiring pattern in which the wiring groove is filled with a plating metal, and a third wiring pattern made of a plating metal on the flat surface of the insulating layer, Are formed sequentially or simultaneously,
    A method of manufacturing a multilayer wiring board, comprising exposing a surface of an insulating layer between the second wiring pattern and the third wiring pattern.
  2. After forming the plated metal layer on the second wiring pattern formed by filling the groove for wiring with the plating metal by electrolytic plating using the metal thin film layer as the power feeding layer and on the flat surface of the metal thin film,
    The resist layer formed on the plated metal layer is subjected to patterning that exposes the surface of the plated metal layer following the third wiring pattern to be formed,
    Next, after electrolytic plating using the metal layer composed of the metal thin film layer and the plating metal layer as a power feeding layer, the exposed plating metal layer is filled with plating metal to form a third wiring pattern,
    The method for manufacturing a multilayer wiring board according to claim 1, wherein a portion of the metal layer between the second wiring pattern and the third wiring pattern is removed.
  3. After patterning the resist layer formed on the metal thin film layer to expose the surface of the metal thin film layer following the wiring groove and the third wiring pattern to be formed,
    By electrolytic plating using the metal thin film layer as a power feeding layer, the plating groove is filled with a plating metal to form a second wiring pattern, and the exposed metal thin film layer is filled with a plating metal to form a third wiring pattern. Form the
    2. The method for manufacturing a multilayer wiring board according to claim 1, wherein the metal thin film layer between the second wiring pattern and the third wiring pattern is removed.
  4.   The manufacturing method of the multilayer wiring board as described in any one of Claims 1-3 which forms the groove | channel for wiring by the press work using a shaping | molding die.
  5. The method for manufacturing a multilayer wiring board according to claim 1, wherein the support plate is a substrate.
JP2006012580A 2006-01-20 2006-01-20 Method for manufacturing multilayer wiring board Pending JP2007194476A (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049364A (en) * 2007-08-21 2009-03-05 Samsung Electro Mech Co Ltd Method for manufacturing wiring board
JP2009158905A (en) * 2007-12-27 2009-07-16 Korea Circuit Co Ltd Method of manufacturing embedded printed-circuit board
EP2083296A3 (en) * 2008-01-24 2009-09-09 Nitto Denko Corporation Manufacturing method of opto-electric hybrid board and opto-electric hybrid board obtained thereby
JP2010010500A (en) * 2008-06-30 2010-01-14 Hitachi Ltd Copper circuit component and its production method
US9269610B2 (en) 2014-04-15 2016-02-23 Qualcomm Incorporated Pattern between pattern for low profile substrate

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002171048A (en) * 2000-12-01 2002-06-14 Shinko Electric Ind Co Ltd Method for manufacturing wiring board
JP2002374066A (en) * 2001-06-14 2002-12-26 Ibiden Co Ltd Method for manufacturing multilayered printed circuit substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002171048A (en) * 2000-12-01 2002-06-14 Shinko Electric Ind Co Ltd Method for manufacturing wiring board
JP2002374066A (en) * 2001-06-14 2002-12-26 Ibiden Co Ltd Method for manufacturing multilayered printed circuit substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049364A (en) * 2007-08-21 2009-03-05 Samsung Electro Mech Co Ltd Method for manufacturing wiring board
JP4681023B2 (en) * 2007-08-21 2011-05-11 サムソン エレクトロ−メカニックス カンパニーリミテッド. Wiring board manufacturing method
JP2009158905A (en) * 2007-12-27 2009-07-16 Korea Circuit Co Ltd Method of manufacturing embedded printed-circuit board
JP4703680B2 (en) * 2007-12-27 2011-06-15 コリア サーキット カンパニー リミテッド Method for manufacturing embedded printed circuit board
EP2083296A3 (en) * 2008-01-24 2009-09-09 Nitto Denko Corporation Manufacturing method of opto-electric hybrid board and opto-electric hybrid board obtained thereby
US7747123B2 (en) 2008-01-24 2010-06-29 Nitto Denko Corporation Manufacturing method of opto-electric hybrid board and opto-electric hybrid board obtained thereby
JP2010010500A (en) * 2008-06-30 2010-01-14 Hitachi Ltd Copper circuit component and its production method
US9269610B2 (en) 2014-04-15 2016-02-23 Qualcomm Incorporated Pattern between pattern for low profile substrate

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