JP2007194247A - Semiconductor light emitting device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fabrication process of a semiconductor light emitting device in which two substrates can be laminated with a predetermined pressure while preventing the substrate from breaking along the crystal direction and a semiconductor layer can be transferred to a substrate other than a growth substrate. <P>SOLUTION: After a contact layer 16D, a second clad layer 15D, an active layer 14D and a first type clad layer 13D are grown epitaxially on a growth substrate 100D, a first metal layer 11D is deposited to form a first wafer W1. On the other hand, a second wafer W2 is formed by depositing a second metal layer 12D on a support substrate 10D. Under a state where the first metal layer 11D and the second metal layer 12D are opposed each other such that the crystals composing the first wafer W1 and the second wafer W2 have crystal directions different from each other, the first wafer W1 and the second wafer W2 are stuck with pressure F and then the growth substrate 100D is removed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor light emitting device manufactured through a transfer process to a substrate different from a growth substrate, and a method for manufacturing the same.

  The external quantum efficiency of a semiconductor light emitting device such as a light emitting diode (LED) or a semiconductor laser (LD: Laser Diode) is composed of two elements, an internal quantum efficiency and a light extraction efficiency, and improves these efficiency. Accordingly, it is possible to realize a semiconductor light emitting device with a long life, low power consumption, and high output. Here, the former internal quantum efficiency is, for example, a layer structure capable of strictly controlling the growth conditions so as to obtain a high-quality crystal with few crystal defects and dislocations, and suppressing the occurrence of carrier overflow. It is improved by doing.

  On the other hand, with regard to the latter light extraction efficiency, for example, when the growth substrate is formed of a material having a light absorption function, and this growth substrate exists on the exit window side, the compound semiconductor layer such as the active layer is removed from the growth substrate. It can be improved by transferring to a new substrate (support substrate). That is, a compound semiconductor layer such as an active layer is formed on a growth substrate, a support substrate is bonded onto the compound semiconductor layer with a predetermined pressure to ensure rigidity, and then the growth substrate is removed by etching. . For example, in an AlGaInP-based red light emitting diode manufactured by growing an AlGaInP-based compound semiconductor layer on a GaAs substrate (growth substrate), the GaAs substrate easily absorbs a red wavelength component. After attaching a GaP substrate (supporting substrate) that hardly absorbs the red wavelength component, the GaAs substrate is removed. Thereby, the light emission intensity can be improved.

  Here, the substrate bonding operation is generally performed at a high pressure in order to obtain a sufficient bonding strength. However, when a compound semiconductor layer such as a substrate or an active layer is composed of a crystal having a zinc blende type structure such as GaAs (gallium arsenide), it is cracked along the crystal direction when exposed to high pressure. Easy to cleave (easy to cleave). For example, when the (100) plane is parallel to the surface (crystal plane) of the substrate, when pressure is applied from a direction perpendicular to the crystal plane, the substrate is crystallized in the direction [011] or [01-1]. It is easy to break along. In order to prevent the substrate from cracking, it is preferable to reduce the pressure as much as possible. Therefore, in Patent Document 1, a technique is proposed in which a metal layer (reflective layer) mainly composed of Au (gold) is provided in advance on each bonding surface. As a result, the substrates can be bonded to each other without causing the wafer to crack.

JP 2004-235581 A

  However, with the technique described in Patent Document 1 described above, it is possible to bond the substrates together, but since the pressure is reduced during bonding, the adhesion of the bonded surfaces is low, and the substrate peels off. There is a problem that it is easy to do. There is also a problem that voids are likely to occur on the bonding surface. As described above, in the conventional technology, if the pressure at the time of bonding is increased, the substrate is easily cracked. Conversely, if the pressure is decreased, the substrate is easily peeled off or voids are easily generated on the bonding surface. There was a problem of becoming.

  The present invention has been made in view of such problems, and its purpose is to prevent the generation of cracks and voids, and to bond a plurality of substrates with sufficient pressure, and to provide a compound semiconductor layer such as an active layer. It is an object of the present invention to provide a method for manufacturing a semiconductor light emitting device that can be transferred to a support substrate different from a growth substrate with a high yield, and a semiconductor light emitting device manufactured by the method.

  The method for manufacturing a semiconductor light emitting device of the present invention includes a step of forming a compound semiconductor layer by crystal growth on a first semiconductor substrate having a first crystal direction in the plane, and a second having a second crystal direction in the plane. Bonding the semiconductor substrate to the compound semiconductor layer side of the first semiconductor substrate at a predetermined pressure and with the second crystal direction being twisted with respect to the first crystal direction; And a step of removing the first semiconductor substrate from the compound semiconductor layer after bonding the second semiconductor substrate.

  Here, the “crystal direction” refers to a direction that is easy to cleave in the plane when pressure is applied from the direction perpendicular to the plane of each substrate, for example, zinc blende type such as GaAs. In the structure, when the (100) plane is parallel to the surface (crystal plane) of the substrate, it is easy to crack along the [011] or [01-1] direction when pressure is applied from the vertical direction. These two directions shall be pointed out.

  In the method for manufacturing a semiconductor light emitting device according to the present invention, even if sufficient pressure is applied in the bonding step, the crystal direction is between the second semiconductor substrate and the first semiconductor substrate and the compound semiconductor layer grown based on the first semiconductor substrate. Since they are displaced from each other, the bonding is performed without cracking any of the substrates.

  The semiconductor light emitting device of the present invention is obtained by the above-described manufacturing method, and has a compound semiconductor layer having a first crystal direction in the plane, a compound semiconductor layer supporting the compound semiconductor layer, and a second crystal direction in the plane. And a support substrate in which the second crystal direction is in a twisted relationship with the first crystal direction. Here, the supporting substrate corresponds to the second semiconductor substrate, and the growth substrate (first semiconductor substrate) for growing the compound semiconductor layer is removed after bonding.

  According to the method for manufacturing a semiconductor light emitting device of the present invention, in the bonding step, the crystal direction is twisted between the second semiconductor substrate and the first semiconductor substrate and the compound semiconductor layer grown based on the first semiconductor substrate. Therefore, there is no possibility that any substrate will break. Therefore, it is possible to apply a pressure with which a sufficient bonding strength can be obtained, and it is possible to realize a semiconductor light emitting device with a very good yield.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a cross-sectional structure of a light-emitting diode 1 (LED) according to a first embodiment of the present invention. In the light emitting diode 1, a first metal layer 11, a second metal layer 12, a first cladding layer 13, an active layer 14, a second cladding layer 15, and a contact layer 16 are stacked in this order on one surface side of a support substrate 10. It has a laminated structure. On the surface of the contact layer 16, a ring-shaped p-side electrode 17 having an opening 17A at the center is formed. An n-side electrode 18 is formed on the back surface of the support substrate 10. The light emitting diode 1 is a top emission type light emitting element in which the first metal layer 11 and the second metal layer 12 on the support substrate 10 side function as a reflective layer, and light emitted from the light emitting region 14A of the active layer 14 is emitted. It is injected from the opening 17A.

  The support substrate 10 is made of a mixed crystal having a zinc blende structure, for example, n-type GaAs or n-type GaP.

  The first metal layer 11 and the second metal layer 12 as the reflection layer are made of a metal having a high reflectivity such as gold (Au) or chromium (Cr).

  The first cladding layer 13, the active layer 14, the second cladding layer 15, and the contact layer 16 are compound semiconductor layers, which are each composed of a mixed crystal having a zinc blende structure, for example, an AlGaInP-based semiconductor. The AlGaInP-based semiconductor refers to a compound semiconductor containing 3B group element aluminum (Al), gallium (Ga) or indium (In) and 5B group element phosphorus (P) in the long-period periodic table.

The active layer 14 has a multiple quantum well structure in which, for example, quantum well layers (not shown) and barrier layers (not shown) are alternately stacked. For example, the undoped In _a Ga _1-a P (0 ≦ as a ≦ 1) consisting of a quantum well layer and an undoped _{(Al b Ga 1-b)} 1-c In c P (0 ≦ b ≦ 1,0 ≦ c ≦ 1) set and a barrier layer made of, it It is composed of multiple layers. Here, the In composition values a and c and the Al composition value b of the active layer 14 are determined in consideration of the emission wavelength, carrier density distribution, and the like. The active layer 14 may have a structure other than the multiple quantum well structure, for example, a single quantum well structure or a bulk structure.

The first cladding layer 13 is, for example, n-type (Al _d Ga _1-d ) _1-e In _e P (0 ≦ d ≦ 1, 0 ≦ e ≦ 1), and the second cladding layer 15 is, for example, p-type (Al _f Ga _1-f ) _1-g In _g P (0 ≦ f ≦ 1, 0 ≦ g ≦ 1). The first cladding layer 13 and the second cladding layer 15 have a larger band gap than the active layer 14. Here, the Al composition and the In composition of the first cladding layer 13 and the second cladding layer 15 are determined in consideration of the carrier confinement property and injection property with respect to the active layer 14. The contact layer 16 is made of, for example, p-type GaP.

  The p-side electrode 17 has a structure in which, for example, a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are stacked in this order on the surface of the contact layer 16, and is electrically connected to the contact layer 16. ing. The n-side electrode 18 has a structure in which, for example, an alloy layer of gold (Au) and germanium (Ge), a nickel (Ni) layer, and a gold (Au) layer are stacked in this order. Electrically connected.

  In the present embodiment, the support substrate 10, the first cladding layer 13, the active layer 14, the second cladding layer 15 and the contact layer 16 are composed of a mixed crystal having a zinc blende structure as described above. As shown in FIG. 4, the support substrate 10 and the compound semiconductor layer such as the active layer 14 have crystal faces S1 and S2 facing each other parallel to the lattice plane (100). On the other hand, the crystal directions [011] of the support substrate 10 and the compound semiconductor layer are different from each other, and are twisted at an angle θ. The same applies to the [01-1] direction.

  That is, the compound semiconductor layer is a crystal grown on another substrate (a growth substrate 100D described later) different from the support substrate 10, and the light-emitting diode 1 of the present embodiment has this compound semiconductor layer formed. It can be seen that the growth substrate 100D is removed after the support substrate 10 is bonded to the growth substrate 100D with the crystal directions shifted from each other. Here, the torsion angle θ excludes angles 0, 90, 180, and 270 degrees where [011] and [01-1] overlap, and is preferably in the range of 5 degrees to 85 degrees. An angle, more preferably 45 degrees.

  As described above, in the present embodiment, the support substrate 10 and the compound semiconductor layer are bonded so that the crystal directions [011] and [01-1] are intentionally different from each other. The directions in which the support substrate 10 and the compound semiconductor layer are easily cleaved are different from each other.

  In the light emitting diode 1 of the present embodiment, when a current is supplied to the p-side electrode 17 and the n-side electrode 18, the current is injected into the light emitting region 14A of the active layer 14, thereby causing recombination of electrons and holes. Light emission (here, red light emission) occurs. Of the emitted light generated in the light emitting region 14A, the light that goes directly to the opening 17A that is an emission window passes through the p-side contact layer 16 and is emitted to the outside, and the light that goes to the substrate 10 side is emitted from the first metal layer 11 and After being reflected to the p-side contact layer 16 side by the reflective layer made of the second metal layer 12, it is emitted from the opening 17A.

  At this time, as will be described later in the manufacturing process, the growth substrate (GaAs substrate) having a light absorption function is removed in advance in the manufacturing process, so that light is not absorbed on the opening 17A side, Further, since the reflective layer (the first metal layer 11 and the second metal layer 12) is formed between the support substrate 10 and the first cladding layer 13, light is not absorbed on the support substrate 10 side. . This improves the light extraction efficiency.

  Next, a method for manufacturing the light-emitting diode 1 will be described with reference to FIGS.

  In the following description, D (for example, “D” at the end of the active layer 14D) at the end of the reference sign indicates the state of the wafer before cleaving and forming into a chip shape. The ones with D at the end of the code have the same composition as those without D at the end of the code. Moreover, the dotted line perpendicular | vertical to the lamination direction shown in FIG.3 and FIG.5 represents the location which will be cleaved when shape | molding in chip shape. The same applies to FIGS. 8, 10, 11 and 13.

In order to manufacture the light emitting diode 1, an AlGaInP-based semiconductor layer is formed on a growth substrate 100D made of, for example, GaAs, for example, by MOCVD (Metal Organic Chemical Vapor Deposition). At this time, for example, trimethylaluminum (TMA), trimethylgallium (TMG), trimethylindium (TMIn), and phosphine (PH ₃ ) are used as raw materials for the AlGaInP-based semiconductor, and for example, hydrogen selenide is used as the raw material for donor impurities. (H ₂ Se) is used, and dimethyl zinc (DMZn), for example, is used as the acceptor impurity raw material.

  Specifically, first, as shown in FIG. 3A, after the contact layer 16D, the second cladding layer 15D, the active layer 14D, and the first cladding layer 13D are stacked in this order on the surface of the growth substrate 100D. Further, a second metal layer 12D is formed on the first cladding layer 13D. Hereinafter, this is referred to as a first wafer W1. On the other hand, the first metal layer 11D is formed on the surface of the support substrate 10D made of, for example, GaP. Hereinafter, this is referred to as a second wafer W2.

  Next, as shown in FIG. 3B, the first wafer W1 and the second wafer W2 are set to a predetermined temperature (for example, 300) with the first metal layer 11D and the second metal layer 12D facing each other. And a predetermined pressure F (e.g., 2000 N to 8000 N when the wafer size is 3 inches) is applied for bonding. At this time, as shown in FIG. 4, the first wafer W1 and the second wafer W2 are bonded so that the crystal directions [011] and [01-1] are twisted at an angle θ.

  As a result, the directions in which the first wafer W1 and the second wafer W2 are easily cleaved are different from each other, and therefore the pressure F is sufficient to obtain a sufficient bonding strength for the first wafer W1 and the second wafer W2. Even if is added, there is no possibility that the first wafer W1 and the second wafer W2 are cracked along the crystal direction. As a result, the yield is improved as compared with the case where these crystal directions [011] and [01-1] are bonded so that the first wafer W1 and the second wafer W2 overlap each other.

  In FIG. 4, the orientation flats (hereinafter referred to as OFs) a1 and a2 of the first wafer W1 and the second wafer W2 are cut out by a string orthogonal to the crystal direction [011]. The first wafer W1 and the second wafer W2 are bonded to each other so that the OFa1 and a2 do not overlap each other, but the position of one of the OFs with respect to the crystal direction is shifted by the twist angle, and the first wafer When affixing W1 and the second wafer W2, OFa1 and a2 may be exactly overlapped. This facilitates the alignment of the first wafer W1 and the second wafer W2.

  Next, as shown in FIG. 5, the growth substrate 100D is removed by, eg, wet etching. Next, as shown in FIG. 1, a ring-shaped p-side electrode 17D is formed on the surface of the contact layer 16D and an n-side electrode 18D is formed on the back surface of the support substrate 10D, for example, by vacuum evaporation, and then dicing is performed. To form a chip. In this way, the light emitting diode 1 shown in FIG. 1 is manufactured.

  As described above, in the present embodiment, in the step of bonding the first wafer W1 and the second wafer W2, the alignment is performed so that the crystal directions of each other have a twisted relationship. The easy directions are different, so even if they are bonded together with a sufficiently strong pressure, there is no risk of cracking, the bonded surface becomes uniform, the occurrence of voids and the like is reduced, and the yield is improved.

[Second Embodiment]
FIG. 6 shows a cross-sectional structure of a surface emitting semiconductor laser according to the second embodiment of the present invention. The surface emitting semiconductor laser 2 includes a lower DBR mirror layer 21 (first multilayer reflector), a lower cladding layer 22, an active layer 23, an upper cladding layer 24, and an upper DBR mirror layer 25 on one surface side of a support substrate 20. The (second multilayer mirror) and the p-side contact layer 26 are stacked in this order. Here, after a part of the lower DBR mirror layer 21, the lower cladding layer 22, the active layer 23, the upper cladding layer 24, the upper DBR mirror layer 25 and the p-side contact layer 26 are formed up to the p-side contact layer 26, The mesa unit 30 is configured by being selectively etched.

  The support substrate 20 is made of a mixed crystal having a zinc blende structure, for example, n-type GaAs. The lower DBR mirror layer 21, the lower clad layer 22, the upper clad layer 24, the upper DBR mirror layer 25, and the p-type contact layer 26 are also compound semiconductor layers, and are also made of a mixed crystal having a zincblende structure, for example, a GaAs-based semiconductor. Each is composed. The active layer 23 is also a compound semiconductor layer, and is composed of a mixed crystal having a zinc blende structure, for example, an InP-based semiconductor. The GaAs-based semiconductor is a compound semiconductor containing indium (In) as a 3B group element and arsenic (As) as a 5B group element in the long-period periodic table, and the InP-based semiconductor is a long period. It refers to a compound semiconductor containing indium (In), a group 3B element, and phosphorus (P), a group 5B element, in the periodic table.

The lower DBR mirror layer 21 is configured to include a plurality of low-refractive index layers and high-refractive index layers. The low refractive index layer is made of, for example, n-type Al _k Ga _1-k As (0 ≦ k ≦ 1) having a thickness of λ / 4n (λ is an oscillation wavelength and n is a refractive index). For example, it is made of n-type Al _m Ga _1-m As (0 ≦ m ≦ k) having a thickness of λ / 4n. Here, examples of the n-type impurity include silicon (Si) and selenium (Se). The lower clad layer 22 is made of, for example, Al _n Ga _1-n As (0 ≦ n ≦ 1), and the upper clad layer 24 is made of, for example, Al _p Ga _1-p As (0 ≦ p ≦ 1). .

The active layer 23 has, for example, a multiple quantum well structure in which quantum well layers (not shown) and barrier layers (not shown) are alternately stacked. For example, the undoped In _q Ga _1-q P (0 ≦ q ≦ 1) and a barrier layer made of undoped (Al _r Ga _1-r ) _1-s In _s P (0 ≦ r ≦ 1, 0 ≦ s ≦ 1) A plurality of layers are stacked. Here, the In composition values q and s and the Al composition value r of the active layer 23 are determined in consideration of the emission wavelength, carrier density distribution, and the like. The active layer 23 may have a structure other than the multiple quantum well structure, for example, a single quantum well structure or a bulk structure.

  The lower cladding layer 22, the active layer 23, and the upper cladding layer 24 are preferably undoped, but may contain p-type or n-type impurities.

The upper DBR mirror layer 25 includes a low refractive index layer and a high refractive index layer as a set and includes a plurality of sets. This low refractive index layer is made of, for example, p-type Al _t Ga _1-t As (0 ≦ t ≦ 1) having a thickness of λ / 4n (where λ is an oscillation wavelength and n is a refractive index). Is made of, for example, p-type Al _u Ga _1-u As (0 ≦ u ≦ t) having a thickness of λ / 4n. Here, examples of the p-type impurity include zinc (Zn), magnesium (Mg), and beryllium (Be).

  However, in the upper DBR mirror layer 25, a current confinement layer 25C is formed instead of the low refractive index layer at a portion of the low refractive index layer, for example, one set apart from the active layer 23 side. The current confinement layer 25C has a current injection region 25C-1 in the central region of the ring-shaped current confinement region 25C-2.

  The p-type contact layer 26 is made of, for example, p-type GaAs, and has, for example, a circular opening 26A in a region facing the current injection region 25C-1.

Further, the region from the peripheral region of the mesa portion 30 to the peripheral portion of the p-type contact layer 26 is covered with an insulating layer 27 made of, for example, SiO ₂ . A ring-shaped p-side electrode 28 is formed on the p-type contact layer 26 so as to partially cross the insulating layer 27. The p-side electrode 28 is formed by, for example, laminating a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer in this order from the p-side contact layer 26 side. It is connected to the. An n-side electrode 29 is formed on the back surface of the support substrate 20. Here, the n-side electrode 29 has, for example, a structure in which an alloy layer of gold (Au) and germanium (Ge), a nickel (Ni) layer, and a gold (Au) layer are stacked in order from the support substrate 20 side. The support substrate 20 is electrically connected.

  Here, as shown in FIG. 7, the structure having the lower DBR mirror layer 21 on the support substrate 20 is the first structure 31, and the stacked structure of the lower cladding layer 22, the active layer 23, and the upper cladding layer 24 is the second structure 32. Considering the laminated structure of the upper DBR mirror layer 25 and the p-type contact layer 26 as the third structure 33, the crystal planes and crystal orientations of the first structure 31, the second structure 32, and the third structure 33 are as follows. This is the same as the relationship between the support substrate 10 described in the first embodiment and the compound semiconductor layer formed thereon. That is, each of them is composed of a mixed crystal having a zinc blende structure, and the crystal faces S3, S4, S5 of the first structure 31, the second structure 32, and the third structure 33 facing each other are lattice planes ( 100), but the crystal directions [011] and [01-1] of the crystal planes S3 and S4 and the crystal directions [011] and [01-1] of the crystal planes S3 and S5 are Facing different directions. That is, the first structure 31 and the second structure 32 are twisted at an angle θ1, and the first structure 31 and the third structure 33 are twisted at an angle θ2.

  That is, each of the second structure 32 and the third structure 33 is formed by crystal growth on another substrate (a growth substrate 200D, 300D described later) different from the support substrate 20, and the surface light emission of the present embodiment. The type semiconductor laser 2 is formed by removing the growth substrate 200D after bonding the first structure 31 and the second structure 32 to each other and further removing the growth substrate 300D after bonding the third structure 33 to each other. It is formed. Note that the twist angles θ1 and θ2 are preferably one angle within a range of 5 degrees to 85 degrees, and more preferably 45 degrees. The angles θ1 and θ2 may be different from each other, or may be the same angle.

  Thus, in this embodiment, at least the crystal directions [011] and [01-1] of the crystal planes S3 and S4 and the crystal directions [011] and [01-1] of the crystal planes S3 and S5 are respectively Since the first structure 31, the second structure 32, and the third structure 33 are bonded so as to intentionally face different directions, the first structure 31, the second structure 32, the first structure 31, and the first structure 31 The directions in which the three structures 33 are easily cleaved are different from each other.

  In this surface emitting semiconductor laser 2, when a predetermined voltage is applied between the n-side electrode 29 and the p-side electrode 28, current is injected into the active layer 23 through the current injection region 25C-1 in the current confinement layer 25C. As a result, light emission is caused by recombination of electrons and holes. This light is reflected by the pair of the lower DBR mirror layer 21 and the upper DBR mirror layer 25, and causes laser oscillation at a wavelength at which the phase change when it reciprocates once in the element is an integral multiple of 2π. Is emitted. At this time, also in the present embodiment, a layer having a light absorption function, for example, a GaAs substrate (growth substrate 300D) or the like is removed in advance in the manufacturing process, and the opening 26A side has a light absorption function. There is no such layer, which greatly improves the light extraction efficiency.

  Next, an example of a method for manufacturing the surface emitting semiconductor laser 2 will be described.

8 to 13 show the manufacturing method in the order of steps. Here, in order to form a GaAs compound semiconductor layer or an InP compound semiconductor layer, the lower DBR mirror layer 21D, the lower cladding layer 22D, the active layer 23D, the upper cladding layer 24D, the upper DBR mirror layer 25D and the p side The contact layer 26D is formed by, for example, the MOCVD method. At this time, for example, trimethylaluminum (TMA), trimethylgallium (TMG), or arsine (AsH ₃ ) is used as a raw material for a GaAs-based compound semiconductor, and as a raw material for a GaP-based compound semiconductor, for example, trimethylaluminum ( TMA), trimethylgallium (TMG), trimethylindium (TMIn), and phosphine (PH ₃ ) are used. For example, H ₂ Se is used as the source material for the donor impurity, and dimethyl zinc (DMZ) is used as the source material for the acceptor impurity.

  Specifically, as shown in FIG. 8, first, a lower DBR mirror layer 21D and a lower cladding layer 22D are formed in this order on a support substrate 20D made of, for example, n-type GaAs (hereinafter referred to as a first wafer W11). Further, the active layer 23D is formed on the growth substrate 200D made of, for example, InP (hereinafter, the second wafer W12). Further, as shown in FIG. 11, a p-side contact layer 26D, an upper DBR mirror layer 25D, and an upper clad layer 24D are formed in this order on a growth substrate 300D made of, for example, p-type GaAs (hereinafter referred to as a third wafer W13). .

  Next, returning to FIG. 8, with the first wafer W11 and the second wafer W12 facing the lower cladding layer 22D and the active layer 23D, a predetermined temperature and a predetermined pressure F (for example, the wafer size is 3 inches). In the case of 2000N to 8000N). At this time, as shown in FIG. 9, the positional relationship between the first wafer W11 and the second wafer W12 so that the respective crystal directions [011] and [01-1] are twisted at an angle θ1. Set.

  As a result, the direction in which each of the first wafer W11 and the second wafer W12 is easily cleaved is different from each other. Therefore, a pressure F that can provide sufficient bonding strength to the first wafer W11 and the second wafer W12. Even if it adds, there is no possibility that the 1st wafer W11 and the 2nd wafer W12 may break along a crystal direction. Therefore, the manufacturing yield is improved as compared with the conventional case where two wafers are bonded together so that the directions in which the two wafers are easily cleaved are the same.

  Note that the positional relationship of OFa11 and a12 with respect to the crystal direction [011] (FIG. 9) is the same as that described in the first embodiment in the present embodiment. The OFa11 and a12 may be exactly overlapped when the first wafer W1 and the second wafer W2 are bonded together by shifting the angle θ1. The same applies to the relationship between OFa11 of the first wafer W1 and OFa12 of the third wafer W2 described later (FIG. 11).

  Next, as shown in FIG. 10, the growth substrate 200D is removed by, for example, a wet etching method (hereinafter referred to as a fourth wafer W14). Subsequently, as shown in FIG. 11, with the fourth wafer W14 and the third wafer W13 facing the active layer 23D and the upper cladding layer 24D, a predetermined temperature and a predetermined pressure F (for example, the wafer size is In the case of 3 inches, bonding is performed at 2000N to 8000N).

  At this time, as shown in FIG. 12, the fourth wafer W14 and the fourth wafer W14 are aligned so that the crystal directions [011] and [01-1] of the first wafer W11 and the third wafer W13 are twisted at an angle θ2. A positional relationship with the third wafer W13 is set. As a result, the directions in which the fourth wafer W14 and the third wafer W13 are easily cleaved are different from each other, and even if a pressure F is applied to obtain a sufficient bonding strength, the fourth wafer W14 and the third wafer W14. There is no possibility that W13 breaks along the crystal direction, and the manufacturing yield is improved as compared with the conventional method.

  Next, as shown in FIG. 13, the growth substrate 300D is removed by, for example, a wet etching method. Subsequently, for example, a mask layer (not shown) is formed on the p-side contact layer 26D, and the reactive ion etching (RIE) method is used to form the p-side contact layer 26D, the upper DBR mirror layer 25D, A part of the upper cladding layer 24D, the active layer 23D, and the lower cladding layer 22D is selectively removed, and a part of the p-side contact layer 26D is etched to form an opening 26A. Thereby, the mesa post 30 having the opening 26A on the top is formed.

  Next, in a water vapor atmosphere, a part of the upper DBR mirror layer 25 is selectively oxidized from the outside of the mesa post 30 to form a current confinement region 25C-2, whereby a current injection region 25C-1 is formed in the central region. A current confinement layer 25C having the following is formed.

  Next, as shown in FIG. 6, the insulating layer 27 is laminated on the mesa post 30 and the peripheral substrate of the mesa post 30 by, for example, a CVD (Chemical Vapor Deposition) method. Thereafter, a part of the top of the mesa post 30 in the insulating layer 27 is selectively removed by etching to expose the upper DBR mirror layer 25 in the opening 26A, and the outer edge of the opening 26A in the p-side contact layer 26 Expose the area.

  Next, for example, Ti (titanium), Pt (platinum), and Au (gold) are sequentially stacked on the mesa post 30 by, for example, vacuum deposition, and then the upper DBR mirror layer 25 is exposed in the opening 26A by selective etching. Thereby, the ring-shaped p-side electrode 28 is formed.

  Next, after the back surface of the support substrate 20D is appropriately polished to adjust the thickness of the substrate, the n-side electrode 29 is formed on the surface. In this way, the surface emitting semiconductor laser 2 of the present embodiment is manufactured.

  Thus, also in the present embodiment, at least the crystal directions of the first structure 31 and the second structure 32 and the crystal directions of the first structure 31 and the third structure 33 are intentionally different directions, respectively. Since the direction in which the first structure 31 and the second structure 32 and the first structure 31 and the third structure 33 are easily cleaved differs, By the pressure of, it will not break along the cleavage direction. In addition, the bonding surface becomes uniform and the generation of voids and the like is reduced, and the yield is improved.

  In the present embodiment, an active layer 23D for generating long-wavelength light is formed of an InP-based growth substrate 200D, and this is formed of a GaAs-based high thermal conductivity having a lower cladding layer 22D previously formed. Since the image is transferred to the support substrate 20D (support substrate 20) side, the thermal resistance at the substrate is small, and the amount of heat generated can be suppressed.

  Further, an upper clad layer 24D is formed using a GaAs-based growth substrate 200D, transferred to a GaAs-based substrate (supporting substrate 20) onto which the active layer 23D has been transferred, and then a current confinement layer 25 made of AlGaAs and AlAs. Thus, the selective oxidation method as described above, which is difficult in the InP system, can be used.

  The present invention has been described with reference to the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made.

  For example, in the above embodiment, the semiconductor material having a long wavelength band such as GaAs or AlGaInP has been described as an example. However, the present invention is not limited to this, and other semiconductor materials such as nitriding are used. Of course, the present invention can be applied to a semiconductor material of a short wavelength band such as a physical group III-V compound semiconductor.

  In the above embodiment, the case where the crystal planes S1, S2, S3, S4, and S5 facing each other in each semiconductor layer are parallel to the lattice plane (100) has been described, but the present invention is not limited to this. However, the present invention can also be applied to a case where it is parallel to another lattice plane, for example, (111).

  Further, in the above embodiment, the case where the mixed crystal structure constituting each semiconductor layer has a zinc blende structure has been described, but the present invention is not limited to this, and other structures, For example, the present invention can also be applied to a diamond structure or a wurtzite structure.

  For example, when the support substrate 10D is formed of a diamond structure such as silicon (Si) and the crystal plane of the support substrate 10D is parallel to the lattice plane (100), it is easy to cleave as in the above embodiment. The crystal directions are [011] and [01-1]. Therefore, as shown in FIG. 4, the support substrate 10D and the growth substrate 100D are bonded together so that the crystal direction of the support substrate 10D and the crystal direction of the growth substrate 100D are twisted at an angle θ. Thus, the same effects as those of the above-described embodiment can be obtained.

  In addition, when the support substrate 10D is formed of a diamond structure such as silicon (Si) and the crystal plane of the support substrate 10D is parallel to the lattice plane (111), the crystal direction that is easy to cleave is as described above. Differently, as shown in FIGS. 14A to 14C, [1-10], [0-11], and [10-1] are obtained. Therefore, the support substrate 10D and the growth substrate 100D are bonded together so that the crystal direction of the support substrate 10D and the crystal direction of the growth substrate 100D are different from each other and have a twisted relationship at an angle θ3. Thus, the same effects as those of the above-described embodiment can be obtained. Here, the twist angle θ3 is set to one of the crystal directions [1-10], [0-11], and [10-1] of the support substrate 10D and the crystal directions [011] and [01 of the growth substrate 100D. -1] except 0, 30, 60, 90, 120, 150, 180, 210, 240, 270, 300, and 330 degrees, and preferably 5 degrees or more and 25 degrees. One angle within a range of less than or equal to degrees, and more preferably 15 degrees.

  Next, for example, when each semiconductor layer has a wurtzite structure such as a GaN-based material, the crystal planes of the support substrates 10D and 20D and the growth substrates 100D, 200D, and 300D are parallel to the lattice plane (0001). When the crystal directions that are easy to cleave are (0-110), (-1-120), (10-10), (2-1), as shown in FIGS. 10), (-1100), and (-12-10). Therefore, the crystal directions of the support substrates 10D and 20D and the crystal directions of the growth substrates 100D, 200D, and 300D are different from each other and are twisted at an angle θ4 so that the support substrate 10D and the growth substrate are in a twisted relationship. By bonding 100D, the support substrate 20D and the growth substrate 200D, and the support substrate 20D and the growth substrate 300D, the same effects as those of the above-described embodiment can be obtained. Here, the torsion angle θ4 depends on the crystal directions (0-110), (−1-120), (10-10), (2-1-10), (−1100), (−12) of the support substrate 10D. -10) and the crystal orientation (0-110), (-1-120), (10-10), (2-1-10), (-1100), (-12) of the growth substrate 100D −10) excluding 0, 30, 60, 90, 120, 150, 180, 210, 240, 270, 300, 330 degrees, which is the angle at which any one of them overlaps, preferably 5 degrees or more and 25 degrees One angle within a range of less than or equal to degrees, and more preferably 15 degrees.

It is a section lineblock diagram of a light emitting diode concerning a 1st embodiment of the present invention. It is a conceptual diagram for demonstrating the crystal direction of each layer which comprises a light emitting diode. It is a cross-sectional block diagram for demonstrating the manufacturing process of a light emitting diode. FIG. 4 is a conceptual diagram for explaining a continuation process of FIG. 3. FIG. 5 is a cross-sectional configuration diagram for explaining a process subsequent to FIG. 4. It is a cross-sectional block diagram of the surface emitting semiconductor laser which concerns on the 2nd Embodiment of this invention. It is a conceptual diagram for demonstrating the crystal direction of each layer which comprises a surface emitting semiconductor laser. It is a cross-sectional block diagram for demonstrating the manufacturing process of a surface emitting semiconductor laser. It is a conceptual diagram for demonstrating the process of the continuation of FIG. FIG. 10 is a cross-sectional configuration diagram for explaining a step subsequent to FIG. 9. FIG. 11 is a cross-sectional configuration diagram for explaining a process subsequent to FIG. 10. It is a conceptual diagram for demonstrating the process of the continuation of FIG. FIG. 13 is a cross-sectional configuration diagram for explaining a step subsequent to FIG. 12. It is a conceptual diagram showing the crystal direction which is easy to cleave when the crystal plane of the board | substrate which has a diamond structure is parallel to a lattice plane (111). It is a conceptual diagram showing the crystal | crystallization direction which is easy to cleave when the crystal plane of the board | substrate which has a wurtzite structure is parallel to a lattice plane (0001).

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Light emitting diode, 2 ... Surface emitting semiconductor laser, 10, 20 ... Support substrate, 11 ... 1st metal layer, 12 ... 2nd metal layer, 13 ... 1st type | mold clad layer, 14 ... Active layer, 14A, 23A Light emitting region, 15 Second cladding layer, 16 Contact layer, 17, 28 p-side electrode, 17A, 26A Opening, 18, 29 n-side electrode, 21 Lower DBR mirror layer, 22 Lower cladding Layer, 24 ... upper cladding layer, 25 ... upper DBR mirror layer, 25C ... current confinement layer, 25C-1 ... current injection region, 25C-2 ... current confinement region, 26 ... p-side contact layer, 27 ... insulating layer, 30 ... mesa, a1, a2, a11 to a13 ... orientation flat (OF), F ... pressure, L1, L2, L3 ... light, S1 to S5 ... crystal plane, W1, W11 ... first wafer, W2, W12 ... first 2 wafers, 13 ... third wafer, W14 ... fourth wafer.

Claims (28)

Forming a compound semiconductor layer by crystal growth on a first semiconductor substrate having a first crystal direction in a plane;
A second semiconductor substrate having a second crystal direction in a plane, a predetermined pressure on the compound semiconductor layer side of the first semiconductor substrate, and the second crystal direction being twisted with respect to the first crystal direction A step of bonding so that
And a step of removing the first semiconductor substrate from the compound semiconductor layer after bonding the second semiconductor substrate to the first semiconductor substrate. The method of manufacturing a semiconductor light emitting element according to claim 1, wherein the first semiconductor substrate and the second semiconductor substrate have the same crystal structure. 3. The method of manufacturing a semiconductor light emitting element according to claim 2, wherein each of the first semiconductor substrate and the second semiconductor substrate has a zinc blende type crystal structure. The method of manufacturing a semiconductor light emitting element according to claim 2, wherein each of the first semiconductor substrate and the second semiconductor substrate has a wurtzite crystal structure. The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the first semiconductor substrate and the second semiconductor substrate have different types of crystal structures. 6. The method of manufacturing a semiconductor light emitting element according to claim 5, wherein the first semiconductor substrate has a zinc blende type crystal structure, and the second semiconductor substrate has a diamond type crystal structure. The crystal planes in each plane of the first semiconductor substrate and the second semiconductor substrate are {100}, and the crystal directions of the first semiconductor substrate and the second semiconductor substrate are not less than 5 degrees and not more than 85 degrees. The manufacturing method of the semiconductor light-emitting device according to claim 3, further comprising a step of bonding so as to have a twisted relationship within the range. The crystal planes in each plane of the first semiconductor substrate and the second semiconductor substrate are {0001}, and the crystal directions of the compound semiconductor layer and the support substrate are within a range of 5 degrees or more and 25 degrees or less. The manufacturing method of the semiconductor light-emitting device according to claim 4, further comprising a step of bonding so as to have a twisting relationship. The crystal planes in each plane of the first semiconductor substrate and the second semiconductor substrate are {100}, and the crystal directions of the first semiconductor substrate and the second semiconductor substrate are not less than 5 degrees and not more than 85 degrees. The manufacturing method of the semiconductor light-emitting device according to claim 6, further comprising a step of bonding so as to have a twist relationship within the range. The crystal plane in the plane of the first semiconductor substrate is {100}, the crystal plane in the plane of the second semiconductor substrate is {111}, and the first semiconductor substrate and the second semiconductor substrate are The method for manufacturing a semiconductor light-emitting element according to claim 6, further comprising a step of bonding so that the crystal directions of each other are twisted within a range of 5 degrees to 25 degrees. Forming a first metal layer on the compound semiconductor layer after forming the compound semiconductor layer on the first semiconductor substrate;
Forming a second metal layer on the second semiconductor substrate;
The method of manufacturing a semiconductor light emitting device according to claim 1, further comprising: bonding the second semiconductor substrate to the first semiconductor substrate by bringing the first metal layer and the second metal layer into contact with each other. Method. The method of manufacturing a semiconductor light emitting element according to claim 11, wherein the first metal layer and the second metal layer both contain Au (gold). 2. The method of manufacturing a semiconductor light emitting element according to claim 1, comprising forming a first conductive type layer, an active layer, and a second conductive type layer in this order as the compound semiconductor layer on the first semiconductor substrate. . Forming an active layer on the first multilayer reflector after forming a first multilayer reflector as the compound semiconductor layer on the first semiconductor substrate;
Forming a second multilayer mirror on the second semiconductor substrate by crystal growth;
The manufacturing method of a semiconductor light emitting element according to claim 1, further comprising a step of bonding the second semiconductor substrate to the first semiconductor substrate by bringing the active layer and the second multilayer mirror into contact with each other. Method. The active layer is a crystal grown on a third semiconductor substrate having a third crystal direction in the plane;
The active layer of the third semiconductor substrate has a predetermined pressure on the first multilayer film reflector side of the first semiconductor substrate, and the third crystal direction is twisted with respect to the first crystal direction. And the process of pasting together,
The method for manufacturing a semiconductor light emitting element according to claim 14, further comprising: removing the third semiconductor substrate from the active layer after bonding the third semiconductor substrate to the first semiconductor substrate. A compound semiconductor layer having a first crystal direction in the plane;
A semiconductor light emitting device comprising: a support substrate that supports the compound semiconductor layer and has a second crystal direction in a plane, and the second crystal direction is in a twisted relationship with the first crystal direction. element. The semiconductor light emitting element according to claim 16, wherein the compound semiconductor layer and the support substrate have the same crystal structure. The semiconductor light emitting device according to claim 17, wherein the compound semiconductor layer and the support substrate each have a zinc blende type crystal structure. The semiconductor light emitting element according to claim 17, wherein the compound semiconductor layer and the support substrate each have a wurtzite crystal structure. The semiconductor light-emitting element according to claim 16, wherein the compound semiconductor layer and the support substrate have different types of crystal structures. The semiconductor light emitting device according to claim 20, wherein the compound semiconductor layer has a zinc blende type crystal structure, and the support substrate has a diamond type crystal structure. The crystal planes in each plane of the compound semiconductor layer and the support substrate are {100}, and the compound semiconductor layer and the support substrate are twisted within a range in which the crystal directions of each other are in the range of 5 degrees to 85 degrees. The semiconductor light-emitting element according to claim 18, wherein The crystal planes in each plane of the compound semiconductor layer and the support substrate are {0001}, and the compound semiconductor layer and the support substrate are twisted within a range in which the crystal directions of each other are 5 degrees or more and 25 degrees or less. The semiconductor light-emitting element according to claim 19, wherein The crystal planes in each plane of the compound semiconductor layer and the support substrate are {100}, and the compound semiconductor layer and the support substrate are twisted within a range in which the crystal directions of each other are in the range of 5 degrees to 85 degrees. The semiconductor light emitting element according to claim 21, wherein: The crystal plane in the plane of the compound semiconductor layer is {100}, the crystal plane in the plane of the support substrate is {111}, and the crystal direction of the compound semiconductor layer and the support substrate is 5 The semiconductor light emitting element according to claim 21, wherein the semiconductor light emitting element has a twist relationship within a range of not less than 25 degrees and not more than 25 degrees. The semiconductor light emitting element according to claim 16, further comprising a metal layer between the compound semiconductor layer and the support substrate. The semiconductor light emitting element according to claim 16, wherein the compound semiconductor layer includes a second conductive type layer, an active layer, and a first conductive type layer from the support substrate side. The compound semiconductor layer includes a second multilayer reflector, an active layer, and a first multilayer reflector from the support substrate side, and at least the crystal direction of the first multilayer reflector is twisted with the crystal direction of the support substrate. The semiconductor light-emitting element according to claim 16, wherein

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