JP2007188992A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method a high drive current, a transmission conductance, and a sub-threshold characteristic can be improved and a floating body potential effect can be restrained, while suppressing increase in the parasitic capacitance, between the drain and the channel and increase in the sub-threshold leakage current due to DIBL effect. <P>SOLUTION: In the semiconductor device, an SOI-MOSFET 1 has a heavily-doped diffusion region 17c, formed in a support substrate 11a, a heavily-doped diffusion region 17d, formed in the support substrate 11a to be deeper than the heavily-doped diffusion region 17c, and a gate electrode 14 formed on the heavily-doped diffusion region 17c. Furthermore, the SOI-MOSFET 1 has a drain region 15d, formed in an SOI layer 11c on the heavily-doped diffusion region 17d, and a source region 15s formed in the SOI layer 11c, on a side opposite to the drain region 15d, sandwiching below the gate electrode 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device using an SOI (Silicon On Insulator) substrate as a semiconductor substrate and a manufacturing method thereof.

  In recent years, semiconductor devices using an SOI (Silicon On Insulator) substrate have been developed for the purpose of reducing power consumption, high integration, multiple functions, and high speed. The SOI substrate is a semiconductor substrate having a supporting substrate such as a silicon substrate, an insulating film formed on the supporting substrate, and a silicon film formed on the insulating film. Hereinafter, the insulating film on the supporting substrate is referred to as a buried oxide film or a BOX (Buried Oxide) layer, and the silicon film on the BOX layer is referred to as a silicon thin film or an SOI layer.

  As a semiconductor device created using an SOI substrate, there is a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), for example. Hereinafter, this is referred to as SOI-MOSFET. Further, in order to distinguish from the SOI-MOSFET, a MOSFET formed using a bulk semiconductor substrate is hereinafter referred to as a bulk-MOSFET.

  The SOI-MOSFET has a fully depletion (FD) type in which the body region under the channel is completely depleted during conduction, and a partial depletion (PD) in which an undepleted region exists at the bottom of the body region. There are two types: types. The body region refers to an SOI layer sandwiched between the source and drain in a silicon thin film, that is, a region where a channel is formed during operation.

  Such an SOI-MOSFET is characterized in that the semiconductor element formed in the SOI layer is electrically completely isolated from the support substrate by the BOX layer and the element isolation insulating film (also referred to as a field oxide film) (first characteristic) ).

  Of the two types of SOI-MOSFETs, the fully depleted SOI-MOSFET has an S value that exhibits subthreshold characteristics compared to other MOSFETs, that is, a bulk-MOSFET or a partially-depleted SOI-MOSFET ( Subthreshold Slope) is low (second feature). The S value refers to a gate voltage value for changing the drain current by one digit in the subthreshold region while keeping the drain voltage constant.

  Furthermore, a fully depleted SOI-MOSFET differs from other MOSFETs in that a PN junction, that is, a forward parasitic diode is not formed between the source / drain and the substrate / well, so that the junction capacitance can be very small. It also has a feature (third feature) that it can be done.

  From the above first to third characteristics, particularly the fully depleted SOI-MOSFET can (1) reduce the threshold voltage (Vt) without increasing the off-leakage current (subthreshold leakage current). Operation is possible (2) Load capacity CL can be reduced, operation speed and power consumption can be reduced, (3) Signal transmission loss in high frequency operation can be reduced, (4) High resistance silicon wafer Can be used as a support substrate, and the high-frequency performance of semiconductor elements including passive elements can be improved. (5) Malfunctions caused by crosstalk through the substrate can be reduced. (6) Malfunctions including latch-up phenomenon are prevented. Various effects such as that can be realized.

  In a fully depleted SOI-MOSFET, the junction capacitance formed between the gate and the support substrate can be further reduced by increasing the thickness of the BOX layer. As a result, effects such as (1) high drive current and mutual conductance, (2) substantially ideal subthreshold characteristics, and (2) suppression of floating body effect (FBE) can be obtained. it can. Note that the mutual conductance refers to the rate of change of the drain current with respect to the change of the gate voltage under a constant drain voltage.

  However, when the BOX layer is thickened, the electric field spreading from the drain penetrates through the BOX layer to the channel (for example, see Non-Patent Document 1 shown below). When such a phenomenon occurs, the parasitic capacitance between the drain and the channel increases, and there arises a problem that the subthreshold leakage current increases due to the DIBL (Drain-Induced Barrier Lowering) effect.

For reference, for example, Patent Document 1 shown below discloses a configuration in which a diffusion region is formed in a region of a support substrate, which is a region under a low-concentration offset region formed between a drain and a gate. Has been.
T. Ernst, et al., “Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture”, Solid-State Electronics 46 (2002), pp. 373-378 JP 2003-273363 A

  As a method of avoiding an increase in the parasitic capacitance between the drain and the channel and an increase in the subthreshold leakage current due to the DIBL (Drain-Induced Barrier Lowering) effect, for example, a method of reducing the thickness of the BOX layer, A method of increasing the impurity concentration can be considered. However, in these methods, since the junction capacitance formed between the gate and the support substrate increases, the effects described above are reduced.

  As described above, in the conventional technique, when an attempt is made to obtain a high drive current, a mutual conductance, an improvement in subthreshold characteristics, a suppression of the floating body potential effect, etc., the parasitic capacitance between the drain and the channel increases or the DIBL effect causes There is a problem that the subthreshold leakage current increases.

  In the technique disclosed in Patent Document 1 described above, a diffusion region is formed in a region of the support substrate, which is a region below the low concentration offset region formed between the drain and the gate. In this configuration, there is a problem that the electric field extending from the drain to the channel through the BOX layer cannot be efficiently suppressed. Furthermore, in the technique according to Patent Document 1, it is necessary to locally increase the thickness of the BOX layer other than under the channel, but there is a problem that it is practically difficult to form such a BOX layer. To do.

  Accordingly, the present invention has been made in view of the above problems, and suppresses an increase in the parasitic capacitance between the drain and the channel and an increase in the subthreshold leakage current due to the DIBL effect, while maintaining a high driving current, a mutual conductance, and a subthreshold. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can realize improvement of hold characteristics and suppression of floating body potential effect.

  In order to achieve this object, a semiconductor device according to the present invention is formed on a support substrate, an SOI substrate having an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer, and a support substrate. A first diffusion region formed, a second diffusion region formed in a region deeper than the first diffusion region of the support substrate, a gate electrode formed on the semiconductor layer and on the first diffusion region, and a semiconductor layer A drain region formed in a region on the second diffusion region, and a source region formed in a region opposite to the drain region across the gate electrode in the semiconductor layer.

  As described above, since the first or second diffusion region is formed in each of the regions below the drain region and the gate electrode in the support substrate, the first or second diffusion region acts on the electric field extending from the drain region. It is possible to prevent the electric field line extending from the drain region from penetrating through the insulating layer under the semiconductor layer to the semiconductor layer under the gate electrode, that is, the region where the channel is formed during operation (body region). It becomes. That is, it is possible to reduce the parasitic capacitance formed between the drain region and the body region. As a result, for example, even when the insulating layer in the SOI substrate is thickened, the parasitic capacitance formed between the drain region and the body region increases, or the subthreshold leakage current increases due to the DIBL effect. The problem to say can be avoided.

  Furthermore, in the present invention, the second diffusion region formed under the drain region is formed in a region deeper than the first diffusion region formed under the gate electrode, in other words, a region deeper to some extent from the upper surface of the support substrate. As a result, it is possible to suppress an increase in junction capacitance formed between the drain region and the second diffusion region. As a result, since the load capacitance CL can be reduced, it is possible to increase the operation speed and reduce the power consumption, and to reduce the signal transmission loss in the high frequency operation.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a SOI substrate having a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer; Forming a first diffusion region; forming a second diffusion region in a region deeper than the first diffusion region of the support substrate; and forming a gate electrode on the semiconductor layer and on the first diffusion region. And a step of forming a drain region in a region on the second diffusion region in the semiconductor layer, and a step of forming a source region in a region opposite to the drain region across the gate electrode in the semiconductor layer. Is done.

  As described above, the first or second diffusion region formed in each of the drain region and the gate electrode in the supporting substrate acts on the electric field extending from the drain region, and therefore, the electric field direction line extending from the drain region is a semiconductor. It is possible to manufacture a semiconductor device that can suppress penetration of the semiconductor layer under the gate electrode through the insulating layer under the layer, that is, the region (body region) where the channel is formed during operation. That is, it is possible to manufacture a semiconductor device in which the parasitic capacitance formed between the drain region and the body region is reduced. As a result, for example, even when the insulating layer in the SOI substrate is thickened, the parasitic capacitance formed between the drain region and the body region increases, or the subthreshold leakage current increases due to the DIBL effect. The problem to say can be avoided.

  Furthermore, in the present invention, the second diffusion region formed under the drain region is formed in a region deeper than the first diffusion region formed under the gate electrode, in other words, a region deeper to some extent from the upper surface of the support substrate. As a result, it is possible to suppress an increase in junction capacitance formed between the drain region and the second diffusion region. As a result, since the load capacitance CL can be reduced, it is possible to increase the operation speed and reduce the power consumption, and to manufacture a semiconductor device in which the signal transmission loss in the high-frequency operation is reduced.

  According to the present invention, while suppressing an increase in drain-channel parasitic capacitance and an increase in subthreshold leakage current due to the DIBL effect, high drive current and mutual conductance, improvement in subthreshold characteristics, and suppression of floating body potential effect A semiconductor device capable of realizing the above and a manufacturing method thereof can be realized.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In the following description, each drawing only schematically shows the shape, size, and positional relationship to the extent that the contents of the present invention can be understood. Therefore, the present invention is illustrated in each drawing. It is not limited to only the shape, size, and positional relationship. Moreover, in each figure, a part of hatching in a cross section is abbreviate | omitted for clarity of a structure. Furthermore, the numerical values exemplified below are merely preferred examples of the present invention, and therefore the present invention is not limited to the illustrated numerical values.

  First, Embodiment 1 according to the present invention will be described in detail with reference to the drawings.

Configuration FIG. 1 is a cross-sectional view showing a schematic configuration of an SOI-MOSFET 1 which is a semiconductor device according to the present embodiment. FIG. 1 shows a cross-sectional structure when the SOI-MOSFET 1 is cut along a plane perpendicular to the gate width direction.

  As shown in FIG. 1, the SOI-MOSFET 1 includes a support substrate 11a, a BOX layer (insulating layer) 11b formed on the support substrate 11a, and an SOI layer (semiconductor layer) 11c formed on the BOX layer 11b. The SOI substrate 11, three high-concentration diffusion regions 17c (first diffusion region), 17d (second diffusion region) and 17s (third diffusion region) formed on the support substrate 11a, and the SOI layer 11c are connected to a plurality of elements. An element isolation insulating film (also referred to as a field oxide film) 12 partitioned into a formation region (also referred to as an active region), a drain region 15d and a source region 15s formed in an element formation region of the SOI layer 11c, a drain region 15d and a source The body region 16 sandwiched between the regions 15s, the gate insulating film 13 formed on the body region 16, and the gate formed on the gate insulating film 13. And a gate electrode 14.

The support substrate 11a in the SOI substrate 11 is a bulk silicon substrate containing, for example, p-type impurities so as to have a concentration of about 1 × 10 ¹⁵ / cm ^3, for example. The substrate resistance is, for example, about 8 to 22 Ω (ohms). However, the present invention is not limited to this, and various semiconductor substrates can be applied.

  The BOX layer 11b in the SOI substrate 11 is a silicon oxide film having a thickness of about 1000 to 2000 angstroms, for example. However, the present invention is not limited to this, and various insulating films can be applied.

The SOI layer 11c in the SOI substrate 11 is a silicon thin film in which p-type impurities (for example, boron ions) are diffused so as to have a relatively thin concentration of, for example, about 1 to 3 × 10 ¹⁵ / cm ³ . However, the present invention is not limited to this, and can be changed in any manner as long as the impurity concentration provides a desired threshold voltage Vt. Moreover, the film thickness can be about 200-1000 mm, for example. Note that a non-doped silicon thin film can also be applied to the SOI layer 11c. In this case, the impurity concentration is the same as that of the support substrate 11a, for example, about 1 × 10 ¹⁵ / cm ³ .

  As described above, the SOI layer 11c in the SOI substrate 11 is partitioned into an active region and a field region by forming the element isolation insulating film 12. The element isolation insulating film 12 can be formed using, for example, a LOCOS (Local Oxidation of Silicon) method. However, the present invention is not limited to this, and it can also be formed by using, for example, an STI (Shallow Trench Isolation) method.

As described above, the drain region 15d and the source region 15s are formed in the active region in the SOI layer 11c. The drain region 15d and the source region 15s are implanted and diffused so that, for example, n-type impurities (for example, arsenic ions or phosphorus ions) have a concentration of, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^3. Can be formed. A region where the drain region 15d and the source region 15s in the active region of the SOI layer 11c are not formed becomes a region where a channel is formed during operation, that is, the body region 16. Therefore, the body region 16 according to the present embodiment is a non-doped region or a region having a relatively low impurity concentration.

  As described above, in this embodiment, since the impurity concentration of the body region 16 is set to be as low as the impurity concentration of the support substrate 11a, carriers passing through the channel formed in the body region 16 during conduction become the body region. 16 can be reduced from being scattered by the impurities present in 16. As a result, it is possible to increase a current (hereinafter referred to as drive current) that flows through the SOI-MOSFET 1 during conduction.

  Further, the gate insulating film 13 is formed on the region sandwiched between the drain region 15d and the source region 15s in the active region of the SOI layer 11c, in other words, on the body region 16. The gate insulating film 13 can be a silicon oxide film formed by, for example, thermally oxidizing the surface of the SOI layer 11c. However, the present invention is not limited to this. For example, a silicon oxide film formed by a CVD (Chemical Vapor Deposition) method or an insulating film formed by another method can also be applied. The film thickness of the gate insulating film 13 can be about 20 to 50 mm, for example.

  As described above, the gate electrode 14 is formed on the gate insulating film 13. The gate electrode 14 may be formed of a polysilicon film having conductivity by including, for example, a predetermined impurity (preferably an n-type impurity), or may include, for example, titanium, aluminum, other metals, or any of them. It can also be formed with a metal film formed of an alloy or the like. In this description, the case where the gate electrode 14 is formed of aluminum will be described as an example. The length of the gate electrode 14 in the gate length direction can be about 100 nm (nanometers), for example. Moreover, the film thickness can be about 1500-2000 mm, for example.

Further, in the high concentration diffusion region 17c in the support substrate 11a, for example, a p-type impurity is implanted into a region below the gate electrode 14 so as to have a concentration of, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^3. Formed with. The high-concentration diffusion region 17c has a number near the upper surface of the support substrate 11a, for example, a region where the upper end of the high-concentration diffusion region 17c coincides with the upper surface of the support substrate 11a or the depth D1 (see FIG. 1) of the upper end from the upper surface of the support substrate 11a. It is formed in a region that is about ten inches.

The high-concentration diffusion regions 17d and 17s in the support substrate 11a have, for example, a p-type impurity concentration of, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ^{3 in} the regions below the drain region 15d and the source region 15s. It is formed by injecting. The high concentration diffusion regions 17d and 17s are formed in a region where the upper end depth D2 (see FIG. 1) from the upper surface of the support substrate 11a is about 500 to 1000 mm.

  Of these high-concentration diffusion regions 17c, 17d, and 17s, the high-concentration diffusion regions 17c and 17d act on the electric field extending from the drain region 15d, thereby causing electric field lines extending from the drain region 15d. Is a structure for suppressing the penetration of the body region 16 through the BOX layer 11b. That is, this is a configuration for reducing the parasitic capacitance formed between the drain region 15 d and the body region 16.

  Further, the high concentration diffusion regions 17c and 17s act on the electric field extending from the source region 15s, so that the electric field lines extending from the source region 15s penetrate through the BOX layer 11b to the body region 16. This is a configuration for preventing this. That is, this is a configuration for reducing the parasitic capacitance formed between the source region 15 s and the body region 16.

  In this embodiment, these high-concentration diffusion regions 17c, 17d, and 17s are formed under the body region 16, the drain region 15d, and the source region 15s, respectively, so that the BOX layer 11b in the SOI substrate 11 is thickened. The problem that the parasitic capacitance formed between the drain region 15d or the source region 15s and the body region 16 increases or the subthreshold leakage current increases due to the DIBL effect can be avoided. Since the parasitic capacitance formed between the source region 15s and the body region 16 is smaller than the parasitic capacitance formed between the drain region 15d and the body region 16, in the present embodiment. The high concentration diffusion region 17s under the source region 15s can be omitted.

  Further, in this embodiment, a high concentration diffusion region 17c formed under the gate electrode 14 is formed in the vicinity of the upper surface of the support substrate 11a. Thereby, it is possible to efficiently act on the electric field spreading from the drain region 15d. That is, it is possible to efficiently reduce the parasitic capacitance formed between the drain region 15d and the body region 16, and to efficiently reduce the subthreshold leakage current due to the DIBL effect.

  Furthermore, in this embodiment, the high concentration diffusion regions 17d and 17s formed below the drain region 15d and the source region 15s are formed in a region deep to some extent from the upper surface of the support substrate 11a. In this example, as described above, the depth D2 from the upper surface of the support substrate 11a at the upper end of each of the high concentration diffusion regions 17d and 17s is formed in a region of about 500 to 1000 mm. In this way, the high concentration diffusion region 17d under the drain region 15d and the high concentration diffusion region 17s under the source region 15s are formed in a deep region to some extent in the support substrate 11a, thereby forming a junction formed therebetween. It is possible to suppress an increase in capacity. As a result, the load capacitance CL can be reduced, so that the operation can be speeded up and the power consumption can be reduced, and the signal transmission loss in the high frequency operation can be reduced.

Manufacturing Method Next, a manufacturing method of the SOI-MOSFET 1 according to this embodiment will be described in detail with reference to the drawings. 2 to 5 are process diagrams showing a method for manufacturing the SOI-MOSFET 1 according to this embodiment.

  In this manufacturing method, as shown in FIG. 2A, an SOI substrate 11 in which a BOX layer 11b and an SOI layer 11c are sequentially stacked on a support substrate 11a is prepared. The BOX layer 11b is a silicon oxide film having a film thickness of about 1000 to 2000 mm, for example, as described above. Further, as described above, the SOI layer 11c is a silicon thin film having a film thickness of, for example, about 200 to 1000 mm.

  Next, a silicon oxide film 101 having a thickness of, for example, about 100 mm is formed on the SOI layer 11c by, for example, thermal oxidation. Subsequently, a silicon nitride film 102 having a thickness of, for example, about 200 mm is formed on the silicon oxide film 101 by, eg, CVD. The silicon nitride film 102 is an antioxidant film for preventing an active region in the SOI layer 11c from being thermally oxidized when forming an element isolation insulating film 12 described later. The silicon oxide film 101 is a buffer film for bringing the silicon nitride film 102, which is an antioxidant film, into close contact with the SOI layer 11c. Subsequently, the silicon nitride film 102 and the silicon oxide film 101 are patterned so as to remain on an active region in the SOI layer 11c by, for example, an existing photolithography process and an etching process. Subsequently, by thermally oxidizing the SOI layer 11c using the silicon nitride film 102 as a mask, as shown in FIG. 2B, an element isolation insulating film 12 for partitioning the SOI layer 11c into an active region and a field region. Form. As a result, the silicon thin film 16A remains in the active region in the SOI layer 11c.

Next, by thermally oxidizing the surface of the SOI layer 11c on which the element isolation insulating film 12 is formed, a silicon oxide film 103 having a thickness of, for example, about 100 mm is formed on the SOI layer 11c. Subsequently, as shown in FIG. 2C, boron ions, which are impurities having p-type conductivity, are accelerated and implanted into the silicon thin film 16A in the SOI layer 11c, for example, to about 10 KeV (kiloelectron volts). . The dose at this time is, for example, about 1 × 10 ¹² / cm ² . Through this process, the silicon thin film 16A in the SOI layer 11c becomes a silicon thin film 16B having an impurity concentration of, for example, about 1 to 3 × 10 ¹⁵ / cm ³ . Note that the silicon oxide film 103 formed on the SOI layer 11c functions as a mask for reducing damage to the SOI layer 11c during impurity implantation. Further, since the element isolation insulating film 12 is formed in the SOI layer 11c as described above, in this step, impurities are implanted into the silicon thin film 16A in the SOI layer 11c in a self-aligning manner. Further, the implanted impurity is thermally diffused, for example.

Next, a predetermined resist solution is spin-coated on the silicon oxide film 103, and a resist pattern R11 having an opening on the region to be the body region 16 in the silicon thin film 16B is formed through an existing photolithography process. Subsequently, as shown in FIG. 3A, by implanting boron ions, which are p-type impurities, for example, by accelerating them to about 30 KeV from the openings in the resist pattern R11, impurities are formed in the vicinity of the surface of the support substrate 11a. A high concentration diffusion region 17c having a concentration of about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ is formed. The region where the high concentration diffusion region 17c is formed is only under the region where the gate electrode 14 is formed as described above. Further, the implanted impurities are thermally diffused, for example. Further, in this description, the silicon oxide film 103 used in the process shown in FIG. 2C is used as it is in the process shown in FIG. 3A, but the present invention is not limited to this, and the silicon oxide film 103 is used. After removal, another silicon oxide film may be formed again.

  Next, after removing the resist pattern R11, the upper surface of the SOI layer 11c is thermally oxidized to form a silicon oxide film 13A having a thickness of, for example, about 20 to 50 mm, as shown in FIG. This silicon oxide film 13A is patterned into the gate insulating film 13 in a later step.

  Next, a silicon nitride film 104 having a film thickness equal to or greater than that of the gate electrode 14, for example, approximately 1500 to 2000 mm, is formed on the entire surface of the SOI layer 11 c by, eg, CVD. Subsequently, an opening is formed in the region of the silicon nitride film 104 where the gate electrode 14 is formed, for example, through an existing photolithography process and etching process. Subsequently, by depositing a metal such as aluminum by, for example, a CVD method, as shown in FIG. 4A, the film thickness is such that at least the opening formed in the silicon nitride film 104 is filled, that is, about 1500 to 2000 mm or more. A conductor film 14A having a thickness of 1 mm is formed.

  Next, the conductor film 14A is patterned to the gate electrode 14 by polishing the conductor film 14A to such an extent that the silicon nitride film 104 is exposed by, for example, CMP (Chemical and Mechanical Polishing). At this time, the conductor film 14A (which may include the silicon nitride film 104) is polished so that the thickness of the gate electrode 14 is, for example, about 1500 to 2000 mm. Subsequently, after the silicon nitride film 104 is removed by existing etching, the exposed silicon oxide film 13A is etched. In the etching of the silicon nitride film 104, conditions that allow a sufficient selection ratio between the gate electrode 14 and the silicon oxide film (the silicon oxide film 13A and the element isolation insulating film 12) are applied. In the etching of the silicon oxide film 13A, conditions that allow a sufficient selection ratio with the gate electrode 14 are applied. Thereby, as shown in FIG. 4B, the gate electrode 14 and the gate insulating film 13 under the gate electrode 14 are formed.

Next, a silicon oxide film 105 having a thickness of, for example, about 100 mm is formed on the exposed SOI layer 11c and the gate electrode 14 by, eg, CVD. Subsequently, as shown in FIG. 5A, for example, boron ions, which are p-type impurities, are accelerated and implanted, for example, to about 30 KeV or more (for example, about 40 KeV) from the silicon oxide film 105, thereby supporting the support substrate. High concentration diffusion regions 17d and 17s having an impurity concentration of, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ are formed in a region deep by a predetermined distance (D2) from the upper surface in 11a. At this time, the gate electrode 14 functions as a mask at the time of impurity implantation. Therefore, the high concentration diffusion regions 17d and 17s are formed under the drain region 15d and the source region 15s, respectively, in a self-aligned manner. Note that the silicon oxide film 105 formed on the SOI layer 11c functions as a mask for reducing damage to the SOI layer 11c during impurity implantation. Further, the implanted impurities are thermally diffused, for example.

Next, as shown in FIG. 5B, for example, arsenic ions or phosphorus ions, which are n-type impurities, are implanted at an acceleration of, for example, about 10 KeV from the silicon oxide film 105 to thereby form a gate electrode in the SOI layer 11c. 14, a drain region 15 d and a source region 15 s having an impurity concentration of, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ are formed in a region other than below. At this time, the gate electrode 14 functions as a mask at the time of impurity implantation. For this reason, the drain region 15d and the source region 15s are formed in a pair of regions sandwiching the gate electrode 14 below in a self-aligning manner. Note that the silicon oxide film 105 formed on the SOI layer 11c functions as a mask for reducing damage to the SOI layer 11c during impurity implantation, as in the step shown in FIG. The implanted impurities are thermally diffused. Further, after forming the drain region 15d and the source region 15s, the silicon oxide film 105 is removed. Furthermore, in this description, the silicon oxide film 105 used in the step shown in FIG. 5A is used as it is in the step shown in FIG. 5B, but the present invention is not limited to this, and the silicon oxide film 105 is used. After removing the film, another silicon oxide film may be formed again.

  Through the steps as described above, the SOI-MOSFET 1 according to the present embodiment as shown in FIG. 1 can be manufactured.

As described above, the SOI-MOSFET 1 according to the present embodiment includes the support substrate 11, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b. On the SOI layer 11c, the SOI substrate 11, the high concentration diffusion region 17c formed in the support substrate 11a, the high concentration diffusion region 17d formed in a region deeper than the high concentration diffusion region 17c of the support substrate 11, and The gate electrode 14 formed on the high concentration diffusion region 17c, the drain region 15d formed in the region on the high concentration diffusion region 17d in the SOI layer 11c, and the drain region 15d across the gate electrode 14 in the SOI layer 11c. And a source region 15s formed in the opposite region.

  In addition, the method for manufacturing the SOI-MOSFET 1 according to the present embodiment includes an SOI substrate 11 having a support substrate 11a, a BOX layer 11b formed on the support substrate 11a, and an SOI layer 11c formed on the BOX layer 11b. The high concentration diffusion region 17c is formed in the support substrate 11a, the high concentration diffusion region 17d is formed in a region deeper than the high concentration diffusion region 17c of the support substrate 11a, and the high concentration diffusion region is formed on the SOI layer 11c. A gate electrode 14 is formed on 17c, a drain region 15d is formed in a region on the high concentration diffusion region 17d in the SOI layer 11c, and a region on the opposite side of the drain region 15d across the gate electrode 14 in the SOI layer 11c. A source region 15s is formed.

  In this way, by forming the high concentration diffusion regions 17d and 17c in the regions of the support substrate 11a below the drain region 15d and the gate electrode 14, respectively, the high concentration diffusion regions 17d and 17c extend from the drain region 15d. Therefore, the electric field direction line extending from the drain region 15d passes through the BOX layer 11b under the SOI layer 11c and the SOI layer 11c under the gate electrode 14, that is, a region where a channel is formed during operation (body region 16). It becomes possible to suppress penetrating into. That is, the parasitic capacitance formed between the drain region 15d and the body region 16 can be reduced. Thereby, for example, even when the BOX layer 11b in the SOI substrate 11 is thickened, the parasitic capacitance formed between the drain region 15d and the body region 16 increases, or the subthreshold leakage current increases due to the DIBL effect. The problem of doing so can be avoided.

  In this embodiment, the high concentration diffusion region 17d formed under the drain region 15d is deeper than the high concentration diffusion region 17c formed under the gate electrode 14, in other words, a region deeper to some extent from the upper surface of the support substrate 11a. Forming. As a result, it is possible to suppress an increase in junction capacitance formed between the drain region 15d and the high concentration diffusion region 17d. As a result, since the load capacitance CL can be reduced, it is possible to increase the operation speed and reduce the power consumption, and to reduce the signal transmission loss in the high frequency operation.

  Further, in the present embodiment, the high concentration diffusion region 17s formed in the region deeper than the high concentration diffusion region 17c of the support substrate 11a and on the opposite side of the high concentration diffusion region 17d across the high concentration diffusion region 17c is further provided. The source region 15s is formed in a region on the high concentration diffusion region 17s in the SOI layer 11c.

  In this way, by forming the high concentration diffusion regions 17s and 17c in the support substrate 11a under the source region 15s and under the gate electrode 14, respectively, the electric field in which the high concentration diffusion regions 17s and 17c extend from the source region 15s. Therefore, it is possible to prevent the line of the electric field extending from the source region 15s from penetrating the body region 16 through the BOX layer 11b below the SOI layer 11c. That is, the parasitic capacitance formed between the source region 15s and the body region 16 can be reduced. Thereby, for example, even when the BOX layer 11b in the SOI substrate 11 is thickened, the parasitic capacitance formed between the source region 15d and the body region 16 increases, or the subthreshold leakage current increases due to the DIBL effect. The problem of doing so can be avoided.

  In the present embodiment, the high concentration diffusion region 17s formed under the source region 15s is deeper than the high concentration diffusion region 17c formed under the gate electrode 14, in other words, a region deeper to some extent from the upper surface of the support substrate 11a. Forming. As a result, it is possible to suppress an increase in junction capacitance formed between the source region 15s and the high concentration diffusion region 17s. As a result, since the load capacitance CL can be reduced, it is possible to increase the operation speed and reduce the power consumption, and to reduce the signal transmission loss in the high frequency operation.

  In the present embodiment, the high-concentration diffusion region 17c is formed on or on the support substrate 11a. Thus, by forming the high concentration diffusion region 17c under the gate electrode 14 in the vicinity of the upper surface of the support substrate 11a, the high concentration diffusion region 17c can efficiently act on the electric field extending from the drain region 15d. As a result, the parasitic capacitance formed between the drain region 15d and the body region 16 can be more effectively reduced.

  In this embodiment, the impurity concentration of the SOI layer 11c, that is, the body region 16, is the same as the impurity concentration of the support substrate 11a or substantially the same as the impurity concentration of the support substrate 11a. In this embodiment, by reducing the impurity concentration of the body region 16 in this way, carriers passing through the channel formed in the body region 16 during conduction are scattered by the impurities present in the body region 16. Can be reduced. As a result, the drive current of the SOI-MOSFET 1 can be increased.

  Next, a second embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of the first embodiment.

Configuration FIG. 6 is a cross-sectional view showing a schematic configuration of an SOI-MOSFET 2 which is a semiconductor device according to the present embodiment. 6 shows a cross-sectional structure when the SOI-MOSFET 2 is cut along a plane perpendicular to the gate width direction, as in FIG.

  As shown in FIG. 6, the SOI-MOSFET 2 includes an SOI substrate 11 composed of a support substrate 11a, a BOX layer 11b formed on the support substrate 11a, and an SOI layer 11c formed on the BOX layer 11b, and a support substrate 11a. The three high-concentration diffusion regions 17c, 17d, and 17s formed on the element isolation insulating film 12 that partitions the SOI layer 11c into a plurality of element formation regions (also referred to as active regions), and the element formation region of the SOI layer 11c The formed drain region 15d and source region 15s, the body region 16 sandwiched between the drain region 15d and source region 15s, the gate insulating film 13 formed on the body region 16, and the gate insulating film 13. And a gate electrode 24. That is, in this embodiment, the gate electrode 14 in the first embodiment is replaced with the gate electrode 24.

  As shown in FIG. 6, the gate electrode 24 includes two gates made of polysilicon having conductivity when a metal gate (hereinafter referred to as a metal gate) 24 a contains an impurity having n-type conductivity, for example. It has a structure sandwiched by 24b (hereinafter referred to as polysilicon gate).

  In this configuration, the metal gate 24a is formed of, for example, titanium, aluminum, other metal, or an alloy containing any of them, like the gate electrode 14 in the first embodiment. In this description, the case where the metal gate 24a is formed of aluminum will be described as an example. Moreover, the film thickness can be about 1500-2000 mm, for example.

  On the other hand, as described above, the polysilicon gate 24b is formed of, for example, polysilicon containing impurities having n-type conductivity, for example, boron ions. Further, the film thickness can be set to, for example, about 1500 to 2000 mm, similarly to the metal gate 24a.

  In this embodiment, the threshold voltage Vt of the SOI-MOSFET 2 is controlled by controlling the ratio of the metal gate 24a in the gate electrode 24, that is, the length of the metal gate 24a in the gate length direction. Here, the relationship between the length of the metal gate 24a (hereinafter referred to as the metal gate length La) and the threshold voltage Vt of the SOI-MOSFET 2 will be described with reference to FIGS. 7 (a) and 7 (b).

  FIG. 7A is an enlarged view showing the gate electrode 24 extracted from the present embodiment. FIG. 7B is a graph showing the dependency of the threshold voltage Vt of the SOI-MOSFET 2 on the metal gate length La. In this description, as shown in FIGS. 7A and 7B, the length of the entire gate electrode 24 in the gate length direction is L, and polysilicon formed on both sides of the metal gate 24a, respectively. The length of the gate 24b in the gate length direction is set to the same length Lb / 2. Further, the length L in the gate length direction of the entire gate electrode 24 is fixed to 100 nm. Therefore, the relationship L = La + 2 × Lb / 2 = La + Lb = 100 [nm] is established.

  As shown in FIG. 7B, when the length of the metal gate length La is increased, that is, the ratio of the metal gate 24a in the gate electrode 24 in the gate length direction is increased, the threshold voltage Vt of the SOI-MOSFET 2 is increased. . In other words, when the length of the metal gate length La is shortened, that is, when the ratio of the metal gate 24a in the gate electrode 24 in the gate length direction is decreased, the threshold voltage Vt of the SOI-MOSFET 2 is decreased. Thus, by controlling the ratio of the metal gate 24a in the gate electrode 24, the threshold voltage Vt of the SOI-MOSFET 2 can be controlled in this embodiment.

  Such a configuration is particularly effective when the impurity concentration in the body region 16 is low. That is, when the impurity concentration in the body region 16 is low, the threshold voltage Vt of the SOI-MOSFET 2 is lowered, and the current blocking ability between the drain and the source when not conducting is lowered, thereby increasing the subthreshold leakage current. There is. Therefore, by increasing the threshold voltage Vt of the SOI-MOSFET 2 using the configuration of the gate electrode 24 as in the present embodiment, the drive current of the SOI-MOSFET 2 is reduced without increasing the impurity concentration of the body region 16. It is possible to reduce the subthreshold leakage current without doing so.

  In the present embodiment, the two polysilicon gates 24b sandwiching the metal gate 24a have the same length in the gate length direction, but the present invention is not limited to this. For example, the gate of the polysilicon gate 24b on the drain side is used. Various modifications can be made such as making the length in the long direction longer than the length in the gate length direction of the polysilicon gate 24b on the source side. Since other configurations are the same as those of the first embodiment, detailed description thereof is omitted here.

Manufacturing Method Next, a manufacturing method of the SOI-MOSFET 2 according to the present embodiment will be described in detail with reference to the drawings. 8 to 11 are process diagrams showing a method for manufacturing the SOI-MOSFET 2 according to this embodiment. In the manufacturing method according to the present embodiment, the steps until the high concentration diffusion region 17c is formed in the support substrate 11a are the same as the steps described with reference to FIGS. 2A to 3A in the first embodiment. Since this is the same, detailed description is omitted here.

In this manufacturing method, first, as described with reference to FIGS. 2A to 3A in the first embodiment, the high concentration diffusion region 17c is formed in the support substrate 11a. Subsequently, after removing the resist pattern R11 (see FIG. 3A), a predetermined resist solution is spin-coated again on the silicon oxide film 103, and an existing photolithography process is performed. A resist pattern R21 having openings is formed on the regions to be the drain region 15d and the source region 15s. Subsequently, as shown in FIG. 8A, boron ions, which are p-type impurities, are accelerated and implanted, for example, to about 30 KeV or more (for example, about 40 KeV) from the openings in the resist pattern R21, thereby supporting the support substrate. High concentration diffusion regions 17d and 17s having an impurity concentration of, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ are formed in a region deep by a predetermined distance (D2) from the upper surface in 11a. The regions where the high concentration diffusion regions 17d and 17s are formed are only under the regions where the drain region 17d and the source region 17s are formed, as in the first embodiment. Further, the implanted impurities are thermally diffused, for example. Further, in this description, the silicon oxide film 103 used in the process shown in FIG. 2C is used as it is in the process shown in FIG. 8A, but the present invention is not limited to this, and the silicon oxide film 103 is used. After removing the film, another silicon oxide film may be formed again.

  Next, after removing the resist pattern R21, the upper surface of the SOI layer 11c is thermally oxidized to form a silicon oxide film 13A having a thickness of, for example, about 20 to 50 mm, as shown in FIG. 8B. This silicon oxide film 13A is patterned into the gate insulating film 13 in a later step.

  Next, a silicon nitride film 204 having a film thickness equal to or greater than that of the metal gate 24a, for example, approximately 1500 to 2000 mm, is formed on the entire surface of the SOI layer 11c by, for example, CVD. Subsequently, a region opening for forming the metal gate 24a in the silicon nitride film 204 is formed through, for example, an existing photolithography process and an etching process. Subsequently, by depositing a metal such as aluminum by CVD, for example, as shown in FIG. 8C, the film thickness is such that at least the opening formed in the silicon nitride film 204 is filled, that is, about 1500 to 2000 mm or more. A conductive film 24A having a thickness of 1 mm is formed.

  Next, the conductor film 24A is patterned to the metal gate 24a by polishing the conductor film 24A to such an extent that the silicon nitride film 204 is exposed by, eg, CMP. At this time, the conductor film 24A (which may include the silicon nitride film 204) is polished so that the thickness of the metal gate 24a is, for example, about 1500 to 2000 mm. Subsequently, the silicon nitride film 204 is removed by existing etching. In the etching of the silicon nitride film 204, conditions that allow a sufficient selection ratio between the metal gate 24a and the silicon oxide film (the silicon oxide film 13A and the element isolation insulating film 12) are applied. Thereby, as shown in FIG. 9A, a metal gate 24a is formed on the silicon oxide film 13A.

  Next, as shown in FIG. 9B, a polysilicon film 24B having a film thickness equal to or greater than that of the polysilicon gate 24b, for example, about 1500 to 2000 mm, is deposited on the SOI layer 11c and the metal by, for example, a CVD method. It is formed on the gate 24a. This polysilicon film 24B is patterned into a polysilicon gate 24b in a later step. Therefore, the polysilicon film 24B has conductivity by including an impurity having n-type conductivity, for example.

  Next, the polysilicon film 24B is polished to such an extent that the upper surface of the metal gate 24a is exposed by, for example, a CMP method. Thereby, as shown in FIG. 10A, the polysilicon film 24B is thinned into a polysilicon film 24C having the same film thickness as the polysilicon gate 24b.

  Next, a predetermined resist solution is spin-coated on the polysilicon film 24C and the metal gate 24a, and a region where the gate electrode 24 is formed on the polysilicon film 24C and the metal gate 24a through an existing photolithography process. A resist pattern R22 is formed thereon. Subsequently, by using the resist pattern R22 as a mask, the exposed polysilicon film 24C and silicon oxide film 13A are etched to pattern the polysilicon film 24C into a polysilicon gate 24b as shown in FIG. 10B. At the same time, the gate insulating film 13 is formed under the gate electrode 24 composed of the metal gate 24a and the polysilicon gate 24b.

Next, a silicon oxide film 205 having a thickness of, for example, about 100 mm is formed on the exposed SOI layer 11c and the gate electrode 24 by, eg, CVD. Subsequently, as shown in FIG. 11, for example, arsenic ions or phosphorus ions, which are n-type impurities, are implanted at an acceleration of, for example, about 10 KeV from the silicon oxide film 205, so that the regions other than those below the gate electrode 24 in the SOI layer 11 c. A drain region 15d and a source region 15s having an impurity concentration of, for example, about 1 × 10 ²⁰ to 1 × 10 ²¹ / cm ³ are formed in the region. At this time, the gate electrode 24 functions as a mask at the time of impurity implantation. Therefore, the drain regions 15d and 15s are formed in a pair of regions sandwiching the bottom of the gate electrode 24 in a self-aligning manner. Note that the silicon oxide film 205 formed on the SOI layer 11c functions as a mask for reducing damage to the SOI layer 11c during impurity implantation. Also, the implanted impurities are diffused. Further, after forming the drain region 15d and the source region 15s, the silicon oxide film 205 is removed.

  Through the steps as described above, the SOI-MOSFET 2 according to this embodiment as shown in FIG. 6 can be manufactured.

As described above, the SOI-MOSFET 2 according to the present embodiment has the support substrate 11, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b. On the SOI layer 11c, the SOI substrate 11, the high concentration diffusion region 17c formed in the support substrate 11a, the high concentration diffusion region 17d formed in a region deeper than the high concentration diffusion region 17c of the support substrate 11, and The gate electrode 24 formed on the high concentration diffusion region 17c, the drain region 15d formed in the region on the high concentration diffusion region 17d in the SOI layer 11c, and the drain region 15d across the gate electrode 24 in the SOI layer 11c. And a source region 15s formed in the opposite region.

  In addition, the method for manufacturing the SOI-MOSFET 2 according to the present embodiment includes an SOI substrate 11 having a support substrate 11a, a BOX layer 11b formed on the support substrate 11a, and an SOI layer 11c formed on the BOX layer 11b. The high concentration diffusion region 17c is formed in the support substrate 11a, the high concentration diffusion region 17d is formed in a region deeper than the high concentration diffusion region 17c of the support substrate 11a, and the high concentration diffusion region is formed on the SOI layer 11c. A gate electrode 24 is formed on 17c, a drain region 15d is formed in a region on the high concentration diffusion region 17d in the SOI layer 11c, and in a region opposite to the drain region 15d across the gate electrode 24 in the SOI layer 11c. A source region 15s is formed.

  As described above, the high concentration diffusion regions 17d and 17c are formed in the regions below the drain region 15d and the gate electrode 24 in the support substrate 11a, respectively. Acts on the electric field extending from the drain region 15d, so that the electric field extending from the drain region 15d passes through the BOX layer 11b below the SOI layer 11c to form the SOI layer 11c under the gate electrode 24, that is, a channel during operation. It is possible to suppress the penetration to the region (body region 16). That is, the parasitic capacitance formed between the drain region 15d and the body region 16 can be reduced. Thereby, for example, even when the BOX layer 11b in the SOI substrate 11 is thickened, the parasitic capacitance formed between the drain region 15d and the body region 16 increases, or the subthreshold leakage current increases due to the DIBL effect. The problem of doing so can be avoided.

  In this embodiment, the high concentration diffusion region 17d formed under the drain region 15d is deeper than the high concentration diffusion region 17c formed under the gate electrode 24, in other words, a region deeper to some extent from the upper surface of the support substrate 11a. Forming. As a result, as in the first embodiment, it is possible to suppress an increase in junction capacitance formed between the drain region 15d and the high concentration diffusion region 17d. As a result, since the load capacitance CL can be reduced, it is possible to increase the operation speed and reduce the power consumption, and to reduce the signal transmission loss in the high frequency operation.

  Further, in this example, as in Example 1, it was formed in a region deeper than the high concentration diffusion region 17c of the support substrate 11a and on the opposite side to the high concentration diffusion region 17d across the lower portion of the high concentration diffusion region 17c. A high concentration diffusion region 17s is further provided, and a source region 15s is formed in a region on the high concentration diffusion region 17s in the SOI layer 11c. As a result, the same effects as those of the first embodiment can be obtained.

  Further, in the present embodiment, as in the first embodiment, the high concentration diffusion region 17c is formed on the upper surface or the surface of the support substrate 11a. As a result, the same effects as those of the first embodiment can be obtained.

  In this embodiment, the impurity concentration of the SOI layer 11c, that is, the body region 16, is the same as the impurity concentration of the support substrate 11a or substantially the same as the impurity concentration of the support substrate 11a. As a result, the same effects as those of the first embodiment can be obtained.

  Further, in this embodiment, the gate electrode 24 is formed on the metal gate 24a formed on a part of the high concentration diffusion region 17c, on the side surface of the metal gate 24a on the high concentration diffusion region 17c, and the metal gate. And a polysilicon gate 24b having a conductivity lower than that of 24a.

  As described above, the gate electrode 24 is composed of two types of gates (metal gate 24a and polysilicon gate 24b) having different dielectric constants, so that the gate electrode 24 of the gate having a high dielectric constant (in this example, the metal gate 24a) is used. By controlling the length, the threshold voltage Vt of the SOI-MOSFET 2 can be controlled. Thereby, for example, even when the impurity concentration of the body region 16 is lowered, it is possible to prevent a problem that the subthreshold leakage current is increased due to a decrease in the threshold voltage Vt of the SOI-MOSFET 2.

  Next, Example 3 of the present invention will be described in detail with reference to the drawings. In the following description, the same components as those in the first embodiment or the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the configuration not specifically mentioned is the same as that of the first embodiment or the second embodiment. Further, in this embodiment, the configuration of the SOI-MOSFET 2 exemplified in the second embodiment is cited as the basic configuration of the semiconductor device. However, the present invention is not limited to this, and the configuration of the SOI-MOSFET 1 exemplified in the first embodiment. It is also possible to use. In this case, the gate electrode 24 is replaced with the gate electrode 14.

Configuration FIG. 12 is a cross-sectional view showing a schematic configuration of an SOI-MOSFET 3 which is a semiconductor device according to the present embodiment. Note that FIG. 12 shows a cross-sectional structure when the SOI-MOSFET 3 is cut along a plane perpendicular to the gate width direction, as in FIGS.

  As shown in FIG. 12, the SOI-MOSFET 3 includes an SOI substrate 11 including a support substrate 11a, a BOX layer 11b formed on the support substrate 11a, and an SOI layer 11c formed on the BOX layer 11b, and a support substrate 11a. The three high-concentration diffusion regions 17c, 17d, and 17s formed on the element isolation insulating film 12 that partitions the SOI layer 11c into a plurality of element formation regions (also referred to as active regions), and the element formation region of the SOI layer 11c The formed drain region 15d and source region 15s, drain region 15d and source region 15s, and lightly doped regions 35d and 35s extending to a part under the gate electrode 14, and lightly doped regions 35d and 35s (drain) The body region 36 sandwiched between the region 15d and the source region 15s) and on the body region 36 And a gate insulating film 13 made, a gate electrode 24 formed on the gate insulating film 13, the side wall 37 formed on both sides of the gate electrode 24 a on the gate insulating film 13. That is, in this embodiment, the side walls 37 are formed on both sides of the gate electrode 24 in the second embodiment, and the low concentration diffusion region (from the drain region 15d to the bottom of the gate electrode 24 via the side wall 37). 35d and a low-concentration diffusion region (also referred to as LDD) 35s extending from the source region 15s to the bottom of the gate electrode 24 through the sidewall 37. Accordingly, the body region 16 in the first or second embodiment is replaced with the body region 36.

  The sidewall 37 is an insulating film formed by, for example, anisotropic etching of a silicon oxide film. The film thickness along the gate length direction can be about 800 mm, for example. By providing such a sidewall 37, the distance from the gate electrode 24 to the drain region 15d and the distance from the gate electrode 24 to the source region 15s are defined.

In the low-concentration diffusion region 35d extending from the drain region 15d to a part of the region under the gate electrode through the side wall 37, for example, n-type impurities (for example, arsenic ions or phosphorus ions) are, for example, 1 × 10 ¹⁹ / cm. It can be formed by injecting and diffusing to a concentration of about ³ . A region where the drain region 15d and source region 15s and the low concentration diffusion regions 35d and 35s in the active region of the SOI layer 11c are not formed becomes a region where a channel is formed during operation, that is, the body region 36. Therefore, the body region 36 according to this embodiment is a non-doped region or a region having a relatively low impurity concentration.

  By having the configuration as described above, the SOI-MOSFET 3 according to the present embodiment can have higher withstand voltage characteristics than the SOI-MOSFET 1 or 2 according to the first or second embodiment. Since other configurations are the same as those of the first embodiment, detailed description thereof is omitted here.

Manufacturing Method Next, a manufacturing method of the SOI-MOSFET 3 according to the present embodiment will be described in detail with reference to the drawings. 13 and 14 are process diagrams showing a method for manufacturing the SOI-MOSFET 3 according to this embodiment. In the manufacturing method according to the present embodiment, the steps until the gate insulating film 13 and the gate electrode 24 are formed on the SOI layer 11c are the same as those in FIG. 2A to FIG. 8 is the same as the process described with reference to FIG. 8A to FIG. 10B, and detailed description thereof is omitted here.

In this manufacturing method, first, as described in Embodiment 1 with reference to FIGS. 2A to 3A, the high-concentration diffusion region 17c is formed in the support substrate 11a, and then in Embodiment 2, FIG. As described with reference to FIGS. 10A to 10B, the gate insulating film 13 and the gate electrode 24 are formed on the SOI layer 11c. Subsequently, a silicon oxide film 305 having a thickness of, for example, about 100 mm is formed on the exposed SOI layer 11c and the gate electrode 24 by, for example, a CVD method. Subsequently, as shown in FIG. 13A, for example, arsenic ions or phosphorus ions, which are n-type impurities, are implanted from the silicon oxide film 305 by accelerating them to, for example, about 5 KeV, so that the gate electrode 24 in the SOI layer 11c is implanted. Low concentration diffusion regions 35d and 35s having an impurity concentration of, for example, about 1 × 10 ¹⁹ / cm ³ are formed in regions other than the lower region. At this time, the gate electrode 24 functions as a mask at the time of impurity implantation. For this reason, the low concentration diffusion regions 35d and 35s are formed in a pair of regions sandwiching the gate electrode 24 under the self-alignment. Note that the silicon oxide film 305 formed over the SOI layer 11c functions as a mask for reducing damage to the SOI layer 11c during impurity implantation. Also, the implanted impurities are diffused.

  Next, after removing the silicon oxide film 205, as shown in FIG. 13B, the gate electrode and the SOI layer 11c on which the silicon oxide film 37A having a film thickness of, for example, about 1000 mm or more is exposed by, eg, CVD. 24 is formed.

  Next, the existing anisotropic etching is performed to pattern the silicon oxide film 37A formed on the SOI layer 11c and the gate electrode 24. As a result, as shown in FIG. 14A, sidewalls 37 having a thickness in the gate length direction of, for example, about 800 mm are formed on both sides of the gate electrode 24.

Next, the silicon oxide film 306 having a thickness of, for example, about 100 mm is formed on the exposed SOI layer 11c, the sidewall 37, and the gate electrode 24 by, for example, CVD. Subsequently, as shown in FIG. 14B, for example, arsenic ions or phosphorus ions, which are n-type impurities, are implanted from the silicon oxide film 306 by accelerating them to about 10 KeV, for example, so that the gate electrode 24 in the SOI layer 11c is implanted. In addition, a drain region 15d and a source region 15s having an impurity concentration of, for example, about 1 × 10 ²⁰ / cm ³ to 1 × 10 ²¹ / cm ³ are formed in a region other than under the sidewall 37. At this time, the gate electrode 24 and the sidewall 37 function as a mask at the time of impurity implantation. For this reason, the drain region 15d and the source region 15s are formed in a pair of regions sandwiching the gate electrode 24 and the side wall 37 under self-alignment. Note that the silicon oxide film 306 formed over the SOI layer 11c functions as a mask for reducing damage to the SOI layer 11c during impurity implantation. Also, the implanted impurities are diffused. Further, after forming the drain region 15d and the source region 15s, the silicon oxide film 306 is removed.

  Through the steps described above, the SOI-MOSFET 3 according to the present embodiment as shown in FIG. 12 can be manufactured.

As described above, the SOI-MOSFET 3 according to the present embodiment has the support substrate 11, the BOX layer 11b formed on the support substrate 11a, and the SOI layer 11c formed on the BOX layer 11b. On the SOI layer 11c, the SOI substrate 11, the high concentration diffusion region 17c formed in the support substrate 11a, the high concentration diffusion region 17d formed in a region deeper than the high concentration diffusion region 17c of the support substrate 11, and The gate electrode 24 formed on the high concentration diffusion region 17c, the drain region 15d formed in the region on the high concentration diffusion region 17d in the SOI layer 11c, and the drain region 15d across the gate electrode 24 in the SOI layer 11c. And a source region 15s formed in the opposite region.

  In addition, the method for manufacturing the SOI-MOSFET 3 according to the present embodiment includes an SOI substrate 11 having a support substrate 11a, a BOX layer 11b formed on the support substrate 11a, and an SOI layer 11c formed on the BOX layer 11b. The high concentration diffusion region 17c is formed in the support substrate 11a, the high concentration diffusion region 17d is formed in a region deeper than the high concentration diffusion region 17c of the support substrate 11a, and the high concentration diffusion region is formed on the SOI layer 11c. A gate electrode 24 is formed on 17c, a drain region 15d is formed in a region on the high concentration diffusion region 17d in the SOI layer 11c, and in a region opposite to the drain region 15d across the gate electrode 24 in the SOI layer 11c. A source region 15s is formed.

  In this manner, by forming the high concentration diffusion regions 17d and 17c in the regions below the drain region 15d and the gate electrode 24 in the support substrate 11a, as in the first and second embodiments, these high concentration diffusion regions 17d. And 17c act on the electric field extending from the drain region 15d, the electric field direction line extending from the drain region 15d passes through the BOX layer 11b below the SOI layer 11c and the SOI layer 11c under the gate electrode 24, that is, the channel in operation. It is possible to suppress penetration into the formed region (body region 36). That is, the parasitic capacitance formed between the drain region 15d and the body region 36 can be reduced. Thereby, for example, even when the BOX layer 11b in the SOI substrate 11 is thickened, the parasitic capacitance formed between the drain region 15d and the body region 36 increases, or the subthreshold leakage current increases due to the DIBL effect. The problem of doing so can be avoided.

  In this embodiment, the high concentration diffusion region 17d formed under the drain region 15d is deeper than the high concentration diffusion region 17c formed under the gate electrode 24, in other words, a region deeper to some extent from the upper surface of the support substrate 11a. Forming. As a result, as in the first and second embodiments, it is possible to suppress an increase in junction capacitance formed between the drain region 15d and the high concentration diffusion region 17d. As a result, since the load capacitance CL can be reduced, it is possible to increase the operation speed and reduce the power consumption, and to reduce the signal transmission loss in the high frequency operation.

  Further, in this embodiment, similarly to the first and second embodiments, the support substrate 11a is formed in a region deeper than the high concentration diffusion region 17c and opposite to the high concentration diffusion region 17d with the lower portion of the high concentration diffusion region 17c interposed therebetween. The source region 15s is formed in a region on the high concentration diffusion region 17s in the SOI layer 11c. As a result, the same effects as those of the first and second embodiments can be obtained.

  In the present embodiment, as in the first and second embodiments, the high-concentration diffusion region 17c is formed on or on the support substrate 11a. As a result, the same effects as those of the first and second embodiments can be obtained.

  In the present embodiment, as in the first and second embodiments, the impurity concentration of the SOI layer 11c, that is, the body region 36 is set to the same concentration as the impurity concentration of the support substrate 11a or substantially the same as the impurity concentration of the support substrate 11a. Yes. As a result, the same effects as those of the first and second embodiments can be obtained.

  Further, in the present embodiment, as in the second embodiment, the gate electrode 24 includes a metal gate 24a formed in a part on the high concentration diffusion region 17c, and the metal gate 24a on the high concentration diffusion region 17c. And a polysilicon gate 24b formed on the side surface and having lower conductivity than the metal gate 24a. Thereby, it is possible to achieve the same effect as in the second embodiment.

  Further, the SOI-MOSFET 3 according to the present embodiment includes low-concentration diffusion regions 35d and 35s having a lower impurity concentration than the drain region 15d and the source region 15s, which are formed in a pair of regions sandwiching the gate electrode 24 under the SOI layer 11c. And a side wall 37 formed on the side surface of the gate electrode 24, the drain region 15 d is formed on the high concentration diffusion region 17 d and in a region other than under the side wall 37, and the source region 15 s is high concentration diffusion. It is formed in a region above the region 17 s and other than under the sidewall 37.

  Thus, the side walls 37 are formed on both sides of the gate electrode 24, and the low concentration diffusion regions 35d or 35s are respectively formed below the side walls 37, that is, between the gate electrode 24 and the drain region 15d or the source region 15s. As a result, the breakdown voltage characteristic of the SOI-MOSFET 3 can be made higher than that of the SOI-MOSFET 1 or 2 according to the first or second embodiment, for example.

  Further, in this embodiment, not only under the low concentration diffusion regions 35d and 35s, but also under the gate electrode 24 and the drain region 15d (which may include the source region 15s), the high concentration diffusion regions 17c and 17d (including 17s). Therefore, it is possible to more effectively suppress the line extending in the direction of the electric field extending from the drain region 15d from passing through the BOX layer 11b below the SOI layer 11c to the body region 36. It becomes.

  In the present embodiment, the case where the SOI-MOSFET 2 according to the second embodiment is cited as described above is exemplified, but the present invention is not limited to this, and for example, the SOI-MOSFET 1 according to the first embodiment can also be cited. It is.

  In addition, the first to third embodiments described above are merely examples for carrying out the present invention, and the present invention is not limited to these. Various modifications of these embodiments are within the scope of the present invention. It is obvious from the above description that various other embodiments are possible within the scope of the present invention.

It is a figure which shows schematic structure of SOI-MOSFET which is a semiconductor device by Example 1 of this invention, and is a figure which shows the cross-section when a SOI-MOSFET is cut | disconnected by the surface perpendicular | vertical to a gate width direction. It is a process diagram which shows the manufacturing method of SOI-MOSFET by Example 1, 2, or 3 of this invention (1). It is a process diagram which shows the manufacturing method of SOI-MOSFET by Example 1, 2, or 3 of this invention (2). It is a process diagram which shows the manufacturing method of SOI-MOSFET by Example 1 of this invention (3). It is a process diagram which shows the manufacturing method of SOI-MOSFET by Example 1 of this invention (4). It is a figure which shows schematic structure of SOI-MOSFET which is a semiconductor device by Example 2 of this invention, and is a figure which shows the cross-section when a SOI-MOSFET is cut | disconnected by the surface perpendicular | vertical to a gate width direction. It is a process figure which shows the manufacturing method of SOI-MOSFET by Example 2 or 3 of this invention (1). It is a process figure which shows the manufacturing method of SOI-MOSFET by Example 2 or 3 of this invention (2). It is a process figure which shows the manufacturing method of SOI-MOSFET by Example 2 or 3 of this invention (3). It is a process figure which shows the manufacturing method of SOI-MOSFET by Example 2 or 3 of this invention (4). It is a process figure which shows the manufacturing method of SOI-MOSFET by Example 2 of this invention (5). It is a figure which shows schematic structure of SOI-MOSFET which is a semiconductor device by Example 3 of this invention, and is a figure which shows the cross-section when a SOI-MOSFET is cut | disconnected by the surface perpendicular | vertical to a gate width direction. It is a process diagram which shows the manufacturing method of SOI-MOSFET by Example 3 of this invention (1). It is a process diagram which shows the manufacturing method of SOI-MOSFET by Example 3 of this invention (2).

Explanation of symbols

1, 2, 3 SOI-MOSFET
11 SOI substrate 11a Support substrate 11b BOX layer 11c SOI layer 12 Element isolation insulating film 13 Gate insulating film 13A Silicon oxide film 14, 24 Gate electrode 14A, 24A Conductive film 15d Drain region 15s Source region 16, 36 Body region 16A, 16B Silicon Thin film 17c, 17d, 17s High concentration diffusion region 24a Metal gate 24b Polysilicon gate 24B, 24C Polysilicon film 35d, 35s Low concentration diffusion region 37 Side wall 37A Silicon oxide film 101, 103, 105, 205, 305, 306 Silicon oxide Film 102, 104, 204 Silicon nitride film R11, R21, R22 Resist pattern

Claims (18)

An SOI substrate having a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer;
A first diffusion region formed on the support substrate;
A second diffusion region formed in a region deeper than the first diffusion region of the support substrate;
A gate electrode formed on the semiconductor layer and on the first diffusion region;
A drain region formed in a region on the second diffusion region in the semiconductor layer;
And a source region formed in a region opposite to the drain region across the gate electrode in the semiconductor layer. A third diffusion region formed in a region deeper than the first diffusion region of the support substrate and opposite to the second diffusion region across the first diffusion region;
The semiconductor device according to claim 1, wherein the source region is formed in a region on the third diffusion region in the semiconductor layer. A low diffusion region having a lower impurity concentration than the drain region and the source region, formed in a pair of regions sandwiching the gate electrode under the semiconductor layer;
A sidewall formed on a side surface of the gate electrode;
3. The semiconductor device according to claim 1, wherein the drain region is formed in a region above the second diffusion region and other than under the sidewall. A low diffusion region having a lower impurity concentration than the drain region and the source region, formed in a pair of regions sandwiching the gate electrode under the semiconductor layer;
A sidewall formed on a side surface of the gate electrode;
The drain region is formed on the second diffusion region and in a region other than the side wall;
The semiconductor device according to claim 2, wherein the source region is formed in a region on the third diffusion region and other than under the sidewall.   5. The semiconductor device according to claim 1, wherein the first and second diffusion regions include an impurity having a conductivity type opposite to that of the impurity included in the drain region. 6.   5. The semiconductor device according to claim 2, wherein the first to third diffusion regions contain impurities having a conductivity type opposite to that of the impurities contained in the drain region or the source region.   The semiconductor device according to claim 1, wherein the first diffusion region is formed on an upper surface or a surface of the support substrate.   The gate electrode is formed on a part of the first diffusion region on the first diffusion region, on the first diffusion region on the side surface of the first conductor layer, and from the first conductor layer. 8. The semiconductor device according to claim 1, further comprising a second conductor film having low conductivity. The first conductor film is a metal film;
9. The semiconductor device according to claim 8, wherein the second conductor film is a polysilicon film having conductivity by containing a predetermined impurity. Preparing an SOI substrate having a support substrate, an insulating layer formed on the support substrate, and a semiconductor layer formed on the insulating layer;
Forming a first diffusion region on the support substrate;
Forming a second diffusion region in a region deeper than the first diffusion region of the support substrate;
Forming a gate electrode on the semiconductor layer and on the first diffusion region;
Forming a drain region in a region on the second diffusion region in the semiconductor layer;
Forming a source region in a region opposite to the drain region across the gate electrode in the semiconductor layer. Forming a third diffusion region in a region deeper than the first diffusion region of the support substrate and opposite to the second diffusion region across the first diffusion region;
The method of manufacturing a semiconductor device according to claim 10, wherein the source region is formed in a region on the third diffusion region in the semiconductor layer. Forming a low diffusion region having an impurity concentration lower than that of the drain region and the source region in a pair of regions sandwiching the gate electrode under the semiconductor layer;
And further forming a sidewall on the side surface of the gate electrode,
12. The method of manufacturing a semiconductor device according to claim 10, wherein the drain region is formed in a region above the second diffusion region and other than under the sidewall. Forming a low diffusion region having an impurity concentration lower than that of the drain region and the source region in a pair of regions sandwiching the gate electrode under the semiconductor layer;
And further forming a sidewall on the side surface of the gate electrode,
The drain region is formed on the second diffusion region and in a region other than the side wall;
12. The method of manufacturing a semiconductor device according to claim 11, wherein the source region is formed in a region on the third diffusion region and other than under the sidewall.   The first and second diffusion regions are formed by diffusing an impurity having a conductivity type opposite to that of the impurity diffused in the drain region. The manufacturing method of the semiconductor device of description.   14. The first to third diffusion regions are formed by diffusing an impurity having a conductivity type opposite to an impurity diffused in the drain region or the source region. A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 10, wherein the first diffusion region is formed on an upper surface or a surface of the support substrate.   The gate electrode is formed on a part of the first diffusion region on the first diffusion region, on the first diffusion region on the side surface of the first conductor layer, and from the first conductor layer. 17. The method of manufacturing a semiconductor device according to claim 10, further comprising: a second conductor film having a low conductivity. The first conductor film is a metal film;
18. The method of manufacturing a semiconductor device according to claim 17, wherein the second conductor film is a polysilicon film having conductivity by containing a predetermined impurity.

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