JP2007180421A - Multilayer circuit board and manufacturing method therefor - Google Patents

Multilayer circuit board and manufacturing method therefor Download PDF

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JP2007180421A
JP2007180421A JP2005379534A JP2005379534A JP2007180421A JP 2007180421 A JP2007180421 A JP 2007180421A JP 2005379534 A JP2005379534 A JP 2005379534A JP 2005379534 A JP2005379534 A JP 2005379534A JP 2007180421 A JP2007180421 A JP 2007180421A
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circuit board
surface region
multilayer circuit
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Mikihiko Ishibashi
幹彦 石橋
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Sumitomo Bakelite Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a multilayer circuit board and multilayer circuit board, where complex processes are not included in the manufacturing process, and the preparation and management of a design tool are easy at the designing stage. <P>SOLUTION: The manufacturing method of the multilayer circuit board 600 includes a process of preparing a substrate 102 and a double-sided circuit board, obtained by forming a first conductor and a second conductor on both of the sides of the substrate 102; a process of previously layering an interlayer adhesive 108 at a predetermined position of the double-sided circuit board; a process of folding the double-sided circuit board one or more times to make the multilayer circuit board, and thereafter connecting the first conductor and the second conductor through the interlayer adhesive 108; and a process of removing the periphery of the multilayer circuit board. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、多層回路板の製造方法および多層回路板に関するものである。   The present invention relates to a method for manufacturing a multilayer circuit board and a multilayer circuit board.

近年の携帯端末をはじめとする電子機器の発展に伴い、高機能化、小型軽量化の要求がますます高まっており、これに伴って、プリント配線板も高密度配線で極薄の多層化の要求が高まってきている。多層プリント配線板は大きく別けて、貫通スルーホールめっき方式とビルドアップ方式の2つに分類され、さらにビルドアップ方式の中には逐次積層をおこなうシーケンシャルビルドアップ方式と一括で積層を行うパラレルビルドアップ方式に分類される。   With the recent development of electronic devices such as mobile terminals, there is an increasing demand for higher functionality, smaller size and lighter weight. With this, printed wiring boards are becoming increasingly thin and multi-layered with high-density wiring. There is an increasing demand. Multilayer printed wiring boards are broadly divided into two types, through-through-hole plating and build-up methods. In addition, build-up methods include sequential build-up method, which performs sequential lamination, and parallel build-up, which performs lamination in a batch. Classified into methods.

貫通スルーホールめっき方式は、あらかじめパターンニングしておいた両面配線板または片面配線板を内層回路として接着層を介して一体化した後、ドリルで貫通穴をあけてスルーホールめっきをおこない各導体層を電気的に導通させる方法である。
また、シーケンシャルビルドアップ方式は、前記のスルーホールめっき方式で作製した多層配線板をコア基板とし、その表層に絶縁層を形成し、次いでブラインドビアを介して最外層とコア基板を導通した後、最外層に配線回路を形成する一連の工程を繰り返すことにより逐次積層していく方法などがある(例えば特許文献1)。
The through-through-hole plating method is a method in which a double-sided wiring board or single-sided wiring board that has been patterned in advance is integrated as an inner layer circuit via an adhesive layer, then through holes are drilled with a drill to perform through-hole plating. Is a method of electrically connecting the two.
In addition, the sequential buildup method uses the multilayer wiring board produced by the through-hole plating method as a core substrate, forms an insulating layer on the surface layer, and then conducts the outermost layer and the core substrate through blind vias, There is a method of sequentially laminating a series of processes for forming a wiring circuit in the outermost layer (for example, Patent Document 1).

パラレルビルドアップ方式は、回路成形した絶縁基材にブラインドビアを形成しビア内をめっきまたは導電ペーストで充填したものを各層毎に用意し、これらを位置決めして積み重ね、熱圧により一括で積層する方法などがある(例えば特許文献2)。
しかしこれらの多層配線板は、何れの方式で行なうにしても、各層毎に別々に回路形成する工程が必要でり、片面配線板や両面配線板に比べ多大な工数が必要でり、また、製造工程も層数に比例して複雑になっていった。
さらに、設計段階においても、各層毎にそれぞれに配線パターンデータ、穴あけデータ、位置決めガイド穴データ、外形加工用データ、絶縁マスクデータなど多くのデータが必要であり、その作成および管理に多大な工数が必要であった。
In the parallel buildup method, a blind via is formed on a circuit-molded insulating base and the inside of the via is filled with plating or conductive paste is prepared for each layer, and these are positioned and stacked, and then laminated together by hot pressure. There are methods (for example, Patent Document 2).
However, these multi-layer wiring boards require a process for forming a circuit separately for each layer regardless of which method is used, and require a large number of man-hours compared to single-sided wiring boards and double-sided wiring boards. The manufacturing process has become more complex in proportion to the number of layers.
Furthermore, at the design stage, each layer requires a lot of data such as wiring pattern data, drilling data, positioning guide hole data, outline processing data, and insulation mask data. It was necessary.

特開平8−125344号公報JP-A-8-125344 特開平11−54934号公報JP 11-54934 A

本発明は、上記事情に鑑みてなされたものであり、製造工程においては、複雑な工程がなく、また、設計段階においては、設計ツールの作成および管理が容易な、多層回路板の製造方法および多層回路板を提供することにある。   The present invention has been made in view of the above circumstances, and there is no complicated process in the manufacturing process, and in the design stage, a method for manufacturing a multilayer circuit board that is easy to create and manage a design tool and It is to provide a multilayer circuit board.

本発明の多層回路板の製造方法は、基材と、前記基材の両面側にそれぞれ第1導電部と第2導電部とが形成された両面回路基板を、少なくとも一回折り畳んで多層回路基板としたのち、前記多層回路基板の周辺部を除去する工程を含むことを特徴とする。   The method for producing a multilayer circuit board according to the present invention includes a multilayer circuit board obtained by folding at least one time a base material and a double-sided circuit board in which a first conductive part and a second conductive part are formed on both sides of the base material, respectively. Thereafter, the method includes a step of removing a peripheral portion of the multilayer circuit board.

この多層回路基板の製造方法では、両面回路基板を所定の位置で折り畳んでいくことにより、折り畳み回数に両面の二層を掛けた層数、例えば、1回の折り畳みでは、1x2+2=4となり、4層が、また、二回の折り畳みでは6層の多層回路基板を得ることが出来る。このように、多層回路基板を複雑な工程を経ることなく、また、多大な設計ツールを使うことなく得ることが出来る。
本発明において、折り畳み工程は種々の形態をとることができる。
たとえば、
前記基材は、矩形形状の第1面領域と、前記第1面領域の一つの辺を共有して隣接する矩形形状の第2面領域とを含み、
前記両面回路基板を折り畳む工程は、前記辺を折り返し部として前記基材を折り畳み、第1面領域および第2面領域を重ね合わせ対向させる工程を含む構成としてもよい。
また、前記基材は、矩形形状の第1面領域と、前記第1面領域の一辺を共有して隣接する矩形形状の第2面領域と、前記第1面領域の他辺を共有して隣接する矩形形状の第3面領域とを含み、
前記両面回路基板を折り畳む工程は、
前記一辺を折り返し部として前記基材を折り畳み、第1面領域および第2面領域を重ね合わせ対向させる第1折り畳み工程と、
前記他辺を折り返し部として前記基材をさらに折り畳み、第1面領域、第2面領域および第3面領域を重ね合わせる第2折り畳み工程と、
を含む構成としてもよい。
上記のようにすれば、基材を有効利用し、多層基板を簡便な工程で効率的に作製することができる。
In this multilayer circuit board manufacturing method, by folding the double-sided circuit board at a predetermined position, the number of folding times is obtained by multiplying two layers on both sides, for example, 1 × 2 + 2 = 4 in one folding. A multilayer circuit board with 6 layers can be obtained by folding twice. Thus, a multilayer circuit board can be obtained without going through complicated processes and without using a great number of design tools.
In the present invention, the folding step can take various forms.
For example,
The base material includes a rectangular first surface region, and a rectangular second surface region adjacent to and sharing one side of the first surface region,
The step of folding the double-sided circuit board may include a step of folding the base material with the side as a folded portion and overlapping the first surface region and the second surface region.
Further, the base material shares a rectangular first surface region, a rectangular second surface region sharing one side of the first surface region, and the other side of the first surface region. An adjacent rectangular third surface region,
The step of folding the double-sided circuit board includes:
A first folding step in which the base is folded with the one side as a folded portion, and the first surface region and the second surface region are overlapped with each other;
A second folding step of further folding the base material with the other side as a folded portion, and overlapping the first surface region, the second surface region, and the third surface region;
It is good also as a structure containing.
If it does as mentioned above, a base material can be used effectively and a multilayer substrate can be produced efficiently by a simple process.

本発明により、製造工程においては、複雑な工程がなく、また、設計段階においては、設計ツールの作成および管理が容易な、多層回路板の製造方法および多層回路板を提供することができる。   According to the present invention, it is possible to provide a method for manufacturing a multilayer circuit board and a multilayer circuit board that are free from complicated processes in the manufacturing process and that are easy to create and manage a design tool in the design stage.

以下、本発明の実施形態について、図面を用いて説明する。なお、すべての図面において、共通する構成要素には同一符号を付し、以下の説明において詳細な説明を適宜省略する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, common constituent elements are denoted by the same reference numerals, and detailed description thereof will be appropriately omitted in the following description.

本実施形態に係る多層回路板の製造方法は、
基材と、前記基材の少なくとも一方の面に設けられた第1導電部および第2導電部とを備える両面回路基板を用意する工程と、
前記一方の面に設けられた前記第1導電部および前記第2導電部のうち、少なくとも一方を層間接着剤で覆う工程と、
前記両面回路基板を少なくとも一回折り畳み、前記層間接着剤を介して前記第1導電部の設けられた第1面領域と前記第2導電部の設けられた第2面領域とを対向させた状態とする工程と、
前記状態で加熱プレスすることにより、前記第1導電部と前記第2導電部に挟まれた部分にある層間接着剤を溶融除去し、前記第1導電部と前記第2導電部とを電気的に接続させ、多層回路基板を形成する工程と、
前記多層回路基板の周辺部を除去して多層回路板を得る工程と
を含むものである。
ここで、基材は、矩形形状の第1面領域と、第1面領域の一辺を共有して隣接する矩形形状の第2面領域と、第1面領域の他辺を共有して隣接する矩形形状の第3面領域とを含む。そして、両面回路基板を折り畳む工程は、(i)前記一辺を折り返し部として基材を折り畳み、第1面領域および第2面領域を重ね合わせ対向させる第1折り畳み工程と、(ii)前記他辺を折り返し部として基材をさらに折り畳み、第1面領域、第2面領域および第3面領域を重ね合わせる第2折り畳み工程とを含む。
すなわち、本実施形態に係る多層回路板600の製造方法は、図1および図2に示すように、基材102と、基材102の両面側に第1導電部105と第2導電部115とが形成された両面回路基板109を用意する工程と、両面回路基板109の、所定の位置に予め層間接着剤108を積層する工程と、両面回路基板109を、少なくとも一回折り畳んで多層回路基板550としたのち、層間接着剤108を介して、第1導電部105と第2導電部115を接続する工程と、多層回路基板550の周辺部を除去する工程とを含む。
The method for manufacturing a multilayer circuit board according to this embodiment is as follows.
Preparing a double-sided circuit board comprising a base material and a first conductive part and a second conductive part provided on at least one surface of the base material;
Covering at least one of the first conductive part and the second conductive part provided on the one surface with an interlayer adhesive;
A state in which the double-sided circuit board is folded at least once, and the first surface region provided with the first conductive part and the second surface region provided with the second conductive part are opposed to each other through the interlayer adhesive. And a process of
By heat-pressing in the state, the interlayer adhesive in the portion sandwiched between the first conductive portion and the second conductive portion is melted and removed, and the first conductive portion and the second conductive portion are electrically connected. Forming a multilayer circuit board, and
And removing a peripheral portion of the multilayer circuit board to obtain a multilayer circuit board.
Here, the base material is adjacent to the rectangular first surface region, the rectangular second surface region sharing one side of the first surface region, and the other side of the first surface region. And a third surface region having a rectangular shape. The step of folding the double-sided circuit board includes (i) a first folding step in which the base is folded with the one side as a folded portion, and the first surface region and the second surface region are overlapped with each other, and (ii) the other side And a second folding step of further folding the base material with the first surface region, the second surface region, and the third surface region superimposed.
That is, as shown in FIGS. 1 and 2, the method for manufacturing the multilayer circuit board 600 according to the present embodiment includes the base material 102, and the first conductive portion 105 and the second conductive portion 115 on both sides of the base material 102. A step of preparing the double-sided circuit board 109 on which the multilayer circuit board 109 is formed, a step of previously laminating the interlayer adhesive 108 at a predetermined position of the double-sided circuit board 109, and the multilayer circuit board 550 by folding the double-sided circuit board 109 at least once After that, a step of connecting the first conductive portion 105 and the second conductive portion 115 via the interlayer adhesive 108 and a step of removing the peripheral portion of the multilayer circuit board 550 are included.

図3は、本発明の製造方法により得られた多層回路板600の一実施形態の概略構成を示す図である。
多層回路板600は、両面回路基板109が、本実施形態では3構成より形成され6層の多層回路板600となっている。両面回路基板109の層間には層間接着剤108を介して接続されている。また、多層回路板600の最外層は、それぞれ、絶縁被覆107により覆われている。各層間の接続は、両面回路基板109では、基材102を貫通する孔にめっきあるいは導電ペーストなどで埋め込まれたフィルドビアめっき103構造となっている。そして、層間の接続は、第1導電部105と第2導電部115とが、金属被覆層104を介して接続されている。
FIG. 3 is a diagram showing a schematic configuration of an embodiment of a multilayer circuit board 600 obtained by the manufacturing method of the present invention.
In the multilayer circuit board 600, the double-sided circuit board 109 is formed of three configurations in the present embodiment to form a six-layer multilayer circuit board 600. An interlayer adhesive 108 is connected between the layers of the double-sided circuit board 109. Further, the outermost layers of the multilayer circuit board 600 are each covered with an insulating coating 107. In the double-sided circuit board 109, the connection between the layers has a filled via plating 103 structure in which a hole penetrating the base material 102 is filled with plating or conductive paste. In connection between the layers, the first conductive portion 105 and the second conductive portion 115 are connected through the metal coating layer 104.

次に、本実施形態に係る多層回路板600の製造方法の一例について図1および図2を用いて説明する。   Next, an example of a method for manufacturing the multilayer circuit board 600 according to the present embodiment will be described with reference to FIGS.

基材102を構成する材料としては、例えば樹脂フィルム基材等が挙げられる。樹脂フィルム基材としては、例えばポリイミド樹脂フィルム、ポリエーテルイミド樹脂フィルム、ポリアミドイミド樹脂フィルム等のポリイミド樹脂系樹脂フィルム、ポリアミド樹脂フィルム等のポリアミド樹脂系フィルム、ポリエステル樹脂フィルム等のポリエステル樹脂系フィルムが挙げられる。このうち、弾性率と耐熱性を向上させる観点から、特にポリイミド樹脂系フィルムが好ましく用いられる。
まず、ポリイミド樹脂フィルムの基材102に金属箔として銅箔101がついた両面積層板を用意する。このとき、基材102に接着剤を用いて銅箔101を貼り合わせたものを使用してもよい。
次に、前記両面積層板に、エッチングやレーザーによって銅箔101を除去し、続いてさらにレーザーや樹脂エッチングにより樹脂を貫通してもう一方の銅箔に至るブラインドビアホールを形成する。このとき、ブラインドビアホールは両面板の片側にのみ形成しても、両側に形成してもよい。さらに、ブランドビアホール内を過マンガン酸塩やプラズマによりデスミア処理をおこない、電解めっきによりフィルドビア103を形成する(図1(a))。このときのフィルドビアは、無電解めっきを用いても、その他導電物質を用いてブラインドビア内を充填してもよい。さらに、必要なフィルドビア上に金属被覆層104をめっき法、ペースト印刷法などを用いて形成する。この場合の金属被覆層104は錫、鉛、銀、銅、亜鉛、ニッケル、ビスマス、アンチモン、インジウム、金の中から選ばれた少なくとも1種類以上の金属で構成された、はんだ金属である。例えば錫系、錫−鉛系、錫−銀系、錫−亜鉛系、錫−ビスマス系、錫−アンチモン、錫−銀−ビスマス系、錫−銅系等があるが、金属元素の組合せや組成に限定されず、最適なものを選択すればよい。金属被覆層104の厚さは、特に限定されないが、好ましくは3〜30μmであり、より好ましくは10〜15μmである。また、はんだ接合時にこの金属被覆層104と銅箔層間で金属拡散による接続劣化を防止する目的で、下地処理としてニッケル等のバリア層を1〜2μm形成しても良い。
Examples of the material constituting the base material 102 include a resin film base material. Examples of the resin film substrate include polyimide resin films such as polyimide resin films, polyetherimide resin films, polyamideimide resin films, polyamide resin films such as polyamide resin films, and polyester resin films such as polyester resin films. Can be mentioned. Of these, a polyimide resin film is particularly preferably used from the viewpoint of improving the elastic modulus and heat resistance.
First, a double-sided laminate having a polyimide resin film substrate 102 with a copper foil 101 as a metal foil is prepared. At this time, a substrate 102 bonded with a copper foil 101 using an adhesive may be used.
Next, the copper foil 101 is removed from the double-sided laminated board by etching or laser, and then a blind via hole penetrating through the resin and reaching the other copper foil is further formed by laser or resin etching. At this time, the blind via hole may be formed only on one side of the double-sided plate or on both sides. Further, desmear treatment is performed in the brand via hole with permanganate or plasma, and a filled via 103 is formed by electrolytic plating (FIG. 1A). The filled via at this time may use electroless plating or may fill the inside of the blind via using another conductive material. Further, the metal coating layer 104 is formed on the necessary filled via using a plating method, a paste printing method, or the like. In this case, the metal coating layer 104 is a solder metal composed of at least one metal selected from tin, lead, silver, copper, zinc, nickel, bismuth, antimony, indium, and gold. Examples include tin, tin-lead, tin-silver, tin-zinc, tin-bismuth, tin-antimony, tin-silver-bismuth, and tin-copper, but combinations and compositions of metal elements It is not limited to this, and an optimal one may be selected. Although the thickness of the metal coating layer 104 is not specifically limited, Preferably it is 3-30 micrometers, More preferably, it is 10-15 micrometers. Further, for the purpose of preventing connection deterioration due to metal diffusion between the metal coating layer 104 and the copper foil layer at the time of soldering, a barrier layer of nickel or the like may be formed as a base treatment by 1 to 2 μm.

つづいて、両面積層板を感光性フォトレジストによりパターンエッチングし、絶縁基材の両面に第2導電部115と第1導電部105を形成する(図1(b))。このとき第1導電部105は円柱、四角柱など、フォトマスクで自由に調節することができる。   Subsequently, the double-sided laminated board is pattern-etched with a photosensitive photoresist to form the second conductive portion 115 and the first conductive portion 105 on both sides of the insulating base (FIG. 1B). At this time, the first conductive portion 105 can be freely adjusted with a photomask such as a cylinder or a quadrangular prism.

次に、前記両面板の必要な部分に絶縁被覆107をおこなう(図1(c))。この絶縁被覆107の箇所はフレックスリジットや多層フレキでの屈曲を必要とする部分や、最終的に最外層にあたる部分である。このときの絶縁被覆107はポリイミドなどの可撓性で耐熱性のある絶縁樹脂と接着剤からなるカバーレイフィルムや、熱硬化型レジストインクや、感光性レジストインク等から選ばれ、前記両面板の片側でも両側でも被覆して差し支えない。   Next, an insulating coating 107 is applied to the necessary part of the double-sided board (FIG. 1C). The location of the insulating coating 107 is a portion that needs to be bent by a flex rigid or a multilayered flex, and finally a portion that corresponds to the outermost layer. The insulating coating 107 at this time is selected from a cover lay film made of a flexible and heat-resistant insulating resin such as polyimide and an adhesive, a thermosetting resist ink, a photosensitive resist ink, and the like. It can be coated on one or both sides.

次に、前記両面板の第1導電部105および導体回路106、基材102上の必要な部分に層間接着剤108(フラックス機能付き接着剤)を形成する(図1(d))。ここで用いるフラックス機能付き接着剤108は、金属表面の清浄化機能、例えば、金属表面に存在する酸化膜の除去機能や、酸化膜の還元機能を有した接着剤であり、第1の好ましい接着剤の構成としては、フェノール性水酸基を有するフェノールノボラック樹脂、クレゾールノボラック樹脂、アルキルフェノールノボラック樹脂、レゾール樹脂、ポリビニルフェノール樹脂などの樹脂(A)と、前記樹脂の硬化剤(B)を含むものである。硬化剤としては、ビスフェノール系、フェノールノボラック系、アルキルフェノールノボラック系、ビフェノール系、ナフトール系、レゾルシノール系などのフェノールベースや、脂肪族、環状脂肪族や不飽和脂肪族などの骨格をベースとしてエポキシ化されたエポキシ樹脂やイソシアネート化合物が挙げられる
第2の好ましい接着剤の構成としては、ビスフェノール系、フェノールノボラック系、アルキルフェノールノボラック系、ビフェノール系、ナフトール系、レゾルシノール系などのフェノールベースや、脂肪族、環状脂肪族や不飽和脂肪族などの骨格をベースとしてエポキシ化されたエポキシ樹脂(C)と、イミダゾール環を有し、かつ前記エポキシ樹脂の硬化剤(D)を含むものである。イミダゾール環を有する硬化剤としては、イミダゾール、2−メチルイミダゾール、2−エチル−4−メチルイミダゾール、2−フェニルイミダゾール、1−ベンジル−2−メチルイミダゾール、2−ウンデシルイミダゾール、2−フェニル−4−メチルイミダゾール、ビス(2−エチル−4−メチル−イミダゾール)などが挙げられる。
この層間接着剤108の形成方法は特に限定されず、例えば、印刷法や転写法などがあるが、シート状の接着剤をラミネートする方法が簡便であり好ましい。
Next, an interlayer adhesive 108 (adhesive with a flux function) is formed on necessary portions on the first conductive portion 105 and the conductor circuit 106 and the base material 102 of the double-sided plate (FIG. 1D). The adhesive 108 with a flux function used here is an adhesive having a cleaning function of a metal surface, for example, a function of removing an oxide film existing on the metal surface and a function of reducing an oxide film, and is a first preferable adhesion. The composition of the agent includes a resin (A) such as a phenol novolak resin having a phenolic hydroxyl group, a cresol novolak resin, an alkylphenol novolak resin, a resole resin, or a polyvinylphenol resin, and a curing agent (B) for the resin. Curing agents are epoxidized based on bisphenol, phenol novolac, alkylphenol novolac, biphenol, naphthol, resorcinol and other skeletons such as aliphatic, cycloaliphatic and unsaturated aliphatic skeletons. Examples of the second preferable adhesive composition include phenolic bases such as bisphenol, phenol novolac, alkylphenol novolac, biphenol, naphthol, resorcinol, aliphatic, and cyclic fats. Epoxy resin (C) epoxidized on the basis of a skeleton such as an aliphatic or unsaturated aliphatic group, an imidazole ring, and a curing agent (D) for the epoxy resin. Examples of the curing agent having an imidazole ring include imidazole, 2-methylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 1-benzyl-2-methylimidazole, 2-undecylimidazole, and 2-phenyl-4. -Methylimidazole, bis (2-ethyl-4-methyl-imidazole) and the like.
A method for forming the interlayer adhesive 108 is not particularly limited, and examples thereof include a printing method and a transfer method. A method of laminating a sheet-like adhesive is simple and preferable.

次に、前記両面板を折り重ねて積層する(図2)。
折り畳みは、矩形図形のある一辺を折り畳む方法を用いてもいいし、または、矩形図面の隣接する他の一辺を折り畳む方法としてもよい。
このとき、より折り重ね易くするために一部をカットしたり、折り曲げ部分に折り目のスリットをいれたり、折り重ねズレないようにガイド穴を設けることができる。このとき、前記両面板から完全に切り離さず、一部分を残しておけば、ハンドリング上の制約を受けることなく最終工程まで加工することが可能である。
Next, the double-sided plates are folded and stacked (FIG. 2).
The folding may be performed by using a method of folding one side of the rectangular figure or by folding another adjacent side of the rectangular drawing.
At this time, in order to make it easier to fold, a guide hole can be provided so that a part is cut, a slit of a crease is inserted in the bent portion, or the folding is not displaced. At this time, if a part is left without being completely separated from the double-sided plate, it is possible to process to the final process without being restricted in handling.

この折り曲げ方はたとえば図4(a)や図4(b)のような方法があげられ特に限定する必要はなく、第1導電部105や第2導電部115、フラックス機能付き接着剤108の配置によって最適な折り曲げ方を選択すればよい。ここでは、図4(a)の折り畳み方について図2を用いて説明する。さらに、図5と図6に示すように、左右の折り畳みだけでなく、前後の折り畳みを組み合わせることによって、6層以上の多層プリント配線板や、屈曲部と部品実装部の複雑に組み合わさったフレックスリジット配線板にも適応できる。   The method of bending is, for example, the method shown in FIGS. 4A and 4B, and is not particularly limited. The first conductive portion 105, the second conductive portion 115, and the adhesive 108 with a flux function are arranged. The optimal bending method may be selected according to the above. Here, the folding method of FIG. 4A will be described with reference to FIG. Furthermore, as shown in FIG. 5 and FIG. 6, by combining not only the left and right folds but also the front and rear folds, a multilayer printed wiring board having six or more layers, or a flexibly combined flex part and component mounting part Applicable to rigid wiring boards.

次に、折り重ねられた前記両面板を一体化する(図2)。このような多層化は、熱圧着、すなわち加熱下で圧着しつつ行う。その具体的方法は、次の通りである。
金属被覆層が溶融する第1の温度に加熱して、第1導電部105の金属被覆層104が、フラックス機能付き接着剤層108を介して、第2導電部115と溶融接合するまで熱圧着し、次いで、金属被覆層104が再度溶融せず、かつ接着剤が硬化するのに適した第2の温度で再加熱してフラックス機能付き接着剤層108を硬化させ、層間を接着させることにより、積層、一体化する。このように、熱圧着の工程において、温度差を設けて行うことにより、金属被覆層108を十分に溶融して接合不良を防止するとともに、かかる溶融接合がなされた後は直ちにフラックス機能付き接着剤層108を硬化させて各層の接合部と溶融接合部を固定化する(図2(b))。
各層を積層する方法としては、例えば、真空プレスまたは熱ラミネートとベーキングを併用する方法等を用いることができる。
なお、前記第1の温度は、好ましくは170〜270℃、より好ましくは185〜260℃とされ、前記第2の温度は、好ましくは120〜200℃、より好ましくは150〜190℃とすることができる。
Next, the folded double-sided plates are integrated (FIG. 2). Such multilayering is performed while thermocompression bonding, that is, pressure bonding under heating. The specific method is as follows.
Heating to the first temperature at which the metal coating layer melts, and thermocompression bonding until the metal coating layer 104 of the first conductive portion 105 is melt-bonded to the second conductive portion 115 via the adhesive layer 108 with a flux function. Then, the metal coating layer 104 is not melted again and is reheated at a second temperature suitable for the adhesive to be cured to cure the adhesive layer 108 with a flux function, and to bond the layers. , Laminated and integrated. As described above, in the thermocompression bonding process, by performing a temperature difference, the metal coating layer 108 is sufficiently melted to prevent poor bonding, and immediately after such fusion bonding is performed, the adhesive with a flux function is used. The layer 108 is cured to fix the joints and melt joints of each layer (FIG. 2B).
As a method of laminating each layer, for example, a vacuum press or a method using a combination of thermal lamination and baking can be used.
The first temperature is preferably 170 to 270 ° C., more preferably 185 to 260 ° C., and the second temperature is preferably 120 to 200 ° C., more preferably 150 to 190 ° C. Can do.

最後に、所望の外形を切断し、多層回路板600(図2(c))を得る。   Finally, a desired outer shape is cut to obtain a multilayer circuit board 600 (FIG. 2C).

本発明を用いた8層の多層フレキシブルプリント配線板の製造方法を実施例として紹介する。まず、銅箔厚み18μm、ポリイミド厚み25μmからなるフレキシブル両面銅張積層板に、UVレーザーにより所定の箇所に、ブランドビアホールを形成し、プラズマデスミアのあと、フィルドビアめっきを形成する。ついで保護フィルムとしてドライフィルムフォトレジストをラミネートし、所定の箇所を露光・現像した後、Sn−Agはんだめっきを15μmおこなう。さらに、再度、ドライフィルムフォトレジストをラミネートし、第1導電部と第2導電部をエッチングにより形成し両面フレキシブルプリント配線板を得る。このとき、この両面フレキシブルプリント回路は図5(a)に示すように、両面フレキシブルプリント配線板ワークシート109のポリイミドをはさんで表裏が第1層と第2層になる(1)の回路110、第3層と第4層になる(2)の回路111、第5層と第6層になる(3)の回路112、第7層と第8層になる(4)の回路113がパターンニングされている。また、これらを折り重ねるとき、第1層から第8層まで順に重なるようにするために、片面側に第2層、第4層、第5層、第7層が配置され、反対面側には、第1層、第3層、第6層、第8層が配置されている。次に、第3層、第4層にあたる(2)の回路111と第5層、第6層にあたる(3)の回路112のフレキシブル性を要する屈曲部114にカバーレイフィルムを絶縁被覆する。さらに、フレックス機能を有する接着剤層を(1)の第2層部分と(4)の第7層部分、屈曲部114を除いた(2)の第4層部分にラミネートする。
次に図5(b)に示すように、折り重ねる部分に金型を用いて折り目125をつけておく。
次に図5(c)に示すように、金型で外形の周辺を切断116するとともに、重ね合わせるための位置決め用のガイド穴117をあける。(4)の回路113の外周の一部はカットせずに残しておく。これによって、両面フレキシブルプリント配線板ワークシート109上に保持されるため、その後の端子めっきや導通検査、打ち抜き加工など工程でハンドリングや搬送が容易におこなうことができる。このとき、屈曲部と積層部の境界に当たる部分は最終工程の外形打ち抜きを考慮してあらかじめ切断126しておく。
次に図6(a)にあるように(3)の回路112と(2)の回路111の間を折り目125に沿って(2)側に重ね回路118になる。さらに図6(b)にあるように(2)の回路111と(3)の回路112が重なった回路118を折り目125に沿って(4)側に重ね回路119になる。最後に図6(c)にあるように(1)の回路110を折り目115に沿って回路119側に重ね回路120となる。このとき、ガイドピンを用いて位置ズレを防止する。
その後、真空式加圧ラミネーターで130℃、0.2MPa、30秒で仮接着した後、250℃、0.05MPaで3分間プレスする。このとき、フラックス機能付き接着剤がフラックス機能を発現し、また、第1導電部の表層のSn−Agはんだが溶融するため、第1導電部と重なり合った第2導電部間に金属接合を形成する。さらに、180℃で1時間ベーキングし接着剤層を完全に硬化させる。最後に最外層をソルダーレジストで被覆し、実装用の端子部をめっきなどにより表面処理を行い、外形打ち抜きによって多層フレキシブルプリント配線板を得る。
A method for producing an eight-layer multilayer flexible printed wiring board using the present invention will be introduced as an example. First, on a flexible double-sided copper clad laminate having a copper foil thickness of 18 μm and a polyimide thickness of 25 μm, a brand via hole is formed at a predetermined location by a UV laser, and after filled with plasma desmear, filled via plating is formed. Next, a dry film photoresist is laminated as a protective film, and a predetermined portion is exposed and developed, and then Sn-Ag solder plating is performed by 15 μm. Furthermore, a dry film photoresist is again laminated, and the first conductive portion and the second conductive portion are formed by etching to obtain a double-sided flexible printed wiring board. At this time, as shown in FIG. 5 (a), this double-sided flexible printed circuit is a circuit 110 of (1) in which the front and back sides of the double-sided flexible printed wiring board worksheet 109 are sandwiched between the first layer and the second layer. The third and fourth layers (2) 111, the fifth and sixth layers (3) 112, and the seventh and eighth layers (4) 113 are patterned. Have been In addition, when these are folded, the second layer, the fourth layer, the fifth layer, and the seventh layer are arranged on one side and the other side on the opposite side in order to overlap in order from the first layer to the eighth layer. Are arranged with a first layer, a third layer, a sixth layer, and an eighth layer. Next, the coverlay film is insulatively coated on the bent portions 114 that require flexibility of the circuit 111 of (2) corresponding to the third layer and the fourth layer and the circuit 112 of (3) corresponding to the fifth layer and the sixth layer. Further, an adhesive layer having a flex function is laminated on the second layer portion (1), the seventh layer portion (4), and the fourth layer portion (2) excluding the bent portion 114.
Next, as shown in FIG.5 (b), the crease | fold 125 is given to the part to fold using a metal mold | die.
Next, as shown in FIG. 5C, the periphery of the outer shape is cut 116 with a mold, and a positioning guide hole 117 for overlapping is formed. A part of the outer periphery of the circuit 113 in (4) is left without being cut. Thereby, since it hold | maintains on the double-sided flexible printed wiring board worksheet 109, handling and conveyance can be easily performed in processes, such as subsequent terminal plating, continuity inspection, and punching. At this time, a portion corresponding to the boundary between the bent portion and the laminated portion is cut 126 in advance in consideration of the outer shape punching in the final process.
Next, as shown in FIG. 6A, the circuit 112 in (3) and the circuit 111 in (2) are overlapped on the (2) side along the fold 125 to become a circuit 118. Further, as shown in FIG. 6B, a circuit 118 in which the circuit 111 in (2) and the circuit 112 in (3) are overlapped becomes a superimposed circuit 119 along the fold 125 on the (4) side. Finally, as shown in FIG. 6C, the circuit 110 of (1) is overlapped on the circuit 119 side along the fold 115 to form a circuit 120. At this time, positional deviation is prevented by using a guide pin.
Then, after temporarily bonding at 130 ° C. and 0.2 MPa for 30 seconds with a vacuum pressure laminator, pressing is performed at 250 ° C. and 0.05 MPa for 3 minutes. At this time, the adhesive with the flux function exhibits the flux function, and the Sn-Ag solder on the surface layer of the first conductive part melts, so that a metal bond is formed between the second conductive parts overlapping the first conductive part. To do. Further, the adhesive layer is completely cured by baking at 180 ° C. for 1 hour. Finally, the outermost layer is covered with a solder resist, the terminal portion for mounting is subjected to surface treatment by plating or the like, and a multilayer flexible printed wiring board is obtained by outer shape punching.

本発明の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of this invention. 本発明の製造方法を説明するための断面図である。It is sectional drawing for demonstrating the manufacturing method of this invention. 本発明により製造された多層回路板を説明するための断面図である。It is sectional drawing for demonstrating the multilayer circuit board manufactured by this invention. 本発明の積層方法を説明するための断面図である。It is sectional drawing for demonstrating the lamination | stacking method of this invention. 本発明の積層方法を説明するための平面図である。It is a top view for demonstrating the lamination method of this invention. 本発明の積層方法を説明するための平面図である。It is a top view for demonstrating the lamination method of this invention.

符号の説明Explanation of symbols

101:銅箔
102:基材
103:フィルドビアめっき
104:金属被覆層
105:第1導電部
106:導体回路
107:絶縁被覆
108:層間接着剤(フラックス機能付き接着剤)
109:両面フレキシブルプリント配線板ワークシート(両面回路基板)
110:第2層面(下面 第1層面)回路
111:第4層面(下面 第3層面)回路
112:第5層面(下面 第6層面)回路
113:第7層面(下面 第8層面)回路
114:屈曲部
115:第2導電部
116:切断
117:ガイド穴
118:第6層面(下面 第5層、第4層、第3層面)回路
119:第3層面(下面 第4層、第5層、第6層、第7層、第8層面)回路
120:第1層面(下面 第2層、第3層、第4層、第5層、第6層、第7層、第8層面)回路
125:折り目
126:切断
550:多層回路基板
600:多層回路板
101: Copper foil 102: Substrate 103: Filled via plating 104: Metal coating layer 105: First conductive part 106: Conductor circuit 107: Insulation coating 108: Interlayer adhesive (adhesive with flux function)
109: Double-sided flexible printed wiring board worksheet (double-sided circuit board)
110: second layer surface (lower surface first layer surface) circuit 111: fourth layer surface (lower surface third layer surface) circuit 112: fifth layer surface (lower surface sixth layer surface) circuit 113: seventh layer surface (lower surface eighth layer surface) circuit 114: Bending portion 115: second conductive portion 116: cutting 117: guide hole 118: sixth layer surface (lower surface fifth layer, fourth layer, third layer surface) circuit 119: third layer surface (lower surface fourth layer, fifth layer, 6th layer, 7th layer, 8th layer surface) circuit 120: 1st layer surface (lower surface 2nd layer, 3rd layer, 4th layer, 5th layer, 6th layer, 7th layer, 8th layer surface) circuit 125 : Crease 126: Cutting 550: Multilayer circuit board 600: Multilayer circuit board

Claims (9)

基材と、前記基材の少なくとも一方の面に設けられた第1導電部および第2導電部とを備える両面回路基板を用意する工程と、
前記一方の面に設けられた前記第1導電部および前記第2導電部のうち、少なくとも一方を層間接着剤で覆う工程と、
前記両面回路基板を少なくとも一回折り畳み、前記層間接着剤を介して前記第1導電部の設けられた第1面領域と前記第2導電部の設けられた第2面領域とを対向させた状態とする工程と、
前記状態で加熱プレスすることにより、前記第1導電部と前記第2導電部に挟まれた部分にある層間接着剤を溶融除去し、前記第1導電部と前記第2導電部とを電気的に接続させ、多層回路基板を形成する工程と、
前記多層回路基板の周辺部を除去して多層回路板を得る工程と
を含むことを特徴とする多層回路板の製造方法。
Preparing a double-sided circuit board comprising a base material and a first conductive part and a second conductive part provided on at least one surface of the base material;
Covering at least one of the first conductive part and the second conductive part provided on the one surface with an interlayer adhesive;
A state in which the double-sided circuit board is folded at least once, and the first surface region provided with the first conductive part and the second surface region provided with the second conductive part are opposed to each other through the interlayer adhesive. And a process of
By heat-pressing in the state, the interlayer adhesive in the portion sandwiched between the first conductive portion and the second conductive portion is melted and removed, and the first conductive portion and the second conductive portion are electrically connected. Forming a multilayer circuit board, and
And a step of removing a peripheral portion of the multilayer circuit board to obtain a multilayer circuit board.
前記基材は、樹脂フィルムである請求項1に記載の多層回路板の製造方法。   The method for manufacturing a multilayer circuit board according to claim 1, wherein the substrate is a resin film. 前記樹脂フィルムは、ポリイミド樹脂フィルムである請求項2に記載の多層回路板の製造方法。   The method for producing a multilayer circuit board according to claim 2, wherein the resin film is a polyimide resin film. 前記両面回路基板は、フィルドビア構造を有する請求項1ないし3のいずれかに記載の多層回路板の製造方法。   4. The method for manufacturing a multilayer circuit board according to claim 1, wherein the double-sided circuit board has a filled via structure. 前記第1導電部または前記第2導電部の表面に、金属被覆層が形成されている請求項1ないし4のいずれかに記載の多層回路板の製造方法。   The method for manufacturing a multilayer circuit board according to any one of claims 1 to 4, wherein a metal coating layer is formed on a surface of the first conductive portion or the second conductive portion. 前記金属被覆層は、はんだまたは低融点金属からなり、厚さが3μm以上、30μm以下である請求項5に記載の多層回路板の製造方法。   The method for manufacturing a multilayer circuit board according to claim 5, wherein the metal coating layer is made of solder or a low melting point metal and has a thickness of 3 μm or more and 30 μm or less. 前記基材は、矩形形状の第1面領域と、前記第1面領域の一つの辺を共有して隣接する矩形形状の第2面領域とを含み、
前記両面回路基板を折り畳む工程は、前記辺を折り返し部として前記基材を折り畳み、第1面領域および第2面領域を重ね合わせ対向させる工程を含む、
請求項1ないし6のいずれかに記載の多層回路板の製造方法。
The base material includes a rectangular first surface region, and a rectangular second surface region adjacent to and sharing one side of the first surface region,
The step of folding the double-sided circuit board includes a step of folding the base material with the side as a folded portion and overlapping and opposing the first surface region and the second surface region,
A method for manufacturing a multilayer circuit board according to any one of claims 1 to 6.
前記基材は、矩形形状の第1面領域と、前記第1面領域の一辺を共有して隣接する矩形形状の第2面領域と、前記第1面領域の他辺を共有して隣接する矩形形状の第3面領域とを含み、
前記両面回路基板を折り畳む工程は、
前記一辺を折り返し部として前記基材を折り畳み、第1面領域および第2面領域を重ね合わせ対向させる第1折り畳み工程と、
前記他辺を折り返し部として前記基材をさらに折り畳み、第1面領域、第2面領域および第3面領域を重ね合わせる第2折り畳み工程と、
を含む、
請求項1ないし6のいずれかに記載の多層回路板の製造方法。
The base material is adjacent to a rectangular first surface region, a rectangular second surface region sharing one side of the first surface region, and sharing another side of the first surface region. A rectangular third surface region,
The step of folding the double-sided circuit board includes:
A first folding step in which the base is folded with the one side as a folded portion, and the first surface region and the second surface region are overlapped with each other;
A second folding step of further folding the base material with the other side as a folded portion, and overlapping the first surface region, the second surface region, and the third surface region;
including,
A method for manufacturing a multilayer circuit board according to any one of claims 1 to 6.
請求項1ないし8のいずれかに記載の方法により製造された多層回路板。

A multilayer circuit board manufactured by the method according to claim 1.

JP2005379534A 2005-12-28 2005-12-28 Multilayer circuit board and manufacturing method therefor Pending JP2007180421A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120011713A1 (en) * 2010-07-13 2012-01-19 Foxconn Advanced Technology Inc. Method for manufacturing multilayer printed circuit board
TWI407872B (en) * 2010-07-22 2013-09-01 Zhen Ding Technology Co Ltd Method for manufacturing printed circuit board
JP2017022173A (en) * 2015-07-07 2017-01-26 日本メクトロン株式会社 Elastic conductive substrate and elastic conductive laminate
WO2018123961A1 (en) * 2016-12-27 2018-07-05 学校法人関東学院 Multilayered wiring board and method for manufacturing multilayered wiring board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0429389A (en) * 1990-05-24 1992-01-31 Hitachi Chem Co Ltd Flexible printed circuit board
JP2005506713A (en) * 2001-10-23 2005-03-03 シャフナー・エーエムファウ・アクチェンゲゼルシャフト Multilayer circuit and manufacturing method thereof
JP2005109188A (en) * 2003-09-30 2005-04-21 Sumitomo Bakelite Co Ltd Circuit board and multilayer board, and method for manufacturing circuit board and multilayer board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0429389A (en) * 1990-05-24 1992-01-31 Hitachi Chem Co Ltd Flexible printed circuit board
JP2005506713A (en) * 2001-10-23 2005-03-03 シャフナー・エーエムファウ・アクチェンゲゼルシャフト Multilayer circuit and manufacturing method thereof
JP2005109188A (en) * 2003-09-30 2005-04-21 Sumitomo Bakelite Co Ltd Circuit board and multilayer board, and method for manufacturing circuit board and multilayer board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120011713A1 (en) * 2010-07-13 2012-01-19 Foxconn Advanced Technology Inc. Method for manufacturing multilayer printed circuit board
US9095082B2 (en) 2010-07-13 2015-07-28 Fukui Precision Component (Shenzhen) Co., Ltd. Method for manufacturing multilayer printed circuit board
TWI407872B (en) * 2010-07-22 2013-09-01 Zhen Ding Technology Co Ltd Method for manufacturing printed circuit board
JP2017022173A (en) * 2015-07-07 2017-01-26 日本メクトロン株式会社 Elastic conductive substrate and elastic conductive laminate
WO2018123961A1 (en) * 2016-12-27 2018-07-05 学校法人関東学院 Multilayered wiring board and method for manufacturing multilayered wiring board
JPWO2018123961A1 (en) * 2016-12-27 2019-10-31 学校法人関東学院 Multilayer wiring board and multilayer wiring board manufacturing method

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