JP2007123913A - Method for manufacturing epitaxial wafer - Google Patents

Method for manufacturing epitaxial wafer Download PDF

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JP2007123913A
JP2007123913A JP2006315028A JP2006315028A JP2007123913A JP 2007123913 A JP2007123913 A JP 2007123913A JP 2006315028 A JP2006315028 A JP 2006315028A JP 2006315028 A JP2006315028 A JP 2006315028A JP 2007123913 A JP2007123913 A JP 2007123913A
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algainp
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Yasuo Hosokawa
泰男 細川
Yasuyuki Sakaguchi
泰之 坂口
Toshiyuki Tanaka
利幸 田中
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Resonac Holdings Corp
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Showa Denko KK
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<P>PROBLEM TO BE SOLVED: To provide an epitaxial wafer having a crystalline, excellent AlGaInP base DH (double hetero) structure on a GaP substrate, and to provide an LED of high luminance using the wafer. <P>SOLUTION: In a method for manufacturing an epitaxial wafer having a double hetero structure of a GaP buffer layer, an AlGaInP first stage lower clad layer, an AlGaInP lower clad layer as an active layer, an AlGaInP active layer, and an AlGaInP upper clad layer on a GaP compound semiconductor substrate, after the GaP buffer layer is grown on the GaP compound semiconductor substrate and the AlGaInP first stage lower clad layer is grown thereon, the surface of the AlGaInP first stage lower clad layer is polished and then the epitaxial growth of the AlGaInP lower clad layer, the GaInP active layer, and the AlGaInP upper clad layer is caused to occur. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、エピタキシャル成長方法によるウェーハに係り、特に格子ミスマッチのあるヘテロ接合を有するエピタキシャルウェーハ、及び当該ウェーハを使用して作製した発光ダイオードに関するものである。   The present invention relates to a wafer formed by an epitaxial growth method, and more particularly to an epitaxial wafer having a heterojunction with a lattice mismatch and a light emitting diode manufactured using the wafer.

近年、半導体基板上に基板の格子定数と異なる格子定数を有する能動層をエピタキシャル成長させて各種デバイスを作製する技術が注目されている。この格子不整合系の材料として、可視光領域の発光ダイオード(LED)やレーザーダイオード(LD)用の材料として利用される(AlXGa1-XYIn1-YP(0≦X≦1,0≦Y≦1)がある。この材料系では特にGaAs基板上に当該材料を使用したDH構造を有するLED、LDとしての応用が盛んに行われている(例えば、特許文献1参照。)。図3にGaAs基板を使用した場合のウェーハ構造を示す。この場合、GaAs基板と(AlXGa1-X0.51In0.49Pエピタキシャル層との間に格子定数の差はなく(格子整合系)、良質なエピタキシャルウェーハが得られている。一方、GaAs基板を使用することで、(AlXGa1-XYIn1-YPのDH構造部分で発光した光のうち、基板側に放出されるものはGaAs基板で吸収されてしまうために、表面側に取り出すことができず発光効率が上がらないという欠点がある。そこで、基板による光の吸収を低減し発光効率を高める目的で、発光した可視光に対して透明なGaPを基板として使用した研究も行われるようになった。しかし、基板としてGaPを使用した場合には、GaP基板と(AlXGa1-XYIn1-YPとの間に格子定数の差(格子ミスマッチ)があるために、(AlXGa1-XYIn1-YPエピタキシャル層の結晶性が劣化することが問題となっていた。 2. Description of the Related Art In recent years, attention has been paid to a technique for manufacturing various devices by epitaxially growing an active layer having a lattice constant different from that of a substrate on a semiconductor substrate. As the material for the lattice-mismatched, is used as a material for a light-emitting diode in the visible light region (LED) and laser diodes (LD) (Al X Ga 1 -X) Y In 1-Y P (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1). Especially in this material system, application as LED and LD which have a DH structure using the said material on a GaAs substrate is performed actively (for example, refer patent document 1). FIG. 3 shows a wafer structure when a GaAs substrate is used. In this case, there is no difference in lattice constant between the GaAs substrate and the (Al x Ga 1-x ) 0.51 In 0.49 P epitaxial layer (lattice matching system), and a good quality epitaxial wafer is obtained. On the other hand, the use of GaAs substrate, (Al X Ga 1-X ) of the light emitted in the Y an In DH structure portion of 1-Y P, which is emitted to the substrate side is absorbed by the GaAs substrate For this reason, there is a drawback in that it cannot be taken out to the surface side and the luminous efficiency does not increase. Therefore, for the purpose of reducing the light absorption by the substrate and increasing the light emission efficiency, research has been conducted using GaP that is transparent to the emitted visible light as the substrate. However, when using GaP as the substrate, due to the difference in lattice constant between the GaP substrate and the (Al X Ga 1-X) Y In 1-Y P ( lattice mismatch), (Al X Ga 1-X ) Y In 1-Y P The crystallinity of the epitaxial layer has been a problem.

また、別の例として、GaAs基板を使用し、構成整合させないでy≠0.51である(AlXGa1-XYIn1-YP系の材料を用いて短波長の可視光LEDを作製するものや、GaAs基板上に0<y<1であるGaAsY1-Y系材料を能動層として作製する可視光LED等がある。 As another example, using a GaAs substrate, a y ≠ 0.51 not allow configuration matching (Al X Ga 1-X) Y In 1-Y P based visible LED material using short wavelength And a visible light LED that uses a GaAs Y P 1-Y material with 0 <y <1 as an active layer on a GaAs substrate.

ここで、この格子定数の差については、LEDを作製した時の発光波長が590nm前後の黄色〜橙色の発光になるような組成のGa0.65In0.35P活性層をエピタキシャル成長させる場合に、その格子ミスマッチ度が約2.7%となる。従来、この格子ミスマッチによる結晶性の劣化を緩和するために、GaP基板の格子定数から所定の組成の(AlXGa1-XYIn1-YPの格子定数まで連続的に格子定数を変化させるエピタキシャル層(格子定数変化層あるいは組成勾配層と称す)を挿入すること(例えば、特許文献2参照。)や、格子定数の異なる層を成長する前に特別なバッファ層を挿入すること(例えば、非特許文献1参照。)が行われてきた。 Here, regarding the difference in lattice constant, the lattice mismatch occurs when a Ga 0.65 In 0.35 P active layer having a composition that emits yellow to orange light having an emission wavelength of about 590 nm when an LED is fabricated is epitaxially grown. The degree is about 2.7%. Conventionally, in order to alleviate the crystallinity degradation caused by the lattice mismatch, a predetermined composition from the lattice constant of the GaP substrate (Al X Ga 1-X) continuously lattice constant to the lattice constant of the Y In 1-Y P Inserting an epitaxial layer to be changed (referred to as a lattice constant changing layer or a composition gradient layer) (see, for example, Patent Document 2), or inserting a special buffer layer before growing a layer having a different lattice constant ( For example, see Non-Patent Document 1.).

ここで、格子ミスマッチ度とは、下記(1)式で定義される。
格子ミスマッチ度=(エピタキシャル層の格子定数−基板の格子定数)×100/(基板の格子定数)・・・(1)
ただし、組成勾配層や特別な成長条件のバッファ層を具備するだけでは格子定数の異なるDH構造部分の結晶性を向上することは現実には難しい。
特開平2−257677号公報 特開平3−203316号公報 Appl.Phys.Lett.53(5).1988
Here, the degree of lattice mismatch is defined by the following equation (1).
Lattice mismatch degree = (lattice constant of epitaxial layer−lattice constant of substrate) × 100 / (lattice constant of substrate) (1)
However, it is actually difficult to improve the crystallinity of the DH structure portion having a different lattice constant only by providing a composition gradient layer or a buffer layer having a special growth condition.
JP-A-2-257777 JP-A-3-203316 Appl. Phys. Lett. 53 (5). 1988

発光した可視光に対して透明なGaP基板を使用する場合や、GaAs基板を利用して格子定数の異なる発光層を用いる場合に、従来行われてきたような組成勾配層を挿入したり、特別な成長条件のバッファ層を挿入するだけでは、格子定数が基板と異なり、表面状態が良好で、且つ結晶性の良好なDH構造部分を成長することは難しい。格子ミスマッチがある場合は、周辺部と組成が異なり成長速度も早くなるため、ヒロックと呼ばれる盛り上がった突起物が島状に分布する結晶表面となる。また、そのようなエピタキシャルウェーハを用いた場合には、高輝度のLEDがまだ得られていない。   When using a GaP substrate that is transparent to the emitted visible light, or when using a light emitting layer having a different lattice constant using a GaAs substrate, a composition gradient layer, which has been conventionally used, It is difficult to grow a DH structure portion having a lattice constant different from that of a substrate, having a good surface state, and good crystallinity only by inserting a buffer layer having a suitable growth condition. When there is a lattice mismatch, the composition is different from that of the peripheral portion and the growth rate is increased, so that raised protrusions called hillocks are formed on the crystal surface distributed in an island shape. Further, when such an epitaxial wafer is used, a high-brightness LED has not been obtained yet.

そこで、組成勾配層あるいはバッファ層を成長した後にその当該表面をポリッシュして平坦にすることにより、格子ミスマッチが原因で発生した転位や欠陥、表面の凹凸がその後の結晶成長層に影響しないようにして、結晶性の良好なDH構造部分ひいては高輝度のLEDを作製することが本発明の目的である。   Therefore, after growing the composition gradient layer or buffer layer, the surface is polished and flattened so that dislocations, defects, and surface irregularities caused by lattice mismatch do not affect the subsequent crystal growth layer. Thus, it is an object of the present invention to produce a DH structure portion with good crystallinity and thus a high-brightness LED.

すなわち、本願発明は以下に関する。
(1)GaP化合物半導体基板上に、GaPバッファ層、AlGaInP第一段下部クラッド層、能動層としてAlGaInP下部クラッド層、AlGaInP活性層、AlGaInP上部クラッド層のダブルヘテロ構造を有するエピタキシャルウェーハの製造方法であって、前記GaP化合物半導体基板上に前記GaPバッファ層を成長させ、その上に前記AlGaInP第一段下部クラッド層を成長させた後に、この前記AlGaInP第一段下部クラッド層表面をポリッシュし、その後、前記AlGaInP下部クラッド層、前記GaInP活性層、前記AlGaInP上部クラッド層のエピタキシャル成長を順次行うことを特徴とする発光ダイオード用途のエピタキシャルウェーハの製造方法。
(2)前記GaPバッファ層と前記AlGaInP第一段下部クラッド層との間に、前記GaP化合物半導体基板の格子定数から能動層の格子定数まで格子定数が連続的に変化するAlGaInP組成勾配層を成長させることを特徴とする(1)に記載の発光ダイオード用途のエピタキシャルウェーハの製造方法。
That is, the present invention relates to the following.
(1) A method of manufacturing an epitaxial wafer having a double heterostructure of a GaP buffer layer, an AlGaInP first-stage lower cladding layer, an AlGaInP lower cladding layer, an AlGaInP active layer, and an AlGaInP upper cladding layer as an active layer on a GaP compound semiconductor substrate. Then, after the GaP buffer layer is grown on the GaP compound semiconductor substrate and the AlGaInP first stage lower cladding layer is grown thereon, the surface of the AlGaInP first stage lower cladding layer is polished, A method of manufacturing an epitaxial wafer for light-emitting diodes, comprising epitaxially growing the AlGaInP lower cladding layer, the GaInP active layer, and the AlGaInP upper cladding layer sequentially.
(2) An AlGaInP composition gradient layer whose lattice constant continuously changes from the lattice constant of the GaP compound semiconductor substrate to the lattice constant of the active layer is grown between the GaP buffer layer and the AlGaInP first-stage lower cladding layer. The method for producing an epitaxial wafer for light-emitting diode use according to (1), wherein

本発明は可視光に対して透明なGaP基板上に、格子ミスマッチのある(AlXGa1-XYIn1-YPのバッファ層あるいは組成勾配層を成長した後に、当該表面をポリッシュし、表面を平坦にした後再度エピタキシャル成長することにより格子ミスマッチの影響を排除し、結晶性の良好な能動層構造を得るものである。また、このようなエピタキシャルウェーハを使用すれば、従来より高輝度のLEDを得ることができる。また、本発明は基板としてGaAsを使用した場合に、GaAsP系のエピタキシャル成長をする場合、AlGaInP系DH構造をエピタキシャル成長する場合にも同様の効果が得られる。 The present invention is transparent GaP substrate to visible light, after growing the a lattice mismatch (Al X Ga 1-X) Y In 1-Y buffer layer or gradient composition layer of P, polished the surface The effect of lattice mismatch is eliminated by flattening the surface and then performing epitaxial growth again to obtain an active layer structure with good crystallinity. Moreover, if such an epitaxial wafer is used, LED with higher brightness than the conventional one can be obtained. In the present invention, when GaAs is used as the substrate, the same effect can be obtained when GaAsP-based epitaxial growth is performed and when an AlGaInP-based DH structure is epitaxially grown.

GaP基板上には、先ず基板の結晶欠陥の影響を低減するため、GaPのバッファ層をエピタキシャル成長させる。結晶成長方法は通常MOVPE法に依るのが一般的である。その上には、本発明で目的としている590〜610nmで発光するような組成に調整した活性層(AlXGa1-XYIn1-YP(0.18≦X≦0.30、Y=0.51)に適合したクラッド層組成と同組成のバッファ層(AlXGa1-XYIn1-YP(X≧0.70、Y=0.51)を成長する。この層の格子定数はGaP基板の格子定数と異なり、約2.7%の格子ミスマッチが存在する。また、このような格子定数の異なるバッファ層を成長する前に組成勾配層を挿入し、格子定数を徐々に変化させて約2.7%の格子ミスマッチのある層を最終的に成長しても良い。この格子ミスマッチの影響を緩和するため、当該バッファ層表面をポリッシュする。ポリッシュする厚さはバッファ層の1/2〜2/3を目安とすれば良い。結晶表面のポリッシュは通常の基板表面をポリッシュするのと同じポリッシングマシーンで行う。例えばバッファ層は3μm程度成長させておき、ポリッシュにより約2μm削って残り膜厚を1μm程度とする。ポリッシュした後再度MOVPE装置に導入して、能動層構造部分の結晶成長を行う。 On the GaP substrate, a GaP buffer layer is first epitaxially grown in order to reduce the influence of crystal defects on the substrate. The crystal growth method is generally based on the MOVPE method. On its active layer was adjusted to the composition such that emission at 590~610nm which are intended in the present invention (Al X Ga 1-X) Y In 1-Y P (0.18 ≦ X ≦ 0.30, Y = 0.51 cladding layer composition having the same composition buffer layer adapted to) (Al X Ga 1-X ) Y in 1-Y P (X ≧ 0.70, Y = 0.51) is grown. The lattice constant of this layer is different from the lattice constant of the GaP substrate, and there is a lattice mismatch of about 2.7%. Further, a composition gradient layer is inserted before growing such buffer layers having different lattice constants, and a layer having a lattice mismatch of about 2.7% is finally grown by gradually changing the lattice constant. good. In order to alleviate the influence of this lattice mismatch, the surface of the buffer layer is polished. The thickness to be polished may be about 1/2 to 2/3 of the buffer layer. The polishing of the crystal surface is performed by the same polishing machine as that for polishing the normal substrate surface. For example, the buffer layer is grown about 3 μm, and is polished by about 2 μm to make the remaining film thickness about 1 μm. After polishing, it is introduced again into the MOVPE apparatus and crystal growth of the active layer structure portion is performed.

再度結晶成長を行う場合に、先ずポリッシュ前に成長したバッファ層と同組成の(AlXGa1-XYIn1-YPをDH構造部分の下部クラッド層として2.0μm程度成長させる。バッファ層と下部クラッド層までは、H2Seをドーパントとしてn型にドーピングし、そのキャリア濃度は1×1018cm-3程度とする。その後活性層を成長させる。膜厚は1.0μm程度とし、組成は590〜610nmの間で目的とする発光波長になるよう設定する。この層はDEZnをドーパントとしてp型にドーピングする。キャリア濃度は5×1017cm-3程度である。次に上部クラッド層を成長させる。組成は下部クラッド層と同じであるが、DEZnをドーパントとしてp型にドーピングする。キャリア濃度は5×1017cm-3程度である。膜厚は下部クラッド層と同じ2μm程度である。こうして得られたDH構造部分の上にコンタクト層として活性層と同組成のGaInPを成長させる。この層も上部クラッド層と同程度にp型にドーピングし、膜厚は0.5μm程度である。 When performing crystal growth once again, it is first 2.0μm about growth polished before grown buffer layer and the same composition in the (Al X Ga 1-X) Y In 1-Y P as a lower cladding layer of the DH structure portion. The buffer layer and the lower cladding layer are doped n-type with H 2 Se as a dopant, and the carrier concentration is about 1 × 10 18 cm −3 . Thereafter, the active layer is grown. The film thickness is set to about 1.0 μm, and the composition is set so that the target emission wavelength is between 590 to 610 nm. This layer is doped p-type with DEZn as a dopant. The carrier concentration is about 5 × 10 17 cm −3 . Next, an upper cladding layer is grown. The composition is the same as that of the lower cladding layer, but it is doped p-type using DEZn as a dopant. The carrier concentration is about 5 × 10 17 cm −3 . The film thickness is about 2 μm which is the same as the lower cladding layer. On the DH structure portion thus obtained, GaInP having the same composition as the active layer is grown as a contact layer. This layer is also doped p-type to the same extent as the upper cladding layer, and the film thickness is about 0.5 μm.

このようにして作製したエピタキシャルウェーハを使用してLEDを作製する場合、発光部分であるDH構造部分の結晶性が格子ミスマッチの影響があるにもかかわらず如何に良好であるかが重要となる。従って、本発明のようにバッファ層成長後にその表面を一旦ポリッシュすると、格子ミスマッチの影響で島状成長した表面の凹凸部分が平坦になり、また発生した結晶欠陥をその後の層に伝播し難くするため、結晶性の良好なDH構造部分のエピタキシャル成長が可能となる。その結果従来得られていた格子不整合系のLEDよりも高輝度が得られる。   When an LED is manufactured using the epitaxial wafer manufactured as described above, it is important how good the crystallinity of the DH structure portion as a light emitting portion is despite the influence of lattice mismatch. Therefore, once the surface is polished after growing the buffer layer as in the present invention, the uneven portion of the island-grown surface is flattened due to the effect of lattice mismatch, and the generated crystal defects are difficult to propagate to the subsequent layers. Therefore, it is possible to epitaxially grow a DH structure portion with good crystallinity. As a result, it is possible to obtain higher luminance than the lattice-mismatched LED that has been obtained conventionally.

次に本発明の実施例を組成勾配層の有無の二つの場合についてそれぞれ詳細に説明する。今回はGaP基板上にGaInPを活性層とするDH構造のエピタキシャルウェーハを作製した。使用したGaP基板は、Sをドープしたn型基板である。本実施例では、MOVPE法により減圧下にて結晶成長を行った。使用した原料ガスはTMA、TMG、TMI、PH3(100%ガス)であり、キャリアガスとして超高純度のH2ガスを使用した。
(実施例1)
先ず、組成勾配層のない場合についての実施例を示す。ウェーハの断面構造を図1に示す。結晶成長は先ず730℃にてGaPバッファ層7を0.5μm成長させた。この時Seをドーパントとして使用しn型のドーピングを行った。続いてDH構造部分の下部クラッド層5と同組成である(Al0.2Ga0.80.65In0.35P第一段下部クラッド層6を約3μm成長させた。この層もSeをドーパントとしてGaPバッファ層7と同じく1×1018cm-3程度にドーピングした。この組成での格子定数はGaPの格子定数より大きく、その格子ミスマッチ度は約2.7%である。従って、この層を3μm成長した後の表面状態は悪く、ヒロックと呼ばれる周辺部と組成が異なり且つ島状成長により周辺より成長速度が速いために盛り上がった突起物が多く存在した。このヒロックの大きさは、3μmのエピタキシャル成長後で約20×30μmであり高さは約6μmであった。また、ウェーハ面内での密度は約1000〜3000cm-2であった。
Next, an example of the present invention will be described in detail for each of the two cases with and without a composition gradient layer. This time, an epitaxial wafer having a DH structure using GaInP as an active layer was fabricated on a GaP substrate. The GaP substrate used is an n-type substrate doped with S. In this example, crystal growth was performed under reduced pressure by the MOVPE method. The raw material gases used were TMA, TMG, TMI, and PH 3 (100% gas), and ultra-high purity H 2 gas was used as the carrier gas.
Example 1
First, the example about the case where there is no composition gradient layer is shown. A cross-sectional structure of the wafer is shown in FIG. For crystal growth, a GaP buffer layer 7 was first grown at 730 ° C. by 0.5 μm. At this time, Se was used as a dopant to perform n-type doping. Subsequently, an (Al 0.2 Ga 0.8 ) 0.65 In 0.35 P first stage lower cladding layer 6 having the same composition as the lower cladding layer 5 in the DH structure portion was grown by about 3 μm. This layer was also doped with Se as a dopant to about 1 × 10 18 cm −3 in the same manner as the GaP buffer layer 7. The lattice constant with this composition is larger than that of GaP, and the degree of lattice mismatch is about 2.7%. Therefore, the surface state after this layer was grown by 3 μm was poor, and there were many protrusions raised because the composition was different from the peripheral part called hillock and the growth rate was faster than the peripheral part due to island growth. The size of this hillock was about 20 × 30 μm and the height was about 6 μm after 3 μm epitaxial growth. The density in the wafer plane was about 1000 to 3000 cm −2 .

ここで第一段目の結晶成長を停止し、ウェーハを取り出した。取り出したウェーハをGaAs基板をポリッシュする通常のポリッシングマシーンでポリッシュした。ポリッシュは平滑なガラスまたはセラミックス定盤に固定し、外径約0.5μmのSiO2超微粒子と次亜塩素酸ナトリウムを主成分とするポリッシュ液を用いて化学機械的に研磨した。この時、加工ダメージを小さくするために、加重は50g/cm2程度に抑えた。研磨速度は装置状態により異なるが、装置により適当な値を設定することで、研磨後の表面の凹凸をピーク値で最大0.002μmに抑えることができる。今回は研磨速度0.05μm/minで、研磨後の表面粗度は0.5μm以下であった。研磨量としては、(Al0.2Ga0.80.65In0.35P成長層約3μmの内約2μmをポリッシュして1μm残した。このウェーハの表面には所々にヒロックの跡が見られたが、平坦であった。 Here, the first-stage crystal growth was stopped, and the wafer was taken out. The removed wafer was polished by a normal polishing machine for polishing the GaAs substrate. The polish was fixed to a smooth glass or ceramic surface plate, and was chemically and mechanically polished using a polish solution mainly composed of SiO 2 ultrafine particles having an outer diameter of about 0.5 μm and sodium hypochlorite. At this time, the load was suppressed to about 50 g / cm 2 in order to reduce processing damage. The polishing rate varies depending on the apparatus state, but by setting an appropriate value depending on the apparatus, the unevenness of the surface after polishing can be suppressed to a maximum value of 0.002 μm. This time, the polishing rate was 0.05 μm / min, and the surface roughness after polishing was 0.5 μm or less. As the polishing amount, about 2 μm of about 3 μm of the (Al 0.2 Ga 0.8 ) 0.65 In 0.35 P growth layer was polished to leave 1 μm. Although the surface of this wafer showed hillocks in some places, it was flat.

再びMOVPE装置にてDH構造部分の結晶成長を行った。ポリッシュ前に成長させた(Al0.2Ga0.80.65In0.35Pを下部クラッド層5として再び1μm成長させた。続いて、Ga0.65In0.35Pの組成を有する活性層4を1μm成長させた。GaP基板8と上記活性層4の間の格子ミスマッチ度は、GaP、Ga0.65In0.35Pの格子定数が各々5.450オングストローム、5.597オングストロームであることより、式(1)から2.7%となる。活性層はDEZnをドーパントとしてp型にドーピングし、そのキャリア濃度は5×1017cm-3とした。活性層の上部には下部クラッド層と同一の組成を有する(Al0.2Ga0.80.65In0.35Pを上部クラッド層3として2μm成長させた。上部クラッド層3も活性層4と同様DEZnをドーパントとしてp型にドーピングした。キャリア濃度も同様に5×1017cm-3とした。また、電極をとりやすくするために、活性層4と同組成のp型Ga0.65In0.35P層をコンタクト層2として最後に成長させた。比較のため同条件で(Al0.2Ga0.80.65In0.35Pの下部クラッド層5を最初から2μm成長し、ウェーハ表面のポリッシュをしないで続いて活性層4を成長した同一構造のエピタキシャルウェーハを作製し、LEDを作製してその発光特性を比較した。 Again, crystal growth of the DH structure portion was performed with the MOVPE apparatus. (Al 0.2 Ga 0.8 ) 0.65 In 0.35 P grown before polishing was grown again by 1 μm as the lower cladding layer 5. Subsequently, an active layer 4 having a composition of Ga 0.65 In 0.35 P was grown by 1 μm. The degree of lattice mismatch between the GaP substrate 8 and the active layer 4 is that the lattice constants of GaP and Ga 0.65 In 0.35 P are 5.450 angstroms and 5.597 angstroms, respectively. %. The active layer was doped p-type using DEZn as a dopant, and its carrier concentration was 5 × 10 17 cm −3 . On the active layer, (Al 0.2 Ga 0.8 ) 0.65 In 0.35 P having the same composition as the lower cladding layer was grown as the upper cladding layer 3 by 2 μm. Similarly to the active layer 4, the upper cladding layer 3 was also doped p-type with DEZn as a dopant. Similarly, the carrier concentration was set to 5 × 10 17 cm −3 . Further, in order to facilitate the electrode formation, a p-type Ga 0.65 In 0.35 P layer having the same composition as that of the active layer 4 was finally grown as the contact layer 2. For comparison, under the same conditions, an epitaxial wafer having the same structure was fabricated by growing the lower cladding layer 5 of (Al 0.2 Ga 0.8 ) 0.65 In 0.35 P 2 μm from the beginning and subsequently growing the active layer 4 without polishing the wafer surface. Then, LEDs were fabricated and their light emission characteristics were compared.

作製したLEDは、350×350μmの大きさであり、その特性評価は積分球を使用した輝度測定により行った。発光波長について視感度補正を行った後のそれぞれの基板を使用したLEDの輝度は、従来のウェーハ表面のポリッシュをしない場合で2500ミリカンデラであったのに対して、ウェーハ表面のポリッシュを行った場合では3500ミリカンデラと高輝度であった。尚、測定時の印加電流は20ミリアンペアである。
(実施例2)
次に、組成勾配層を挿入した場合の実施例について示す。ウェーハは図2に示す構造とした。実施例1で示したのと同様に、先ず730℃にてGaPバッファ層7を0.5μm成長させた。続いてAl、In原料を添加し、その供給量を連続的に変化させて、組成がGaPから(Al0.2Ga0.80.65In0.35Pまで変化する組成勾配層16を2μm成長させた。組成勾配層16での原料供給量の変化は、TMGaで25→14SCCM、TMInで3→97SCCM、TMAlは一定とした。
The produced LED has a size of 350 × 350 μm, and its characteristic evaluation was performed by luminance measurement using an integrating sphere. The brightness of the LED using each substrate after correcting the visibility with respect to the emission wavelength was 2500 millicandelas when the conventional wafer surface was not polished, whereas the wafer surface was polished. In some cases, the brightness was as high as 3500 millicandelas. The applied current at the time of measurement is 20 milliamperes.
(Example 2)
Next, an example in which a composition gradient layer is inserted will be described. The wafer has the structure shown in FIG. In the same manner as shown in Example 1, the GaP buffer layer 7 was first grown at 730 ° C. by 0.5 μm. Subsequently, Al and In raw materials were added, and the supply amount was continuously changed to grow 2 μm of the composition gradient layer 16 whose composition changed from GaP to (Al 0.2 Ga 0.8 ) 0.65 In 0.35 P. The changes in the raw material supply amount in the composition gradient layer 16 were constant for TM → 25 → 14 SCCM, TMIn 3 → 97 SCCM, and TMAl.

組成勾配層16を成長後、連続して(Al0.2Ga0.80.65In0.35Pの組成を有する下部クラッド層5と同一組成層のn−AlGaInP第一段下部クラッド層6を3μm成長させた。この時点で第一段目の結晶成長を停止し、ウェーハを取り出した。表面状態は実施例1に比べて良好であった。これは組成勾配層16により格子ミスマッチの影響を僅かながら緩和できたためと思われる。この場合のヒロックの大きさは、約10×20μmであり、高さは約5μmであった。また、ウェーハ面内での密度も約400〜500cm-2であり、組成勾配層の無い実施例1より少なかった。取り出したウェーハを実施例1と同様、第一段下部クラッド層6の残り膜厚が1μmとなるようにポリッシュし、第二段目の結晶成長を行った。平坦度については、実施例1と同様0.5μm以下であった。 After the composition gradient layer 16 was grown, an n-AlGaInP first-stage lower cladding layer 6 having the same composition layer as the lower cladding layer 5 having a composition of (Al 0.2 Ga 0.8 ) 0.65 In 0.35 P was continuously grown by 3 μm. At this point, the first-stage crystal growth was stopped and the wafer was taken out. The surface condition was better than that of Example 1. This is presumably because the composition gradient layer 16 can slightly relax the influence of the lattice mismatch. In this case, the size of the hillock was about 10 × 20 μm, and the height was about 5 μm. Further, the density in the wafer plane was about 400 to 500 cm −2 , which was less than that in Example 1 without the composition gradient layer. The removed wafer was polished in the same manner as in Example 1 so that the remaining film thickness of the first-stage lower cladding layer 6 was 1 μm, and the second-stage crystal growth was performed. About flatness, it was 0.5 micrometer or less like Example 1. FIG.

DH構造部分の再成長は実施例1と全く同様の手順で行った。こちらの場合も同条件で作製し、ポリッシュ工程の無いエピタキシャルウェーハとLEDの輝度で比較した。組成勾配層16を挿入したがポリッシュしなかったものについては、2800ミリカンデラであったのに対して、ポリッシュを行い、二段階成長したものでは3700ミリカンデラと高輝度であった。これらの結果は、組成勾配層16を成長後その表面をポリッシュすることにより、格子ミスマッチの影響で発生したヒロックや結晶欠陥の影響をその後の結晶成長に伝播させないことができたためだと思われる。   The DH structure portion was regrown in the same procedure as in Example 1. In this case, the same conditions were used, and the brightness of the epitaxial wafer without the polishing process and the brightness of the LED were compared. When the composition gradient layer 16 was inserted but not polished, it was 2800 millicandelas, whereas when it was polished and grown in two stages, the brightness was as high as 3700 millicandelas. These results are thought to be because the effect of hillocks and crystal defects generated due to the lattice mismatch could not be propagated to the subsequent crystal growth by polishing the surface of the composition gradient layer 16 after growth.

GaP基板と格子ミスマッチの存在するバッファ層を成長後、一旦その表面をポリッシュした後に再度DH構造部分の結晶成長を行うことにより、結晶性の良好なDH構造部分が得られ、そのようなエピタキシャルウェーハを使用してLEDを作製した場合には従来にない高輝度のLEDを得ることができる。   After growing a buffer layer having a lattice mismatch with the GaP substrate, once polishing the surface, crystal growth of the DH structure portion is performed again to obtain a DH structure portion with good crystallinity. Such an epitaxial wafer When an LED is manufactured using the above, an unprecedented high brightness LED can be obtained.

本発明によるエピタキシャルウェーハの構造の一例を示す図である。It is a figure which shows an example of the structure of the epitaxial wafer by this invention. 本発明による組成勾配層を含むエピタキシャルウェーハの構造の一例を示す図である。It is a figure which shows an example of the structure of the epitaxial wafer containing the composition gradient layer by this invention. 従来のGaAs基板を使用したエピタキシャルウェーハの構造を示す図である。It is a figure which shows the structure of the epitaxial wafer which uses the conventional GaAs substrate.

符号の説明Explanation of symbols

1 電極
2 p−GaInPコンタクト層
3 p−AlGaInP上部クラッド層
4 p−GaInP活性層
5 n−AlGaInP下部クラッド層
6 n−AlGaInP第一段下部クラッド層
7 n−GaPバッファ層
8 Sドープn−GaP基板
9 電極
12 p−GaAsコンタクト層
16 n−AlGaInP組成勾配層
17 n−GaAsバッファ層
18 Siドープn−GaAs基板
DESCRIPTION OF SYMBOLS 1 Electrode 2 p-GaInP contact layer 3 p-AlGaInP upper cladding layer 4 p-GaInP active layer 5 n-AlGaInP lower cladding layer 6 n-AlGaInP first stage lower cladding layer 7 n-GaP buffer layer 8 S-doped n-GaP Substrate 9 Electrode 12 p-GaAs contact layer 16 n-AlGaInP composition gradient layer 17 n-GaAs buffer layer 18 Si-doped n-GaAs substrate

Claims (2)

GaP化合物半導体基板上に、GaPバッファ層、AlGaInP第一段下部クラッド層、能動層としてAlGaInP下部クラッド層、AlGaInP活性層、AlGaInP上部クラッド層のダブルヘテロ構造を有するエピタキシャルウェーハの製造方法であって、前記GaP化合物半導体基板上に前記GaPバッファ層を成長させ、その上に前記AlGaInP第一段下部クラッド層を成長させた後に、この前記AlGaInP第一段下部クラッド層表面をポリッシュし、その後、前記AlGaInP下部クラッド層、前記GaInP活性層、前記AlGaInP上部クラッド層のエピタキシャル成長を順次行うことを特徴とする発光ダイオード用途のエピタキシャルウェーハの製造方法。 A method of manufacturing an epitaxial wafer having a double heterostructure of a GaP buffer layer, an AlGaInP first-stage lower cladding layer, an AlGaInP lower cladding layer, an AlGaInP active layer, and an AlGaInP upper cladding layer on a GaP compound semiconductor substrate, After the GaP buffer layer is grown on the GaP compound semiconductor substrate and the AlGaInP first-stage lower cladding layer is grown thereon, the surface of the AlGaInP first-stage lower cladding layer is polished, and then the AlGaInP An epitaxial wafer manufacturing method for light-emitting diodes, comprising epitaxially growing a lower clad layer, the GaInP active layer, and the AlGaInP upper clad layer sequentially. 前記GaPバッファ層と前記AlGaInP第一段下部クラッド層との間に、前記GaP化合物半導体基板の格子定数から能動層の格子定数まで格子定数が連続的に変化するAlGaInP組成勾配層を成長させることを特徴とする請求項1に記載の発光ダイオード用途のエピタキシャルウェーハの製造方法。 An AlGaInP composition gradient layer having a lattice constant that continuously changes from the lattice constant of the GaP compound semiconductor substrate to the lattice constant of the active layer is grown between the GaP buffer layer and the AlGaInP first-stage lower cladding layer. The manufacturing method of the epitaxial wafer for light emitting diode uses of Claim 1 characterized by the above-mentioned.
JP2006315028A 2006-11-22 2006-11-22 Method for manufacturing epitaxial wafer Pending JP2007123913A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010087264A (en) * 2008-09-30 2010-04-15 Toyoda Gosei Co Ltd Semiconductor device manufacturing method
CN113594243A (en) * 2021-07-21 2021-11-02 电子科技大学 Gradient polarization doped enhanced GaN longitudinal field effect transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010087264A (en) * 2008-09-30 2010-04-15 Toyoda Gosei Co Ltd Semiconductor device manufacturing method
CN113594243A (en) * 2021-07-21 2021-11-02 电子科技大学 Gradient polarization doped enhanced GaN longitudinal field effect transistor

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