JP2007110047A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which can improve the electrical property of a power MOSFET of trench structure. <P>SOLUTION: While rotating a substrate 1, ion implantation of impurities is carried out to an epitaxial layer 2 from an oblique direction with a predetermined angle from the normal line of the surface of the epitaxial layer 2, to form a second channel region 9 having desired impurity concentration distribution in the epitaxial layer 2 of the side wall of a gate trench 5. Then, a gate insulating film is formed in the inner surface of the gate trench 5. Further, a conductive film is embedded in the gate trench 5, and a gate electrode composed of the conductive film is formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a manufacturing method of a trench common drain common field effect transistor (hereinafter referred to as a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor)). is there.

  Power devices are used, for example, for switching regulators used for stabilized power supplies of electronic devices, charging circuits for notebook personal computers or mobile phones, backlight control for liquid crystal panels, and the like, and their applications are rapidly expanding in recent years. In particular, power MOSFETs can achieve higher switching speed and lower loss than other power devices such as bipolar transistors, and can be expected to improve performance by manufacturing using the latest semiconductor manufacturing technology. Therefore, it is attracting attention as a power device that can meet the needs of the market.

For example, the structure and electrical characteristics of a power MOSFET, and application examples of the power MOSFET to a switching power supply and a periodic rectifier circuit have been reported (for example, see Non-Patent Document 1).
Issued by Transistor Technology Editorial Department, "Practical application of power MOSFET", December 1, 2000

  For example, the on-resistance that occupies a steady loss at the on-time has been improved by miniaturizing a structural unit called a cell. However, since a power MOSFET is required to have a large current capacity, there is a limit to miniaturization thereof, and various devices have been made to further reduce the on-resistance. Therefore, the present inventor examined a technique for reducing the on-resistance by, for example, replacing the planar structure with a trench structure and optimizing the power MOSFET structure. As one of the results of the study, it became clear that optimization of the impurity concentration distribution in the channel region formed on the sidewall of the trench is an effective method for further improving the electrical characteristics of the power MOSFET. It was. However, it is technically difficult to control the impurity concentration of only the side wall of the trench, and there remains a technical problem regarding a method for manufacturing a power MOSFET to achieve this.

  An object of the present invention is to provide a technique capable of improving the electrical characteristics of a power MOSFET having a trench structure.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate groove in an epitaxial layer after forming an epitaxial layer on the surface of the semiconductor substrate, and a predetermined line from the normal of the surface of the epitaxial layer while rotating the semiconductor substrate. Impurities are ion-implanted into the epitaxial layer on the sidewall of the gate trench from an oblique direction to form a channel region having a desired impurity concentration distribution, and then a gate insulating film is formed on the inner surface of the gate trench And a step of embedding a conductive film in the gate groove and forming a gate electrode made of the conductive film.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By controlling the impurity concentration distribution in the channel region, the electrical characteristics of the power MOSFET having the trench structure can be improved.

  In this embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Some or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in this embodiment, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified, or in principle limited to a specific number in principle. The number is not limited to the specific number, and may be a specific number or more. Further, in the present embodiment, the constituent elements (including element steps and the like) are not necessarily essential unless particularly specified and apparently essential in principle. Yes. Similarly, in this embodiment, when referring to the shape, positional relationship, etc. of the component, etc., the shape, etc. substantially, unless otherwise specified, or otherwise considered in principle. It shall include those that are approximate or similar to. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals in principle, and the repeated description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  A method of manufacturing a power MOSFET having a trench structure according to an embodiment of the present invention will be described in the order of steps with reference to FIGS. In the present embodiment, a method for manufacturing an n-channel power MOSFET (hereinafter abbreviated as a power nMOS) is illustrated.

First, as shown in FIG. 1, a semiconductor substrate (semiconductor wafer processed into a circular thin plate) 1 made of, for example, n ⁺ type single crystal silicon is prepared. Subsequently, after an n-type epitaxial layer 2 having a desired thickness is formed on the surface of the semiconductor substrate 1 by epitaxial growth, p-type impurities such as boron are ion-implanted into the epitaxial layer 2, and further heat treatment is performed on the semiconductor substrate 1. Is applied to activate the p-type impurity to form the p ⁻ -type first channel region 3.

  Next, as shown in FIG. 2, after the silicon oxide film 4 is formed on the surface of the epitaxial layer 2, the silicon oxide film 4 and the epitaxial layer 2 are sequentially processed by a dry etching method using the resist pattern as a mask. A gate groove 5 penetrating the one channel region 3 is formed.

  Next, as shown in FIG. 3, after an insulating film 6 is formed on the surface of the epitaxial layer 2 including the inner surface of the gate groove 5, a p-type impurity, for example, boron is ion-implanted into the epitaxial layer 2 which becomes an element isolation region. Then, an n-type impurity such as phosphorus or arsenic is ion-implanted into the epitaxial layer 2 that becomes the source region. Subsequently, while the semiconductor substrate 1 is rotated, impurities are ion-implanted into the epitaxial layer 2 on the side wall of the gate groove 5 from the oblique direction with the inclination from the normal of the surface of the epitaxial layer 2 as an angle θ (hereinafter, angle ion implantation). ). The ion species for the angle ion implantation may be an n-type impurity (for example, phosphorus or arsenic) or a p-type impurity (for example, boron or boron fluoride), and the ion species, dose, and implantation energy are as desired for the power nMOS. It is selected according to the electrical characteristics. Also, impurities can be introduced into the epitaxial layer 2 on the side wall of the gate groove 5 by rotating the semiconductor substrate 1 and performing angle ion implantation. In the ion implantation or angle ion implantation, impurities are introduced into a desired region, and other regions that are not desired are covered with, for example, a resist pattern.

Thereafter, the semiconductor substrate 1 is subjected to a heat treatment to activate the p-type impurity and the n-type impurity implanted into the epitaxial layer 2 by the ion implantation or angle ion implantation. As a result, an n ⁺ type source region 8 is formed around the gate groove 5 on the surface of the epitaxial layer 2, and a p ⁺ type element isolation region 7 is formed around the source region 8 on the surface of the epitaxial layer 2. The second channel region 9 is formed in the epitaxial layer 2 on the side wall 5. Here, since the second channel region 9 having a desired impurity concentration distribution can be formed in the epitaxial layer 2 on the side wall of the gate groove 5, the electrical characteristics of the power nMOS can be improved.

  Next, as shown in FIG. 4, after the insulating film 6 is removed, the insulating film 10 is formed on the surface of the epitaxial layer 2 including the inner surface of the gate groove 5 by, for example, a CVD (Chemical Vapor Deposition) method. The insulating film 10 formed on the inner surface of the gate groove 5 functions as a gate insulating film, and is made of, for example, a silicon oxide film or a silicon nitride film. Subsequently, a conductive film 11a, for example, a polycrystalline silicon film is deposited on the insulating film 10 by, for example, a CVD method. The conductive film 11a is formed by filling the inside of the gate trench 5.

  Next, as shown in FIG. 5, the gate electrode 11 is formed by polishing the conductive film 11 a by, for example, CMP (Chemical Mechanical Polishing) to leave the conductive film 11 a inside the gate groove 5. Subsequently, after the interlayer insulating film 12 is formed on the epitaxial layer 2, the interlayer insulating film 12 is processed by a dry etching method using the resist pattern as a mask to form the connection hole 13 reaching the source region 8 and the gate electrode 11. Form.

  Next, after depositing a metal film, for example, an aluminum film or an alloy film containing aluminum as a main component on the epitaxial layer 2 including the inside of the connection hole 13, the metal film is processed by a dry etching method using a resist pattern as a mask. Thus, the wiring 14 is formed. Further, a passivation film 15 that covers the wiring 14 is formed.

Next, as shown in FIG. 6, the back surface of the semiconductor substrate 1 is ground to thin the semiconductor substrate 1 to a predetermined thickness, thereby forming an n ⁺ -type drain 16. The drain 16 is formed in common in a plurality of power MOSFETs. Thereafter, a metal film, for example, an aluminum film or an alloy film containing aluminum as a main component is deposited on the back surface of the semiconductor substrate 1 by, for example, a sputtering method to form the back electrode 17 made of the metal film. Thereby, the power nMOS is substantially completed.

  As described above, according to the present embodiment, after forming the gate groove 5, a channel region having a desired impurity concentration distribution can be formed by introducing impurities into the epitaxial layer 2 on the side wall of the gate groove 5. The electrical characteristics of the power nMOS can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the present invention is applied to an n-channel type power MOSFET has been described. However, the present invention can also be applied to a p-channel type power MOSFET, and the same effect can be obtained.

  The power MOSFET having a trench structure according to the present invention can be applied to a power supply unit of an electronic device that particularly requires lightness, shortness, and high performance.

It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of power MOSFET of the trench structure which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of power MOSFET of the trench structure which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of power MOSFET of the trench structure which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of power MOSFET of the trench structure which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of power MOSFET of the trench structure which is one embodiment of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing process of power MOSFET of the trench structure which is one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Epitaxial layer 3 1st channel region 4 Silicon oxide film 5 Gate groove 6 Insulating film 7 Element isolation region 8 Source region 9 Second channel region 10 Insulating film 11 Gate electrode 11a Conductive film 12 Interlayer insulating film 13 Connection hole 14 Wiring 15 Passivation film 16 Drain 17 Back electrode

Claims (3)

A method of manufacturing a semiconductor device having the following steps;
(A) forming a first conductivity type epitaxial layer on a surface of a first conductivity type semiconductor substrate;
(B) ion-implanting a second conductivity type impurity different from the first conductivity type into the epitaxial layer to form a first channel region;
(C) forming a gate groove through the first channel region in the epitaxial layer;
(D) forming a source region by ion-implanting a first conductivity type impurity around the gate groove on the surface of the epitaxial layer;
(E) Impurities are ion-implanted into the epitaxial layer on the side wall of the gate trench from a diagonal direction at a predetermined angle from the normal line of the surface of the epitaxial layer while rotating the semiconductor substrate, Forming a step;
(F) after the step (e), forming a gate insulating film on the inner surface of the gate groove;
(G) After the step (f), a step of embedding a conductive film in the gate groove to form a gate electrode made of the conductive film;
(H) after the step (g), forming an interlayer insulating film on the epitaxial layer, and forming a connection hole reaching the source region and the gate electrode in the interlayer insulating film;
(I) forming a wiring electrically connected to the source region and the gate electrode through the connection hole;
(J) forming a passivation film covering the wiring;
(K) A step of grinding the back surface of the semiconductor substrate so that the semiconductor substrate has a predetermined thickness and then forming a back electrode on the back surface of the semiconductor substrate.   2. The method of manufacturing a semiconductor device according to claim 1, wherein an impurity concentration of the first channel region is different from an impurity concentration of the second channel region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein, prior to the step (e),
(L) A method of manufacturing a semiconductor device, further comprising a step of ion-implanting a second conductivity type impurity around the source region on the surface of the epitaxial layer to form an element isolation region.

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