JP2007088779A - Transmitting/receiving system and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transmitting/receiving system and method using an OFDM modulation/demodulation system by which circuit scale is sharply reduced. <P>SOLUTION: In the transmitting/receiving system 10 using the OFDM demodulation system, a predetermined module in a module group of a modulation system and a predetermined module in a module group of a demodulation system serve as a commonized module. For example, a scrambler 51 and a descrambler 61 are commonized to be considered as a scrambler/descrambler 11, mapping 54 and demapping 64 are commonized to serve as mapping/demapping 14, symbol control 55 and frame control 65 are commonized to serve as symbol control/frame control 15 and IFFT 56 and FFT 66 are commonized to serve as IFFT/FFT 16. The transmitting/receiving system 10 is implemented on a processing platform 20. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a transmission / reception system and method using an orthogonal frequency division multiplexing (OFDM) modulation / demodulation scheme.

  The OFDM modulation / demodulation method is one of digital modulation methods, and is a method of increasing frequency utilization efficiency by arranging subcarriers orthogonally on the frequency axis. Conventionally, it has been adopted in European digital broadcasting system (Digital Video Broadcasting terminal: DVB-T), Japanese DVB system (Band Segment Transmission) -OFDM system, and IEEE 802.11a wireless LAN system (see Non-Patent Document 1). ).

  FIG. 10A shows a conventional OFDM modulation circuit 50, and FIG. 10B shows a conventional OFDM demodulation circuit 60. As shown in FIG. 10A, a conventional OFDM modulation circuit 50 includes a scrambler 51, a convolutional coding 52, an interleaver 53, a mapping 54, a symbol control 55, and an inverse fast Fourier transform (IFFT). ) It is configured in the order of 56 modules.

  The scrambler 51 randomizes the digital signal according to a desired rule (for example, a pseudo random number sequence) and creates random transmission data. The convolutional encoding 52 performs convolutional encoding for error correction on the transmission data. The interleaver 53 changes the position of the bit sequence in order to convert the burst error into a random error. The mapping 54 performs mapping to a desired modulation scheme (such as a QPSK modulation scheme). The symbol control 55 constitutes a frame from a predetermined number of symbols and a guard interval. The IFFT 56 converts orthogonal subcarriers into a time axis signal by IFFT processing.

  As shown in FIG. 10B, the conventional OFDM demodulation circuit 60 includes a fast Fourier transform (FFT) 66, a frame control 65, a demapping 64, a deinterleaver 63, a Viterbi decoding 62, and a desk. The modules are arranged in the order of the modules of the Rambler 61.

  The FFT 66 removes the guard interval portion and converts the orthogonal subcarriers into frequency axis signals again by FFT processing. The frame control 65 extracts a predetermined number of symbols from the frame. The demapping 64 performs data demapping according to a desired modulation method. The deinterleaver 53 performs the reverse operation of replacing the position of the bit sequence. The Viterbi decoding 62 decodes the convolutional code using the Viterbi algorithm. The descrambler 61 restores the data by randomizing according to a desired rule.

Takuro Sato, “From Basics to Applications of OFDM Technology”, published on November 30, 1999, Realize Inc.

  As described above, the conventional OFDM demodulation circuit 50 and the OFDM demodulation circuit 60 have a signal processing unit having symmetry. For this reason, there may be a common functional part in signal processing such as a data path control circuit. However, in the conventional OFDM modulation / demodulation circuit, since the OFDM demodulation circuit 50 and the OFDM demodulation circuit 60 are configured separately, there is a problem that the circuit scale increases.

  Accordingly, an object of the present invention is to provide a transmission / reception system and method using an OFDM modulation / demodulation method that can reduce the circuit scale significantly.

  The transmission / reception system according to the present invention is a transmission / reception system using an orthogonal frequency division multiplexing modulation / demodulation system, wherein a predetermined module in a modulation system module group and a predetermined module in a demodulation system module group are shared. It is characterized by.

  Here, in the transmission / reception system of the present invention, the predetermined module in the modulation module group is a scrambler module that scrambles input data, and the predetermined module in the demodulation system module group that is shared with the scrambler module. These modules can be descrambler modules that descramble input data.

  Here, in the transmission / reception system of the present invention, the predetermined module in the module group of the modulation system is a mapping module that maps input data to a signal of a predetermined multi-level modulation scheme, and is shared with the mapping module. A predetermined module in the module group of the demodulation system can be a demapping module that demappings an input signal to binary data.

  Here, in the transmission / reception system according to the present invention, the predetermined module in the modulation system module group inserts a guard interval into the input signal to form one symbol, and performs symbol control for forming a frame from a predetermined number of the symbols. A predetermined module in the module group of the demodulation system that is a module and is shared with the symbol control module can be a frame control module that extracts a symbol from a framed input signal.

Here, in the transmission / reception system of the present invention, the predetermined module in the modulation system module group is an inverse fast Fourier transform module that performs an inverse fast Fourier transform process on the input signal to convert the input signal into a signal on a time axis. The predetermined module in the demodulator module group shared with the fast Fourier transform module may be a fast Fourier transform module that performs fast Fourier transform processing on the input signal to convert it to a signal on the frequency axis.
Here, in the transmission / reception system according to the present invention, the predetermined module in the modulation system module group is a convolutional coding module that performs convolutional coding on an input signal, and the demodulation system shared with the convolutional coding module is used. The predetermined module in the module group can be a Viterbi decoding module that decodes an input signal using a Viterbi algorithm.
Here, in the transmission / reception system according to the present invention, the predetermined module in the modulation system module group is an interleaver module that replaces the position of a bit sequence with respect to an input signal, and the demodulation system shared with the interleaver module The predetermined module in the group of modules can be a deinterleaver module that performs the reverse operation of replacing the position of the bit sequence with respect to the input signal.

  Here, the transmission / reception system of the present invention further includes a processing platform for performing processing indicated by a data packet including input data, and the processing platform is provided according to the processing contents of the modulation system or the demodulation system. Using a routing table indicating a packet input source and an output destination for the next processing, a data packet input from the input source is output to the output destination to perform modulation or demodulation processing A switching module that controls the order of processing of the modulation system or the demodulation system, and a processing module that is an input source and an output destination of the routing table and is assigned as the common module, the switching module side For data packets sent from the, indicated by the data packet A plurality of input / output buffers connected to the switching module and buffering the data packets, wherein the data packets are sent to the switching module by performing modulation or demodulation processing; The input buffer buffers data packets input from the routing table input source to the switching module, and the output buffer buffers data packets output from the switching module side to the routing table output destination. The processing platform is configured by arbitrarily combining the switching module and the processing module via a set of input / output buffers, and at least one switching module. The module When there are a plurality of switching modules connected to the outside of the platform through corresponding input / output buffers, the routing table indicates the sharing of the modulation system or demodulation system processing in each switching module. Provided for each module, the switching module inputs a data packet from the outside of the processing platform, from the processing module or another switching module via a corresponding input buffer, and is indicated by the data packet. A routing process for outputting the data packet to an output destination corresponding to an output destination based on a routing table corresponding to a modulation system or a demodulation system to be processed, and the processing module is connected to the switching module. A modulation or demodulation process indicated by the data packet sent through the corresponding output buffer is performed on the data packet, and the data packet is sent to the corresponding output buffer and a set of input buffers. To the switching module side, and the other switching module is the other according to the processing of the modulation system or the demodulation system indicated by the data packet sent from the switching module via the corresponding output buffer. The routing table for the switching module is used to perform routing processing on the data packet, and the data packet is sent to the switching module side via the corresponding output buffer and a pair of input buffers. be able to.

  Here, in the transmission / reception system according to the present invention, the processing module processes the data packet by using a parameter table for each processing module indicating a modulation system or a demodulation system process according to the input data packet. Can be output.

  Here, in the transmission / reception system of the present invention, the parameter packet including the identifier of the processing module input from outside the processing platform and the contents of the parameter table of the processing module is sent to the processing module specified by the identifier. By transmitting based on a predetermined condition, the contents of the parameter table can be dynamically rewritten.

  The transmission / reception method of the present invention is a transmission / reception method using an orthogonal frequency division multiplexing modulation / demodulation system, and is characterized in that predetermined processing in the modulation system and predetermined processing in the demodulation system are made common.

  Here, in the transmission / reception method of the present invention, the predetermined process in the modulation system is a scrambler process that scrambles input data, and the predetermined process in the demodulation system that is shared with the scrambler process is a descrambling process for the input data. Descrambler processing can be performed.

  Here, in the transmission / reception method of the present invention, the predetermined process in the modulation system is a mapping process for mapping input data to a signal of a predetermined multilevel modulation scheme, and the predetermined process in the demodulation system shared with the mapping process is performed. The process can be a demapping process in which an input signal is demapped to binary data.

  Here, in the transmission / reception method of the present invention, the predetermined process in the modulation system is a symbol control process in which a guard interval is inserted into an input signal to form one symbol and a frame is formed from a predetermined number of the symbols. The predetermined process in the demodulation system that is shared with the symbol control process can be a frame control process for extracting a symbol from a framed input signal.

Here, in the transmission / reception method of the present invention, the predetermined process in the modulation system is an inverse fast Fourier transform process in which an inverse fast Fourier transform process is performed on the input signal to convert the input signal into a signal on the time axis. The predetermined process in the demodulation system that is shared with the process can be a fast Fourier transform process in which a fast Fourier transform process is performed on the input signal to convert the signal into a signal on the frequency axis.
Here, in the transmission / reception method of the present invention, the predetermined process in the modulation system is a convolutional encoding process for performing convolutional encoding on an input signal, and the predetermined process in the demodulation system that is shared with the convolutional encoding process Can be a Viterbi decoding process for decoding an input signal using a Viterbi algorithm.
Here, in the transmission / reception method of the present invention, the predetermined process in the modulation system is an interleaver process for exchanging the position of a bit sequence with respect to an input signal, and the predetermined process in the demodulation system shared with the interleaver process is A deinterleaver process can be performed in which an operation reverse to the above-described replacement of the position of the bit sequence is performed on the input signal.

  According to the transmission / reception system using the OFDM modulation / demodulation system of the present invention, in the transmission / reception system using the OFDM modulation / demodulation system, the predetermined module in the modulation module group and the predetermined module in the demodulation module group are shared. Module. For example, the scrambler 51 and the descrambler 61 can be used as a scrambler / descrambler, the mapping 54 and the demapping 64 can be used as a mapping / demapping, and the symbol control 55 The frame control 65 can be used as a symbol control / frame control, and the IFFT 56 and the FFT 66 can be used as an IFFT / FFT. As a result, the same functions as those of the conventional OFDM modulation circuit 50 and OFDM demodulation circuit 60 can be executed by half of the processing modules except for the overhead for processing switching, etc., so that the circuit scale can be greatly reduced. There is an effect that a transmission / reception system using a modulation / demodulation method can be provided.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. In the following, for convenience of explanation, the components of FIGS. 10A and 10B described in the background art are referred to as necessary.

  FIG. 1 shows a transmission / reception system 10 using an OFDM modulation / demodulation method according to a first embodiment of the present invention. In the transmission / reception system 10, a predetermined module in a modulation system module group (scrambler 51 to IFFT 56 shown in FIG. 10A) and a demodulation system module group (descrambler 61 to FFT 66 shown in FIG. 10B). It is possible to make the predetermined module in the module common.

  In the transmission / reception system 10, the predetermined module in the modulation system module group is a scrambler 51 (scrambler module) that scrambles input data, and the predetermined module in the demodulation system module group shared with the scrambler 51. Can be a descrambler 61 (descrambler module) that descrambles input data. The module shared in this way is the scrambler / descrambler 11 shown in FIG. In the scrambler / descrambler 11, for example, a data path control circuit, a scramble / descramble processing engine, and the like can be shared hardware. A specific circuit example will be described in detail in the second embodiment.

  In the transmission / reception system 10, the predetermined module in the modulation system module group is a mapping 54 (mapping module) that maps input data to a signal of a predetermined multi-level modulation scheme. The predetermined module in the module group may be a demapping 64 (demapping module) that demappings an input signal into binary data. The module thus shared is the mapping / demapping 14 shown in FIG. In the mapping / demapping 14, for example, the data path control circuit, the input / output data rate adjustment buffer, and the like can be shared hardware. A specific circuit example will be described in detail in the second embodiment.

  In the transmission / reception system 10, a predetermined module in the modulation system module group inserts a guard interval into an input signal to form one symbol, and a symbol control 55 (symbol control module) that performs framing of a frame from a predetermined number of the symbols. The predetermined module in the demodulating module group shared with the symbol control 55 can be a frame control 65 (frame control module) for extracting symbols from the framed input signal. The module shared in this way is the symbol control / frame control 15 shown in FIG. In the symbol control / frame control 15, for example, a data path control circuit, a work buffer, and the like can be shared hardware. A specific circuit example will be described in detail in the second embodiment.

  In the transmission / reception system 10, the predetermined module in the modulation system module group is an IFFT 56 (inverse fast Fourier transform module) that performs IFFT processing on an input signal to convert it into a signal on the time axis, and the demodulation that is shared with the IFFT 56. The predetermined module in the system module group may be an FFT 66 (Fast Fourier Transform Module) that performs FFT processing on the input signal and converts it to a signal on the frequency axis. The module thus shared is the IFFT / FFT 16 shown in FIG. In the IFFT / FFT 16, for example, a data path control circuit, an input buffer, an output buffer, and the like can be shared hardware. A specific circuit example will be described in detail in the second embodiment.

  There is no particular symmetry in signal processing between the convolutional coding 52 in the modulation system module group and the Viterbi decoding 62 in the demodulation system module group, but in the encoding process and part of the decoding process. The work buffer register is shared. Therefore, in the convolutional encoding / Viterbi decoding 12 shown in FIG. 1, the convolutional encoding 52 (convolutional encoding module) and the Viterbi decoding 62 (Viterbi decoding module) share the work buffer register. However, it may be configured to be arranged in parallel. Similarly, although there is no particular symmetry in signal processing between the interleaver 53 and the deinterleaver 63 in the modulation system module group, the working buffer register is set in a part of the interleave processing and deinterleave processing. Shared. For this reason, in the interleaver / deinterleaver 13 shown in FIG. 1, the interleaver 53 (interleaver module) and the deinterleaver 63 (deinterleaver module) share a work buffer register in parallel. Therefore, the configuration may be arranged in a regular manner.

  The transmission / reception method using the OFDM modulation / demodulation method described above is a process in which a predetermined process in the modulation system and a predetermined process in the demodulation system are made common. Here, the predetermined process in the modulation system is a scrambler process (corresponding to the process of the scrambler 51), and the predetermined process in the demodulation system shared with the scrambler process is a descrambler process (of the descrambler 61). Equivalent to processing). Further, the predetermined process in the modulation system is a mapping process (corresponding to the process of mapping 54), and the predetermined process in the demodulation system shared with the mapping process is a demapping process (corresponding to the process of demapping 64). It can be. The predetermined process in the modulation system is a symbol control process (corresponding to the process of the symbol control 55), and the predetermined process in the demodulation system shared with the symbol control process is a frame control process (corresponding to the process of the frame control 65). ). The predetermined processing in the modulation system is IFFT processing (corresponding to the processing of IFFT 56), and the predetermined processing in the demodulation system shared with the IFFT processing can be FFT processing (corresponding to processing of FFT 66). The predetermined process in the modulation system is a convolutional coding process (corresponding to the process of the convolutional coding 52), and the predetermined process in the demodulation system shared with the convolutional coding process is a Viterbi decoding process (Viterbi decoding process). Equivalent to the process 62). The predetermined process in the modulation system is an interleaver process (corresponding to the process of the interleaver 53), and the predetermined process in the demodulation system shared with the interleaver process is a deinterleaver process (deinterleaver process). Equivalent to the processing of the leaver 63).

  As described above, according to the first embodiment of the present invention, in the transmission / reception system 10 using the OFDM modulation / demodulation method, the predetermined module in the modulation system module group (scrambler 51 to IFFT 56 described in the background art), and the demodulation system A predetermined module in the module group (descrambler 61 to FFT 66 described in the background art) can be used as a common module. For example, the scrambler 51 and the descrambler 61 can be used in common as the scrambler / descrambler 11, the mapping 54 and the demapping 64 can be used in common as the mapping / demapping 14, and symbol control can be performed. 55 and the frame control 65 can be used as a symbol control / frame control 15, and IFFT 56 and FFT 66 can be used as an IFFT / FFT 16. As a result, the same functions as those of the conventional OFDM modulation circuit 50 and OFDM demodulation circuit 60 can be executed by half of the processing modules except for the overhead for processing switching, etc., so that the circuit scale can be greatly reduced. A transmission / reception system using a modulation / demodulation method can be provided.

  The transmission / reception system 10 described above can be implemented on a desired processing platform. In the second embodiment, a specific processing platform will be described first, and then each processing module implemented on the processing platform will be described.

  FIG. 2 shows a processing platform 20 according to the second embodiment of the present invention. In FIG. 2, reference numeral 21 denotes a hardware interface (I / F) having a function of inputting / outputting data packets to / from the outside of the processing platform 20, and 30 is connected to the hardware I / F 21 to control the order of signal processing. The switching modules ISM1 and 22 are connected to the switching module ISM1 (30) and are one of processing modules for performing various processing on the data packet. The scrambler to which the function of the scrambler / descrambler 11 is assigned. / Descrambler processing module 23 is one of the processing modules connected to the switching module ISM1 (30), and is a convolution / Viterbi decoding processing module 24 to which the function of convolutional encoding / Viterbi decoding 12 is assigned. Is the switching module ISM Is an interleaver / deinterleaver processing module assigned with the function of the interleaver / deinterleaver 13, 25 is connected to the switching module ISM2 (31) One of the processing modules, a mapping / demapping processing module to which the function of mapping / demapping 14 is assigned, and 26 is one of the processing modules connected to the switching module ISM3 (32), A symbol control / frame control processing module 27 to which the function of the frame control 15 is assigned, 27 is one of processing modules connected to the switching module ISM3 (32), and an inverse to which the function of the inverse FFT / FFT 16 is assigned. It is a FT / FFT processing module.

  As shown in FIG. 2, between the hardware I / F 21 and the switching module ISM1 (30), a path dp1 for data packets (black arrow) and a path pp1 for parameter packets (described later) (outlined) And a path dp22-in and dp22-out for data packets (both are black arrows) and a parameter packet between the switching module ISM1 (30) and the scrambler / descrambler processing module 22 And a path pp22 (open arrow). For the sake of illustration, the other paths are not labeled, but the black arrow is a data packet path, and the white arrow path is a parameter packet path. Another switching module ISM2 (31) is connected to the switching module ISM1 (30) via an interface (not shown). An interleaver / deinterleaver processing module 24 and a mapping / demapping processing module 25 are connected to the switching module ISM2 (31), and another switching module ISM3 (32) is connected via an interface (not shown). ing. A symbol control / frame control processing module 26 and an IFFT / FFT processing module 27 are connected to the switching module ISM3 (32). In FIG. 2, the processing platform 20 is composed of a combination of three switching modules ISM1 (30), ISM2 (31) and ISM3 (32) and six processing modules 22, etc. This is an example. Thus, the processing platform 20 can be configured by a combination of an arbitrary number of switching modules ISM1 (30) and the like and an arbitrary number of processing modules 22 and the like.

  The switching module ISM1 (30) is provided according to the processing contents of the modulation system or the demodulation system, and uses the routing table 36 indicating the input source of the data packet and the output destination for the next processing, to By outputting the data packet input from the beginning to the output destination and performing the modulation system or the demodulation system, the order of the modulation system or the demodulation system can be controlled. The switching module ISM2 (31) and the switching module ISM3 (32) can similarly control the order of processing using the routing tables 37 and 38, respectively.

  The processing module 22 or the like that is an input source and an output destination indicated by the routing table 36 or the like and is assigned as the above-described common module is used for the data packet sent from the switching module ISM1 (30) side or the like. The data packet is sent to the switching module ISM1 (30) side by performing the modulation system or the demodulation system indicated by the data packet.

  As shown in FIG. 2, a plurality of input buffers 33c and 33d for buffering data packets and a plurality of output buffers 33a and 33b are connected to the switching module ISM1 (30), and the switching module ISM2 A plurality of input buffers 34c and 33d and a plurality of output buffers 34a and 34b are connected to (31), and a plurality of sets of input buffers 35c and 35d and a plurality of output buffers 35a are connected to the switching module ISM3 (32). And 35b are connected. The input buffer 33d and the like buffer data packets input from the input source indicated by the routing table 36 and the like to the switching module ISM1 (30) and the like, and the output buffer 33a and the like are indicated by the routing table 36 and the like. The data packet output from the switching module ISM1 (30) etc. to the output destination is buffered. In FIG. 2, the input buffer 33d and the like and the output buffer 33a and the like have one block (the capacity is arbitrary, but it is assumed to have a capacity of at least one data packet). However, this is an example, and the input buffer 33d and the output buffer 33a and the like can have an arbitrary number of blocks. When the buffer has a plurality of blocks, data packets are controlled by FIFO (First-In First-Out). Hereinafter, when both the input buffer and the output buffer are referred to, they are referred to as “input / output buffers”. In FIG. 2, an input / output buffer is not shown between the switching module ISM1 (30) and the switching module ISM2 (31), but this is omitted for convenience of the drawing, and the switching module ISM. An input / output buffer having an arbitrary number of blocks can be provided between them.

  The processing platform 20 can be configured by arbitrarily combining the switching module ISM1 (30) and the processing module 22 and the like via a pair of input / output buffers 33d and 33a that correspond to each other. In this case, at least one switching module, for example, ISM1 (30) is connected to the outside of the processing platform 20 (hardware I / F 21) via an input / output buffer (not shown). When the processing platform 20 has a plurality of switching modules ISM1 (30), etc., the routing table 36, etc., indicates that each switching module ISM1 (30) etc. indicates the sharing of modulation system or demodulation system processing. -It is provided for each module ISM1 (30).

  The switching module ISM1 (30) or the like receives data packets from the processing platform 20 (hardware I / F 10), the processing module 22 or the like, or another switching module ISM2 (31) via the corresponding input buffer. input. Next, the routing table 36 or the like corresponding to the modulation or demodulation processing indicated by the data packet is selected, the output destination is obtained based on the routing table 36 or the like, and the output corresponding to the output destination Routing processing for outputting data packets via the buffer 33a and the like is performed. In FIG. 2, the routing process in the switching module ISM1 (30) or the like is indicated by a dotted line.

  The processing module 22 or the like receives the data packet sent from the switching module ISM1 (30) or the like via the corresponding output buffer 33a or the like. Next, the modulation or demodulation process indicated by the data packet is performed on the data packet. Thereafter, the data packet is sent to the switching module ISM1 (30) side through the input buffer 33d and the like that are paired with the corresponding output buffer 33a and the like.

  The other switching module ISM2 (31) etc. receives the data packet sent from the switching module ISM1 (30) etc. via a corresponding output buffer (not shown). Next, using the routing table 37 for the switching module ISM2 (31) corresponding to the processing of the modulation system or the demodulation system indicated by the data packet, the above routing processing is performed on the data packet. . That is, the switching module ISM2 (31) is similar to the switching module ISM1 (30), the processing module 24, etc., or another switching module ISM1 (30) or ISM3 (32) for the switching module ISM2 (31). The data packet is input through a corresponding input buffer (not shown). Next, the routing table 37 or the like corresponding to the modulation or demodulation processing indicated by the data packet is selected, the output destination is obtained based on the routing table 37 or the like, and the output corresponding to the output destination Routing processing for outputting data packets through the buffer 34a and the like is performed. Thereafter, the data packet is sent to the switching module ISM1 (30) side through an input buffer (not shown) paired with a corresponding output buffer (not shown).

  The processing module 22 or the like has a parameter table (not shown) for each processing module 22 or the like that indicates the modulation or demodulation processing according to the input data packet. The processing module 22 or the like performs processing according to the input data packet by using each parameter table, and outputs the resulting data packet.

  Each parameter table is not fixed contents, but can be initialized to arbitrary contents and dynamically rewritten later. The platform 20 inputs a parameter packet including an identifier of the processing module 22 and the like and the contents of the parameter table of the processing module 22 and the like from the outside (hardware I / F 21) via the path pp1 for the parameter packet. can do. The platform 20 dynamically transmits the contents of the parameter table by transmitting the input parameter packet to the processing module 22 identified by the identifier via the parameter packet path pp1 based on a predetermined condition. Can be rewritten. The platform 20 inputs a parameter packet from the outside (hardware I / F 21) via the data packet path dp1, and the parameter packet is specified by the identifier via the data packet path. It can also be transmitted to the processing module 22 or the like based on a predetermined condition.

  Next, each processing module 22 implemented on the processing platform 20 will be described. FIG. 3 is a block diagram showing the scrambler / descrambler processing module 22. In FIG. 3, the same reference numerals as those in FIG. As shown in FIG. 3, the scrambler / descrambler processing module 22 inputs a parameter packet from the switching module ISM1 (30) side via a parameter packet path pp22 (open arrow). The parameter packet includes contents indicating transmission (modulation) or reception (demodulation), and the parameter packet processing unit 22a sets the contents in the parameter table. The processing engine COM22, which is a common processing unit, inputs from the path dp22-in for data packets based on the contents indicating transmission (modulation) or reception (demodulation) obtained from the parameter / packet processing unit 22a. The received data is scrambled in the case of transmission, descrambled in the case of reception, and output from the data packet path dp22-out to the switching module ISM1 (30) side.

  The scrambling performed by the processing engine COM22 uses a generator polynomial G (X) as shown in Equation 1 when the bit string of data input from the data packet path dp22-in is Xj (j = 1 to 15), for example. Just do it. In Expression 1, “+” is an exclusive OR.

  Of course, any generator polynomial other than Equation 1 can be used. In the case of reception (demodulation), data is reproduced by descrambling by the same process.

  FIG. 4 is a block diagram showing the convolutional encoding / Viterbi decoding processing module 23. In FIG. 4, the same reference numerals as those in FIG. In FIG. 4, dp23-in indicates a path for data packets from the switching module ISM1 (30) side, pp23 indicates a path for parameter packets from the switching module ISM1 (30) side, and dp23- “out” indicates a path for data packets to the switching module ISM1 (30) side. As described in the first embodiment, there is no particular symmetry in signal processing between the convolutional coding 52 in the modulation module group and the Viterbi decoding 62 in the demodulation module group. The work buffer and register are shared in part of the processing and the decoding processing. For this reason, as shown in FIG. 4, in the convolutional coding / Viterbi decoding 23, the convolutional coding 52 and the Viterbi decoding 62 are arranged in parallel while sharing the work buffer register 23a. It has a configuration. Each process of the encoding process and the decoding process is executed by obtaining a necessary buffer by appropriately occupying or partially using the work buffer / register 23a. In the convolutional coding 52, when the bit string of the data input from the data packet path dp23-in is, for example, Xk (k = 1 to 6), generator polynomials G1 (X) and G2 (X) as in Expression 2 are used. May be used for convolutional coding. In Expression 2, “+” is an exclusive OR. The convolutionally encoded data is output from the data packet path dp23-out to the switching module ISM1 (30) side.

  Of course, any generator polynomial other than Equation 2 can be used. In the case of reception (demodulation), the Viterbi decoding 62 decodes the convolutional code using the Viterbi algorithm to the data input from the data packet path dp23-in, and the switching module from the data packet path dp23-out. Output to the ISM1 (30) side.

  FIG. 5 is a block diagram showing the interleaver / deinterleaver processing module 24. In FIG. 5, the same reference numerals as those in FIG. In FIG. 5, dp24-in indicates a path for data packets from the switching module ISM1 (30) side, pp24 indicates a path for parameter packets from the switching module ISM1 (30) side, and dp24- “out” indicates a path for data packets to the switching module ISM1 (30) side. As described in the first embodiment, there is no particular symmetry in signal processing between the interleaver 53 in the modulation module group and the deinterleaver 63 in the demodulation module group. The work buffer register is shared in part of the deinterleave processing. Therefore, as shown in FIG. 5, in the interleaver / deinterleaver 24, the interleaver 53 and the deinterleaver 63 are arranged in parallel while sharing the work buffer register 24a. It has become. Each process of the interleaving process and the deinterleaving process is executed by obtaining necessary buffers by appropriately occupying or partially using the work buffer register 24a. The interleaver 53 interleaves the data input from the data packet path dp24-in and outputs the data packet from the data packet path dp24-out. The depth of the interleaving is preferably about the constraint length of the convolutionally encoded signal performed in the convolutional encoding 52. The deinterleaver 63 deinterleaves the data input from the data packet path dp24-in and outputs it from the data packet path dp24-out.

  FIG. 6 is a block diagram showing the mapping / demapping processing module 25. In FIG. 6, the same reference numerals as those in FIG. In FIG. 6, pp25 indicates a path for parameter packets from the switching module ISM1 (30) side, dp25-in indicates a path for data packets from the switching module ISM1 (30) side, and dp25- “out” indicates a path for data packets to the switching module ISM1 (30) side. As shown in FIG. 6, the mapping / demapping processing module 25 inputs the parameter packet from the switching module ISM1 (30) side via the parameter packet path pp25. The parameter packet includes contents indicating transmission (modulation) or reception (demodulation), and the parameter packet processing unit 25a sets the contents in the parameter table.

  In the case of transmission (modulation), the input processing unit 25b receives the data input from the data packet path dp25-in based on an instruction from the parameter / packet processing unit 25a as a buffer COM 25 (input / output data). Write to the rate adjustment buffer. Based on the instruction from the parameter / packet processing unit 25a, the output processing unit 25c maps the data in the buffer COM 25 and outputs the data from the data packet path dp25-out. As a mapping modulation method, a desired method such as QPSK, 16QAM, or 64QAM can be used. For example, in the case of 64QAM, the input signal is divided into 6 bits and mapped on the complex plane with 64 points. In the case of reception (demodulation), the input processing unit 25b demaps the data input from the data packet path dp25-in based on the instruction from the parameter / packet processing unit 25a according to the modulation method or as it is. Write to buffer COM25. Based on the instruction from the parameter / packet processing unit 25a, the output processing unit 25c outputs the data in the buffer COM 25 from the data packet path dp25-out as it is or after demapping depending on the modulation format.

  FIG. 7 is a block diagram showing the symbol control / frame control processing module 26. In FIG. 7, the same reference numerals as those in FIG. In FIG. 7, pp26 indicates a path for parameter packets from the switching module ISM1 (30) side, dp26-in indicates a path for data packets from the switching module ISM1 (30) side, and dp26- “out” indicates a path for data packets to the switching module ISM1 (30) side. As shown in FIG. 7, the symbol control / frame control processing module 26 inputs the parameter packet from the switching module ISM1 (30) side via the parameter packet path pp26. The parameter packet includes contents indicating transmission (modulation) or reception (demodulation), and the parameter packet processing unit 26a sets the contents in the parameter table.

  In the case of transmission (modulation), the input processing unit 26b rearranges data input from the data packet path dp26-in based on an instruction from the parameter / packet processing unit 26a, and performs a buffer COM 26 (work) To the buffer). Based on the instruction from the parameter / packet processing unit 26a, the output processing unit 26c reads out the data packet from the buffer COM 26 and outputs it as a frame from the data packet path dp26-out. One frame can be composed of a desired number of symbols. One symbol is composed of an OFDM symbol and a guard interval. In the case of reception (demodulation), the input processing unit 26b writes the data packets input from the data packet path dp26-in to the buffer COM 26 while rearranging them based on the instruction from the parameter packet processing unit 26a. The output processing unit 26c reads data from the buffer COM 26 based on an instruction from the parameter / packet processing unit 26a, and outputs the data from the data packet path dp26-out.

  FIG. 8 is a block diagram showing the IFFT / FFT processing module 27. In FIG. 8, the same reference numerals as those in FIG. In FIG. 8, pp27 indicates a path for parameter packets from the switching module ISM1 (30) side, dp27-in indicates a path for data packets from the switching module ISM1 (30) side, and dp27- “out” indicates a path for data packets to the switching module ISM1 (30) side. In FIG. 8, reference numeral 27a is an interface with the switching module ISM1 (30) side, 27b is an FFT processing engine unit, and COM27 is a buffer (an input / output buffer and a working buffer) for a common part. As shown in FIG. 8, the IFFT / FFT processing module 27 performs processing only by the FFT processing engine unit 27b, and processing units corresponding to the IFFT processing engine are not provided separately and independently.

  FIG. 9 is a block diagram for explaining the IFFT processing in the IFFT / FFT processing module 27. In FIG. 9, the same reference numerals as those in FIG. As shown in FIG. 9, the real part (Real) and the imaginary part (Imag) of the data input from the data packet path dp27-in are swapped by the interface 27a, and then the FFT processing engine part 27b. Is input. That is, the real part (Real) of the input data is input as an imaginary part (Imag) to the FFT processing engine unit 27b, and the imaginary part (Imag) of the input data is input to the FFT processing engine unit 27b. Is entered as After normal FFT processing is performed in the FFT processing engine unit 27b, the real part (Real) and the imaginary part (Imag) of the data output from the FFT processing engine unit 27b are interfaces as shown in FIG. After being swapped again at 27a, the data packet path dp27-out is output. That is, the real part (Real) of the data output from the FFT processing engine unit 27b is output as the imaginary part (Imag) from the data packet path dp27-out (Imag) and output from the FFT processing engine unit 27b. The imaginary part (Imag) of the data is output as the real part (Real) from the path dp27-out (Real) for the data packet.

  Next, it will be described that IFFT processing is possible by swapping (at the time of input and output) in the interface 27a as described above. If the Fourier transform of g [n] is G [k] and the inverse Fourier transform of G [k] is g [n], the FFT process is given by Expression 3 and the IFFT process is given by Expression 4. Here, Σ is set to n = 0 to N−1 in the expression 3 and k = 0 to N−1 in the expression 4 (the same applies to the following, so the subscript is omitted).

  Here, in Equation 3,

Then, Expression 3 becomes Expression 3 '.

  In Equation 4,

Then, Expression 4 becomes Expression 4 '.

  here,

Assuming that, Equation 4 ′ becomes Equation 4 ″.

  Comparing equation 4 ″ and equation 3 ′, only the part with −1 in exp is different, indicating that the direction of rotation is reversed. The operation of changing the rotation direction can be realized by exchanging (x, y) on the polar coordinates, that is, the real part and the imaginary part. Also in Equation 5, the rotation direction is reversed on the polar coordinates, and this can also be realized by replacing (x, y), that is, the real part and the imaginary part. Therefore, the IFFT processing is performed by exchanging (swapping) the equation 5 with the interface 27a (during data input) shown in FIG. 9 and exchanging (swapping) the equation 4 ″ with the interface 27a (during data output). Can be realized.

  As described above, according to the second embodiment of the present invention, the transmission / reception system 10 according to the first embodiment can be implemented on the processing platform 20. The processing platform 20 includes a switching module ISM1 (30) and the like and a scrambler / descrambler processing module 22 and the like. The switching module ISM1 (30) is provided according to the processing contents of the modulation system or the demodulation system, and uses the routing table 36 indicating the input source of the data packet and the output destination for the next processing, to By outputting the data packet input from the beginning to the output destination and performing the modulation system or the demodulation system, the order of the modulation system or the demodulation system can be controlled. As a result, in the second embodiment, as in the first embodiment, exactly the same functions as those of the conventional OFDM modulation circuit 50 and OFDM demodulation circuit 60 can be executed by half the processing modules except for the overhead for switching processes. In addition, it is possible to provide a transmission / reception system using an OFDM modulation / demodulation method that can greatly reduce the circuit scale.

  As an application example of the present invention, application to a wireless LAN system of IEEE802.11a can be mentioned.

It is a figure which shows the transmission / reception system using the OFDM modulation / demodulation system by Example 1 of this invention. It is a figure which shows the processing platform 20 in Example 2 of this invention. 3 is a block diagram showing a scrambler / descrambler processing module 22. FIG. 6 is a block diagram showing a convolutional encoding / Viterbi decoding processing module 23. FIG. 3 is a block diagram showing an interleaver / deinterleaver processing module 24. FIG. 3 is a block diagram showing a mapping / demapping processing module 25. FIG. 3 is a block diagram showing a symbol control / frame control processing module 26. FIG. 4 is a block diagram showing an IFFT / FFT processing module 27. FIG. 4 is a block diagram for explaining IFFT processing in an IFFT / FFT processing module 27. FIG. 1 is a diagram illustrating a conventional OFDM modulation circuit 50 and OFDM demodulation circuit 60. FIG.

Explanation of symbols

10 transmission / reception system, 11 scrambler / descrambler, 12 convolutional coding / Viterbi decoding, 13 interleaver / deinterleaver, 14 mapping / demapping, 15 symbol control / frame control, 16 IFFT / FFT, 20 processing platform, 21 hardware I / F, 22 scrambler / descrambler processing module, 22a, 25a, 26a parameter packet processing unit 22a, 23 convolution / Viterbi decoding processing module, 24 interleaver / deinterleaver processing module, 25 mapping / Demapping processing module, 25b, 26b input processing unit, 25c, 26c output processing unit, 26 symbol control / frame control processing module, 27 IFF / FFT processing module, 27a interface, 27b FFT processing engine section, 30 switching module ISM1, 31 switching module ISM2, 32 switching module ISM3, 33a, 33b, 33c, 33d, 34a, 34b, 34c, 34d, 35a, 35b, 35c, 35d I / O buffer, 36, 37, 38 Routing table, 50 Conventional OFDM modulation circuit, 51 Scrambler, 52 Convolutional coding, 53 Interleaver, 54 Mapping, 55 Symbol control, 56 IFFT, 60 Conventional OFDM demodulator circuit, 61 descrambler, 62 Viterbi decoding, 63 deinterleaver, 64 demapping, 65 frame control, 66 FFT.

Claims (13)

  A transmission / reception system using an orthogonal frequency division multiplexing modulation / demodulation system, wherein a predetermined module in a modulation system module group and a predetermined module in a demodulation system module group are used as a common module.   2. The transmission / reception system according to claim 1, wherein the predetermined module in the modulation system module group is a scrambler module that scrambles input data, and a predetermined module in the demodulation system module group that is shared with the scrambler module. A transmission / reception system, wherein the module is a descrambler module that descrambles input data.   3. The transmission / reception system according to claim 1, wherein the predetermined module in the module group of the modulation system is a mapping module that maps input data to a signal of a predetermined multilevel modulation system, and is shared with the mapping module. A predetermined module in the demodulation system module group is a demapping module for demapping an input signal into binary data.   4. The transmission / reception system according to claim 1, wherein a predetermined module in the modulation system module group inserts a guard interval into an input signal to form one symbol, and a frame includes a predetermined number of the symbols. A transmission / reception system, wherein a predetermined module in the demodulating module group shared with the symbol control module is a frame control module for extracting a symbol from a framed input signal .   5. The inverse fast Fourier transform module according to claim 1, wherein a predetermined module in the modulation system module group performs an inverse fast Fourier transform process on an input signal to convert the input signal into a signal on a time axis. And the predetermined module in the demodulating module group shared with the inverse fast Fourier transform module is a fast Fourier transform module that performs fast Fourier transform processing on the input signal to convert it to a signal on the frequency axis. A characteristic transmission / reception system. The transmission / reception system according to any one of claims 1 to 5, further comprising a processing platform for performing processing indicated by a data packet including input data,
The data packet input from the input source is sent using the routing table provided according to the processing contents of the modulation system or the demodulation system and indicating the input source of the data packet and the output destination for the next processing. A switching module that controls the order of processing of the modulation system or the demodulation system by outputting to the output destination and performing the processing of the modulation system or the demodulation system;
A processing module which is an input source and an output destination of a routing table and is assigned as the common module, and is a modulation system indicated by the data packet for a data packet sent from the switching module side Or performing a demodulation process to send the data packet to the switching module side;
A plurality of sets of input / output buffers connected to the switching module for buffering data packets, wherein the input buffer buffers data packets input from the routing table input source to the switching module side. And an output buffer for buffering data packets output from the switching module side to an output destination of the routing table,
The processing platform is configured by arbitrarily combining the switching module and the processing module through a pair of the input / output buffers, and at least one switching module corresponds to the outside of the processing platform. When there are multiple switching modules connected via an input / output buffer, a routing table is provided for each switching module to indicate the sharing of modulation system or demodulation system processing in each switching module. And
The switching module inputs a data packet from the outside of the processing platform, the processing module or another switching module via a corresponding input buffer, and processes a modulation system or a demodulation system indicated by the data packet. A routing process for outputting the data packet via an output buffer corresponding to an output destination based on a routing table according to
The processing module performs modulation or demodulation processing indicated by the data packet sent from the switching module via the corresponding output buffer on the data packet, and the data packet To the switching module side through an output buffer and a set of input buffers,
The other switching module uses the other switching module routing table corresponding to the modulation system or the demodulation system processing indicated by the data packet sent from the switching module via the corresponding output buffer. And transmitting / receiving the data packet to the switching module side through the corresponding output buffer and a pair of input buffers.   7. The transmission / reception system according to claim 6, wherein the processing module processes the data packet using a parameter table for each processing module indicating a modulation system or a demodulation system processing according to the input data packet. A transmission / reception system characterized by outputting.   8. The transmission / reception system according to claim 7, wherein a parameter packet including an identifier of a processing module and contents of a parameter table of the processing module input from outside the processing platform is transmitted to the processing module specified by the identifier. A transmission / reception system in which the contents of the parameter table are dynamically rewritten by transmitting based on the above conditions.   A transmission / reception method using an orthogonal frequency division multiplexing modulation / demodulation method, wherein a predetermined process in a modulation system and a predetermined process in a demodulation system are made common.   10. The transmission / reception method according to claim 9, wherein the predetermined process in the modulation system is a scrambler process that scrambles input data, and the predetermined process in the demodulation system that is shared with the scrambler process descrambles the input data. A transmission / reception method characterized by descrambler processing.   11. The transmission / reception method according to claim 9 or 10, wherein the predetermined process in the modulation system is a mapping process for mapping input data to a signal of a predetermined multilevel modulation scheme, and the predetermined process in the demodulation system shared with the mapping process. The transmission / reception method is characterized in that the process is a demapping process for demapping an input signal into binary data.   12. The transmission / reception method according to claim 9, wherein the predetermined processing in the modulation system includes a guard interval in an input signal to form one symbol and framing a frame from a predetermined number of the symbols. A transmission / reception method characterized by being a symbol control process, wherein the predetermined process in the demodulation system shared with the symbol control process is a frame control process for extracting a symbol from a framed input signal. The transmission / reception method according to any one of claims 9 to 12, wherein the predetermined process in the modulation system is an inverse fast Fourier transform process for performing an inverse fast Fourier transform process on an input signal to convert it into a signal on a time axis, The transmission / reception method characterized in that the predetermined process in the demodulation system shared with the inverse fast Fourier transform process is a fast Fourier transform process in which an input signal is subjected to a fast Fourier transform process and converted to a signal on a frequency axis.

Images