JP2007074840A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device wherein an operating voltage margin is improved by a simple constitution, and in particular, a semiconductor integrated circuit device dedicated to a wireless IC tag that can lengthen a communication distance by a simple constitution. <P>SOLUTION: Propagated energy is inputted to an input terminal in the form of an electrical signal. A direct-current voltage is generated from the inputted electrical signal at a power supply circuit. An internal voltage different from the direct-current voltage is formed at a charge pump circuit with a limited current at start, and an internal circuit is operated at the internal voltage. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique that is effective when used in a semiconductor integrated circuit device including a suitable charge pump circuit such as a wireless IC tag mounted with an IC chip and an IC card.

Japanese Patent Laid-Open No. 2002-176141 is an example in which a voltage rectifier circuit for generating a power supply voltage is provided in a wireless IC tag. Japanese Patent Laid-Open No. 2005-151777 is an example of restricting charging / discharging of a capacitor using a constant current in order to prevent noise generation in a charge pump circuit.
JP 2002-176141 A JP 2005-151777 A

  The inventor of the present application has faced the problem of whether the transmission / reception distance can be further increased in the development of a wireless IC tag in which data is rewritten using a nonvolatile memory. In a nonvolatile memory such as a flash EEPROM, a voltage larger than an operation voltage at the time of a read operation is required for a write operation and an erase operation. In order to form such a large voltage in the semiconductor integrated circuit, it was examined to use a multistage charge pump circuit as shown in FIG. This charge pump circuit is a circuit called a Dixon type, and by applying pulses F0, / F0 whose phases are shifted by 180 ° to an element pump circuit composed of a diode D and a capacitor CP for each stage, A voltage corresponding to the number of stages of amplitude can be output. Since the circuit of FIG. 4 is composed of four stages, a voltage of VPP = −4 (VDD−VD) can be obtained with the voltage drop due to the diode being VD, the pulse amplitude being VDD and the load current being zero. In addition, in order to prevent a voltage drop due to VD, there is a system in which the diode is replaced with a MOS and the gate is driven at a high voltage.

  In the charge pump circuit, as shown in the timing diagram of FIG. 31, when the input terminal of the pulse F0 of the capacitor CP1 becomes the power supply voltage VDD, the capacitor is charged positively at the pulse input terminal and negatively charged at the diode D1 side. . When the input pulse F0 becomes the ground potential VSS of the circuit in the next cycle, the diode D1 side becomes a negative voltage, and the potential of the capacitor CP2 at the next stage is set to-(VDD-VD). At this time, since the input terminal of the pulse / F0 of the capacitor CP2 at the next stage is VDD, the potential difference of the capacitor CP2 is 2VDD−VD. Next, when the pulse is inverted again, the potential on the diode side of the second-stage capacitor becomes − (2VDD−VD), and the potential of the next-stage capacitor CP3 becomes −2 (VDD−VD). Thereafter, as the number of stages increases while repeating this operation, the negative potential becomes deeper, and when passing through the diode D5, the potential becomes −4 (VDD−VD). When a large current is consumed at the start of the pumping operation, the power source of the circuit that controls the operation of the charge pump circuit becomes unstable, and the operation control of the charge pump circuit cannot be performed properly. It has been found that the operation control of the volatile memory cannot be performed well, and the transmission / reception distance of the wireless IC tag or the like is limited by the current consumption at the start of the pumping operation.

  In the present inventor, paying attention to the fact that there is a large difference between the current flowing through the charge pump circuit when the pumping operation is started and the current flowing through the charge pump circuit after the output voltage VPP reaches the desired voltage, We considered increasing the transmission / reception distance in the wireless IC tag by limiting the current in the charge pump circuit.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which an operating voltage margin is improved with a simple configuration. Another object of the present invention is to provide a semiconductor integrated circuit device for a wireless IC tag that can increase the communication distance with a simple configuration. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the propagated energy is input to the input terminal in the form of an electrical signal. A DC voltage is generated from the input electric signal by a power supply circuit, an internal voltage different from the DC voltage is formed by a charge pump circuit in which a current at startup is limited, and the internal circuit is operated by the internal voltage.

  The operation margin can be improved with a simple configuration. A wireless IC tag that can increase the communication distance with a simple configuration can be obtained.

  FIG. 1 is a circuit diagram showing one embodiment of a charge pump circuit mounted on a semiconductor integrated circuit device according to the present invention. The charge pump circuit of this embodiment uses a pump circuit in which an element pump circuit RECT composed of a diode D and a boost pump capacity CP is connected in multiple stages. A drive circuit LM-DRV that supplies pulses F1 and / F1 to the element pump circuit RECT that constitutes the charge pump circuit, and a constant current bias circuit BIAS for performing a limiting current of the drive circuit LM-DRV are provided.

  This charge pump circuit is a Dixon type circuit as described above, and applies pulses F1, F1 whose phases are shifted by 180 ° to an element pump circuit composed of a diode D and a capacitor CP for each stage. Thus, a voltage VPP corresponding to the number of stages of the amplitude of the pulse is formed. This boosted voltage VPP is used as the operating voltage of the load circuit LD. The load circuit LD is shown as an equivalent circuit of the capacitor CL and the resistor RL.

  FIG. 2 shows a circuit diagram of an embodiment of the drive circuit LM-DRV of FIG. The drive circuit LM-DRV is supplied with an input pulse F0 using a CMOS inverter circuit composed of an N-channel MOS transistor M1 and a P-channel MOS transistor M2 as an input stage. The output signal of this input stage is supplied to the gates of P channel MOS transistor M5 and N channel MOS transistor M4. Constant current source MOS transistor M6 and MOS transistor M3 are inserted on both the PMOS side and NMOS side of the output stage. Thereby, when the MOS transistor M5 is turned on, the discharge current can be limited, and when the MOS transistor M4 is turned on, the sink current can be limited. The drive circuit LV-DRV corresponding to the input pulse / F0 is also a similar circuit.

  FIG. 3 shows a circuit diagram of an embodiment of the bias circuit BIAS of FIG. The bias circuit BIAS forms constant voltages VGN and VGP supplied to the gates of the constant current source MOS transistors M3 and M6. A current of (VDD−Vth) / RS flows through the MOS transistor M7. The Vth is a threshold voltage between the gate and source of the MOS transistor M7. When the sizes of the MOS transistor M7 and the MOS transistor M8 are the same, the same current flows through the MOS transistors M8 and M9. Here, since the MOS transistor M7, the MOS transistor M3, the MOS transistor M9, and the MOS transistor M6 form a current mirror, the current of the drive circuit is limited to N × (VDD−Vth) / RS. Here, N is the size ratio of the MOS transistors M7 and M3 and the MOS transistors M9 and M6.

  In FIG. 2, the ground potential VSS is supplied to the gate of the MOS transistor M6, the power supply voltage VDD is supplied to the gate of the MOS transistor M3, and the MOS transistors M6 and M3 may be operated as resistance elements. . In this way, the bias circuit BIAS can be omitted. The MOSFETs M6 and M3 can be replaced with resistors using a diffusion layer or resistors using a wiring layer.

  FIG. 4 shows an explanatory diagram of the operating current of the charge pump circuit of FIG. In this figure, in order to understand the present invention, the charge pump circuit has a current limit using the drive circuit LM-DRV and the bias circuit BIAS as described above, and a charge when such a current limit is not performed. The operating current of the pump circuit is shown for comparison. When there is no current limit, as shown by the dotted line in the figure, current that exceeds the power supply capacity of the power supply circuit flows at the beginning of startup. Can be. Also, in the charge pump circuit with a current limiting circuit, a larger current flows in the latter half than in a charge pump circuit without a current limitation, so the time until reaching a desired level is hardly changed.

  The power supply circuit that forms the power supply voltage VDD is formed by rectifying a received signal received by an antenna like a wireless IC tag, as will be described later. Therefore, for example, it has a constant power supply capability as shown by the dotted line in FIG. The limit current of the charge pump circuit by the bias circuit BIAS and the drive circuit LM-DRV is set to be equal to or less than the power supply circuit supply capability. By setting such a limit current, the boosted voltage VPP can be formed in the same manner as in the case where the current limit is not greater than the power supply circuit supply capability.

  When the current limitation is not performed, it means that a current exceeding the power supply circuit supply capacity flows in the charge pump circuit at the start-up as indicated by a dotted line in FIG. In the power supply circuit formed by rectifying the reception signal received by the antenna as described above, if a current exceeding the supply capacity flows, the power supply voltage VDD inevitably decreases significantly, and the charge pump circuit The operation itself is not performed. That is, the drive circuit such as the oscillation circuit or the CMOS inverter circuit that forms the pulses F0 and / F0 does not operate, and the charge pump circuit cannot be boosted. After all, the wireless IC tag that does not limit the current operates only under the condition that the supply capability of the power supply circuit is equal to or higher than the peak current of the charge pump circuit.

  According to a trial calculation by the inventor of the present application, the current at the start-up in the charge pump circuit that forms the boosted voltage VPP such as −10V is as large as about 120 μA. In the RFID tag IC having the charge pump circuit that consumes such a large current, the current supply capability of the power supply circuit formed by rectifying the received signal received by the antenna is the charge pump circuit. It is necessary to make the current consumption at 120 μA or more in the above. That is, since the electric field strength of the radio wave received by the wireless IC tag corresponds to the current supply capability of the power supply circuit, the communicable distance between the signal source and the wireless IC tag is an extremely short distance to obtain the electric field strength. Means that.

  When the current limiting function is provided in the charge pump circuit as in the above embodiment to limit the current at the start-up, the power supply circuit supply capability necessary for operating the charge pump circuit can be reduced. For example, in FIG. 4, the maximum current flowing through the charge pump circuit can be reduced to 40 μA by the limiting current. As a result, even if the charge pump circuit mounted on the wireless IC tag is the same, the current supply capability in the power supply circuit can be reduced to about 1/3 by providing the current limiting function as described above. That is, in the wireless IC tag equipped with the charge pump circuit of this embodiment, it means that the electric field intensity received by the antenna may be as small as about 1/3, and the transmission / reception distance can be increased. . Since this current limiting function can be arbitrarily set by setting the current in the bias circuit BIAS, it is also possible to set a communicable distance by the current limitation in consideration of the performance of the power supply circuit.

  FIG. 5 is a circuit diagram showing another embodiment of the charge pump circuit mounted on the semiconductor integrated circuit device according to the present invention. In this embodiment, a drive circuit LM-DRV with a current limiting circuit is provided for each step-up capacitor CP. The pulses F0 and / F0 are supplied to the drive circuit LM-DRV corresponding to the element pump circuit including the diode D and the capacitor CP for each stage.

  For example, when the boosted voltage VPP of −10V is obtained as described above when the power supply voltage VDD is 1.3V, the element pump circuit RECT has a multistage configuration such as 15 to 16 stages. When the drive circuits LM-DRV are provided corresponding to the pulses F0 and / F0 as shown in FIG. 1 and the pulses F1 and / F1 are supplied to the eight element pump circuits RECT, the pulses F1 and / F1 are supplied. The wiring for transmitting F1 is long, and the wiring width is increased to reduce parasitic resistance. As a result, the parasitic capacitance in the wiring for transmitting the pulses F1, / F1 increases, the charge / decharge current in the parasitic capacitance increases, and the power efficiency in the charge pump circuit decreases.

  On the other hand, when the drive circuit LM-DRV with a current limiting circuit is provided for each boost capacitor CP as in the embodiment circuit of FIG. 5, the pulses F0 and / F0 are transmitted to the drive circuit LM-DRV. Since the current supply capability in the wiring may be small, the wiring width can be reduced. This can reduce the parasitic resistance and parasitic capacitance of the wiring from the drive circuit LM-DRV to which the pulses F1 and / F1 are transmitted to the boost capacitor CP, thereby improving the power efficiency of the entire boost circuit and further increasing the current supply capability. The effect can also be expected.

  FIG. 6 is a circuit diagram showing another embodiment of the charge pump circuit mounted on the semiconductor integrated circuit device according to the present invention. In this embodiment, the multistage element pump circuit RECT is operated by being divided into a front stage and a rear stage. In the figure, the four-stage element pump circuit RECT is divided into two stages, a front stage and a rear stage. Pulses F0 and / F0 are directly supplied to the two element pump circuits REC on the front stage side, and pulses F0 'and / F0' are supplied to the rear stage side through the gate circuits G1 and G2. The gate circuits G1 and G2 are controlled by a control signal ONi. The gate circuits G1 and G2 are composed of AND gate circuits, for example.

  When the charge pump circuit is activated, the control signal ONi is set to the low level (logic 0), the gates of the gate circuits G1 and G2 are closed, and the pulses F0 'and / F0' are both kept at the low level. Accordingly, since only the element pump circuit RECT on the upstream side operates at the time of startup, the current consumption in the charge pump circuit can be halved. Then, after a predetermined time has elapsed, the control signal ONi is set to high level (logic 1), the gates of the gate circuits G1 and G2 are opened, and the pulses F0 ′ and / F0 ′ corresponding to the pulses F0 and / F0 become Supplied to the element pump circuit. As a result, the element pump circuit on the subsequent stage also starts to operate, and the boosted voltage VPP is formed. In this example, the number of divisions is two. However, if the element pump circuits are connected in multiple stages as in the 16 stages, the number of divisions may be increased as in 3 divisions or 4 divisions.

  FIG. 7 is an explanatory diagram of the operating current of the charge pump circuit of FIG. As shown in FIG. 7, since the initial charge of the booster capacitor is dispersed over time, the current at the start-up of the booster pump circuit can be reduced to half. That is, the peak value of the current consumption of the booster pump circuit can be controlled by appropriately adjusting the starting time of the subsequent stage ONi (i = 0, 1,...). It is sufficient if the current consumption of the charge pump circuit dispersed in this way is less than the power supply circuit supply capability. In other words, when the power supply capability of the power supply circuit exceeds the peak current of the charge pump circuit, the wireless IC tag is in a state where it can communicate with the signal transmission source.

  FIG. 8 is a circuit diagram showing another embodiment of the charge pump circuit mounted on the semiconductor integrated circuit device according to the present invention. In this embodiment, the embodiment of FIG. 1 and the embodiment of FIG. 6 are combined. That is, in addition to the gate circuits G1 and G2 for time-division driving of the booster pump circuit as in the embodiment of FIG. 6, a current limiting circuit as in the embodiment of FIG. 1 is provided corresponding to each divided block. Drive circuit LM-DRV is provided.

  FIG. 9 is a circuit diagram showing another embodiment of the charge pump circuit mounted on the semiconductor integrated circuit device according to the present invention. In this embodiment, the embodiment of FIG. 5 and the embodiment of FIG. 6 are combined. That is, as shown in FIG. 5, a drive circuit LM-DRV with a current limiting circuit is provided for each step-up capacitor CP. In addition to the gate circuits G1 and G2 for time-division driving of the boost pump circuit as in the embodiment of FIG. 6, pulses F0, / F0 and F0 ′, / F0 ′ are applied to the respective divided blocks. It is to supply.

  FIG. 10 is an explanatory diagram of the operating current of the charge pump circuit of FIGS. 8 and 9. The combined effect of the drive circuit with a current limiting circuit and time-division driving can reduce the operating current compared to the case where each is used alone. That is, in the figure, the current waveform with no current limitation and time-division driving is shown by a dotted line, the current waveform with current limitation is shown by a one-dot chain line, and the current waveform of time-division driving + current limitation is shown by a solid line. Has been.

  FIG. 11 is a block diagram showing another embodiment of the charge pump circuit mounted on the semiconductor integrated circuit device according to the present invention. In this embodiment, a MOS transistor is used as the rectifying element of the booster pump circuit, and the gate level is controlled so as not to cause a voltage drop due to the threshold voltage Vth. That is, the element pump circuit RECT includes terminals X1, X2, F1, F3, Y1, Y2, and FP, and is provided with a pulse gate control circuit GCNT that supplies the terminal F3 and the drive circuit LM-DRV.

  The terminal FP of each element pump circuit RECT is connected in common and supplied with a pulse FP. The terminal F3 is connected to the output F3 of the gate control circuit. The output terminal F1 of the drive circuit LM-DRV is connected to the terminal F1 except for the element pump circuit RECT at the final stage. The terminal F1 of the final-stage element pump circuit RECT is given the circuit ground potential. Then, the ground potential is supplied to the terminal X1 of the first stage element pump circuit RECT, and the pulse F2 is supplied to the terminal X2. The output terminals Y1 and Y2 of the element pump circuit RECT are connected to the input terminals X1 and X2 of the next stage element pump circuit RECT, respectively. The boosted voltage VPP is output from the output terminal Y1 of the final stage element pump circuit, and the terminal Y2 is opened.

  FIG. 12 shows a circuit diagram of an embodiment of the element pump circuit of FIG. The capacitor CP is a boost capacitor, and the MOS transistors M1 to M5 are rectifier circuits. Here, attention is paid to the i-th element pump circuit RECT. When the terminal F1 becomes VDD by the drive circuit LM-DRV, the gate control circuit GCNT boosts the voltage to the terminal F3 to 2VDD. Since the gate potential of the MOS transistor M4 is −iVDD in the previous cycle, it is − (i−2) VDD at this time. On the other hand, since the terminal Y1 to which the other end of the capacitor CP is connected is -iVDD in the previous cycle, it becomes-(i-1) VDD at this time. The terminal X1 to which the source of the MOS transistor M4 is connected is-(i-1) VDD. Therefore, the gate-source voltage of the MOS transistor M4 becomes VDD, and the capacitor CP can be charged without loss of the threshold voltage Vth. The MOS transistor M1 is turned on by the pulse FP immediately before start-up to set the substrate potential of the MOS transistors M2, M3, and M4 to VSS, and the substrate potential rises due to the coupling by the gate-substrate capacitance, causing latch-up. It works to prevent.

  FIG. 13 shows a circuit diagram of an embodiment of the gate control circuit of FIG. By setting the pulse F2 having the VDD amplitude to the power supply voltage VDD, the capacitor CB is charged through the MOS transistor M15. Here, since the MOS transistor M15 is a P-channel type, the capacitor CB can be charged with no loss of the threshold voltage Vth. On the other hand, since the MOS transistor M16 is off and the MOS transistor M17 is on, the output F3 is VSS. Next, when the pulse F2 becomes the ground potential VSS, the MOS transistor M12 side of the capacitor CB becomes the power supply voltage VDD by the ON state of M12, and the MOS transistor M16 side is boosted to 2VDD. At this time, since the gate of the MOS transistor M16 is VSS, the charge flows out through the MOS transistor M16. As a result, the output pulse F3 is a pulse having a low level of VSS and a high level of 2VDD.

  As described above, by using the embodiment circuit shown in FIGS. 11 to 13, the forward voltage of the diode as shown in FIG. 1 or the like or the voltage loss due to the threshold voltage Vth when the MOSFET is diode-connected can be eliminated. For this reason, the output voltage of the boost pump circuit can be further increased. In other words, if the required output voltage VPP is the same, the number of stages of the element pump circuits RECT in cascade can be reduced.

  FIG. 14 is a circuit diagram showing another embodiment of the charge pump circuit mounted on the semiconductor integrated circuit device according to the present invention. In this embodiment, MOS transistors M20 to M22 as switching elements for precharging are provided for each boosting capacitor CP in the second and subsequent stages of the charge pump circuit called Dickson type as shown in FIG. As described above, the precharge switch elements M20 to M22 are provided for each boost capacitor CP, and both the pulses F0 and / F0 are set to the high level (VDD), so that the boost capacitor is charged before starting the boost circuit. I can leave. Thereby, the current corresponding to the precharge can be reduced when the pump operation is started. If a large peak current flows during the simultaneous precharge, the precharge operation is performed while performing a current limiting function on the MOS transistors M20 to M22, in other words, using the on-resistance value as a small element size. What should I do?

  FIG. 15 is a block diagram showing another embodiment of the charge pump circuit mounted on the semiconductor integrated circuit device according to the present invention. This embodiment is a modification of the above-described FIG. 11, and a terminal FP0 is added to the element pump circuit RECT, which are connected in common and supplied with a pulse FP0. Correspondingly, a drive circuit with precharge control DRVP is provided. Other configurations are the same as those in FIG.

  FIG. 16 shows a circuit diagram of an embodiment of the element pump circuit of FIG. In this embodiment, a MOS transistor M6 is added to the element pump circuit of FIG. The MOS transistor M6 has a source-drain path connected between the circuit ground potential and the terminal Y1, and a gate connected to the added terminal FP0. Other configurations are the same as those of the embodiment of FIG.

  FIG. 17 shows a circuit diagram of an embodiment of the drive circuit DRVP with precharge control of FIG. The drive circuit DRVP with precharge control inputs the pulses F0, / F0, F2 and / F2 to the inverter circuits, respectively, and outputs the output signals as pulses F00, / F00, F20 and / F20 through a NAND gate circuit. Output. The NAND gate circuit has its gate controlled by the output signal of the inverter circuit that receives the added pulse FP0.

  FIG. 18 is a timing chart for explaining the operation of the charge pump circuit of FIG. The pulse FP0 is a boosted capacitor precharge signal, and is precharged at a high level ("H") before the charge pump circuit is activated. Due to the high level of the pulse FP0, the gate circuit of FIG. 17 is closed and all of F00, / F00 and F20, / F20 are set to the high level. As a result, the precharge operation is performed for each boost capacitor CP as in the embodiment of FIG. That is, the MOS transistor M6 of each element pump circuit RECT serves as the switch element M20 and the like.

  When the booster pump circuit is activated, the pulse FP0 is set to low level ("L"). As a result, pulses F00, / F00 and F20, / F20 are output corresponding to the pulses F0, / F0 and F2, / F2, and the boosting operation is started. In this embodiment, each element pump circuit RECT is combined with a current limiting function by the drive circuit LM-DRV and a precharge operation as shown in FIG.

  FIG. 19 is a timing chart for explaining the operation of the charge pump circuit of FIG. This figure shows the timing on a large scale. Before the write or erase operation, the pump capacitor is precharged for boosting capacitance. That is, the pulse FP0 is set to the high level. This precharge may be started immediately after power-on. In this case, if the on-resistance of the precharge switch MOS transistor M6 is increased so that it may overlap with the current of another circuit, a larger current reduction effect can be obtained.

  FIG. 20 is a block diagram showing an embodiment of a wireless IC tag to which the present invention is applied. A power rectifier circuit, a modulation circuit, and a demodulation circuit data are provided for the antenna. The power supply rectifier circuit rectifies a received signal formed into an electric signal by an antenna to form a power supply voltage VDD. The demodulating circuit demodulates the received signal into digital data. The clock component included in the demodulated signal is transmitted to the clock oscillation circuit, and the synchronized clock is reproduced. The reception logic circuit receives and receives data received using the regenerated clock. The control system logic circuit and logic circuit perform overall control operations. The transmission system logic circuit forms a transmission signal and transmits it to the modulation circuit. The modulation circuit modulates the transmission signal and outputs it through the antenna.

  A nonvolatile memory EEPROM is provided as a memory. This nonvolatile memory EEPROM is provided with a charge pump circuit required for a write operation and an erase operation in response to a power supply voltage from a power supply rectifier circuit. Although not particularly limited, the nonvolatile memory EEPROM is controlled to be written / read and erased via a transmission logic circuit. Write data to the nonvolatile memory EEPROM is processed by the data received by the receiving logic circuit or the control logic circuit. Read data from the nonvolatile memory EEPROM or data processed by the control system logic circuit is transmitted to the modulation circuit through the transmission system logic circuit and output. In addition, a test circuit is provided to perform various tests.

  FIG. 21 shows a circuit diagram of an embodiment of the power supply rectifier circuit of FIG. When the reception voltage received by the antenna is a negative voltage, the capacitor C11 is charged through the diode D11. When the reception voltage received by the antenna is a positive voltage, the capacitor C12 is charged with a voltage boosted through the diode D123. In this way, a positive voltage is accumulated in the capacitor 12. Therefore, when the received voltage received by the antenna is a negative voltage, the capacitor C13 is charged with a higher voltage via the diode D13. When the received voltage received by the antenna is a positive voltage, the boosted voltage is applied to charge the output capacitor C14 through the diode D14. Although not limited in particular, the Zener diode ZD prevents the output voltage VDD from becoming too high and exceeding the breakdown voltage of the internal circuit.

  The power supply rectifier circuit is formed in the wireless IC tag by rectifying the received signal as described above. Therefore, when a load current exceeding the current supply capability flows, the potential of the output capacitor C14 decreases, and the internal circuit It will be below the lower limit voltage. For this reason, the wireless IC tag is conditioned on the condition that the operating current of the internal circuit is smaller than the current supply capability of the power supply rectifier circuit, and does not operate when this condition is not satisfied.

  FIG. 22 is a block diagram showing one embodiment of the EEPROM of FIG. The control logic receives the signals RES, RE, and WE and the clock MCK, determines the memory operation mode, and generates a Y address signal and various control signals necessary for it. The memory mat is configured by arranging memory cells in a matrix state. The address buffer receives the address signals AD0 to AD6 and supplies the X address signal to the X decoder. The X decoder decodes the X address signal and performs an operation of selecting a word line of the memory mat. The data latch temporarily holds data for one word line. When the word line is selected, the stored data is held in the data latch. The write data input through the I / O buffer is stored in the data latch through the Y gate in accordance with the selection signal formed by the Y decoder, and a write operation is performed in units of word lines. In the read operation, the Y gate selects the data unit (D00 to D15) designated by the Y decoder from the data latch and outputs it through the I / O buffer.

  Although there is no particular limitation, in a configuration in which erasing is performed in units of word lines, memory data is fetched into the data latch by a read operation, and the memory cells of the word line are erased all at once, and any data latch is performed. By inputting write data in units of data and then performing a write operation in units of one word line, a part of the data for one word line is rewritten. The charge pump circuit of the above embodiment is used for the VPP generation circuit. That is, the power supply voltages VDD and VSS are received, and the boosted voltage VPP required for writing or erasing is formed using the pulse formed by the oscillation circuit or the input clock MCK.

  FIG. 23 is a block diagram showing another embodiment of the charge pump circuit mounted on the semiconductor integrated circuit device according to the present invention. In this embodiment, the same current reduction effect can be obtained by controlling the drive frequency of the charge pump circuit to be low at the beginning and then high from the middle. That is, an oscillation pulse of the oscillation circuit and a low-frequency pulse obtained by dividing the oscillation pulse are formed and switched by the selector. That is, the charge pump circuit is initially operated with a low-frequency pulse divided by the selection signal SEL, and is switched to the oscillation pulse by the selection signal SEL after a predetermined time has elapsed. According to this method, there is no need to provide a bias circuit, and there is an advantage that current consumption can be reduced accordingly. You may combine this system and said each Example suitably.

  FIG. 24 is a sectional view of an element structure of an embodiment of an EEPROM memory cell used in the present invention. The memory cell of this embodiment has a two-transistor configuration of a memory transistor (MG) and a switch MOS transistor (CG). The gates of both transistors are made of polysilicon, and the gate (CG) of the switch MOS is also called a control gate or a word line. In the memory transistor, the gate insulating film is made of an ONO film, and charges are held by trapping electrons in a trap in the nitride film, thereby forming a nonvolatile memory. A state where a certain amount of electrons are captured in the trap is “0”, and a state where there are few electron captures and a hole is captured more than a certain amount is “1”. In the EEPROM, the memory cell state after erasure is defined as “1”. In the memory in the “1” state, even when the memory gate potential is set to 0V at the time of reading, if a read voltage Vr is applied to the drain, current flows at the source 0V. To do.

  FIG. 25 shows a circuit diagram of a memory mat portion for explaining the operation of the EEPROM used in the present invention. (1) is a read mode, (2) is a write mode, and (3) is an erase mode.

  In the read mode of FIG. 25 (1), as shown in the bias condition of FIG. 25 and the timing chart of FIG. 26, the magnitude of the memory current at the time of reading of the EEPROM reflects the amount of charge held in the memory. . In the memory in the “1” state, holes are trapped in the trap in the nitride film, and channel current flows easily. For example, a current as large as several tens of μA flows. In the “0” state memory, electrons are trapped in the traps in the nitride film, and channel current does not flow. Using this characteristic, at the time of reading, the data line DL is first precharged, the current supply source is turned off, and then the potential of the selected word line is raised. An appropriate potential VDDxn of the word line depends on Vth of the switch MOS transistor, but is generated by boosting from the power supply voltage VDD as necessary in order to sufficiently reduce the on-resistance of the switch MOS transistor. When reading the memory in the “1” state, the data line is discharged, the sense latch is inverted, and the data line becomes 0V. When reading the memory in the “0” state, the potential of the data line decreases slightly due to the charge share when the word line potential increases, but is maintained higher than the inversion voltage of the sense latch and becomes equal to the power supply voltage of the latch. . “1” and “0” are determined based on the difference between the data line potentials.

  In the erase mode of FIG. 25 (3), as shown in the bias condition of FIG. 25 and the timing diagram of FIG. 27, a negative high voltage VPP is applied to the selected memory gate, and the power supply voltage VDD is applied to the selected WELL (well). To do. A power supply voltage VDD is applied to the common source line. The data line is floating. When a tunneling current flows due to an electric field due to a potential difference between the selected memory gate and the substrate WELL, and holes are trapped in the traps in the nitride film, they are erased to be in a “1” state. In erasing, first, the potentials of the non-selected memory gate and the selected WELL are raised to VDD. Thereafter, a negative high voltage VPP is simultaneously applied to the selected memory gate and the non-selected WELL by an erasing charge pump circuit.

  In the write mode of FIG. 25 (2), as shown in the bias conditions of FIG. 25 and the timing diagram of FIG. 28, the power supply voltage VDD is applied to the selected memory gate and the negative high voltage VPP is applied to the well WELL. A negative high voltage VPP is applied to the data line when the data to be written is “0”, and VDD is applied when the data is “1”. When a tunneling current flows due to an electric field due to the potential difference between the memory gate and the channel, and electrons are captured by the trap in the nitride film, the state becomes "0". In writing, the potential of the selected word line WL is raised in order to transmit the potential of the data line to the selected memory gate. Next, a write inhibition voltage corresponding to data “1” is applied to the data line DL. Next, the potential of the selected memory gate MG is raised. Thereafter, a negative high voltage VPP is simultaneously applied to the well WELL and the non-selected memory gate by the write charge pump circuit.

  FIG. 29 is a timing chart for explaining an example of the operation of the EEPROM of FIG. A read operation is instructed by the high level of the signal RE. A memory mat selection operation is performed by the address signal AD, and read data is output from the output terminal DO. Next, the signal WE is set to a high level to instruct a write operation. The memory cell selection operation is performed by the address signal AD, and the write data DI is input. At this time, the write data for one word line is input to the data latch, or the storage data is held in the data latch by the word line selection operation, the write data is input for a specific Y address, and the data in the data latch is When data is written in the memory cell, the charge pump circuit starts operating to form the boosted voltage VPP.

  When the operation of the charge pump circuit is started for such a write, the power supply voltage VDD rapidly decreases unless the current limiting function is provided, and the entire internal circuit of the wireless IC tag becomes inoperable. . That is, the write data stored in the data latch is lost, and the wireless IC tag becomes substantially inoperable. On the other hand, when the charge pump circuit of the present application is used, current limitation is performed at the start of the pumping operation to secure the operating voltage VDD of the wireless IC tag, and the write data is correctly stored in the memory cell without being lost. Written. This is the same when executing the erase mode. That is, when a specific word line is selected and data is rewritten, erasing is performed with the rewritten data being input to the data latch. Therefore, in order to secure the rewritten data, the charge pump circuit has a current limiting function. It is necessary to provide

  In the wireless IC tag, information stored in a storage circuit stored in a register or the like included in another reception logic circuit or control logic circuit of the EEPROM is not lost by the activation of the charge pump circuit. In order to achieve this, it is important to maintain the power supply voltage VDD.

  As described above, in the charge pump circuit of the present application, (1) by adding a current limiting element to the inverter circuit that drives the boost pump capacity of the element pump circuit, the charge current of the boost pump capacity is limited, It is possible to prevent a large current from flowing in the first cycle of the boosting start. (2) By dividing the element pump circuit into a plurality of blocks and activating them one by one in order, the charging current of the boost pump capacity is dispersed, so that a large current in the first cycle can be prevented from flowing. (3) By disposing a drive circuit having a current limiting function for each booster capacitor, the current at start-up can be reduced, and at the same time, the parasitic capacitance and parasitic resistance between the drive circuit and the booster capacitor are reduced. The power efficiency of the circuit can also be improved. (4) By controlling the drive frequency of the booster circuit to be small at the beginning and large from the middle, it is possible to suppress a large through current due to booster pump capacity charging in the first cycle while maintaining the current supply capability at the time of steady operation. Is possible. (5) Since the charge current of the boost pump capacity is dispersed by slowly charging the capacity in the pump at the time of power-on or before starting the boost pump circuit, it is possible to prevent a large current from flowing in the first cycle.

  (6) By combining one or more of the above (1) and (2) to (5), the effects of both can be combined to further suppress a large through current due to boost pump capacity charging in the first cycle. It is. (7) By combining any one or both of the above (2) and (3) to (5), it is possible to combine the effects of both and further suppress a large through current due to boost pump capacity charging in the first cycle. It is. (8) By combining the above (4) and (5), the effects of both can be combined to further suppress a large through current due to boost pump capacity charging in the first cycle. As described above, the current in the first cycle can be suppressed, but the current supply capability in the remaining period of the boosting operation is sufficient, so the peak current consumption is increased while keeping the time required for boosting to a high voltage short. It becomes possible to satisfy the suppressed current specification.

  Although the invention made by the present inventors has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. The wireless tag IC is not limited, and a non-contact type IC card may be used. Further, for example, the propagated energy may be light or sound. That is, the present invention can also be applied to a case where light is converted into an electric signal and thereby a power supply voltage is formed, or sound is converted into an electric signal and rectified to form a power supply voltage. That is, the present invention can be similarly applied to an optical response IC tag, a voice response IC tag, and the like. The present invention can be widely used in various semiconductor integrated circuit devices having a charge pump circuit that operates by receiving a propagated energy to generate a power supply voltage.

1 is a circuit diagram showing one embodiment of a charge pump circuit mounted on a semiconductor integrated circuit device according to the present invention. FIG. FIG. 2 is a circuit diagram illustrating an example of a drive circuit LM-DRV in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a bias circuit BIAS in FIG. 1. It is explanatory drawing of the operating current of the charge pump circuit of FIG. It is a circuit diagram which shows another Example of the charge pump circuit mounted in the semiconductor integrated circuit device based on this invention. It is a circuit diagram which shows another Example of the charge pump circuit mounted in the semiconductor integrated circuit device based on this invention. It is explanatory drawing of the operating current of the charge pump circuit of FIG. It is a circuit diagram which shows another Example of the charge pump circuit mounted in the semiconductor integrated circuit device based on this invention. It is a circuit diagram which shows another Example of the charge pump circuit mounted in the semiconductor integrated circuit device based on this invention. It is explanatory drawing of the operating current of the charge pump circuit of FIG.8 and FIG.9. It is a block diagram which shows another Example of the charge pump circuit mounted in the semiconductor integrated circuit device based on this invention. FIG. 12 is a circuit diagram showing an embodiment of the element pump circuit of FIG. 11. FIG. 12 is a circuit diagram illustrating an example of the gate control circuit of FIG. 11. It is a circuit diagram which shows another Example of the charge pump circuit mounted in the semiconductor integrated circuit device based on this invention. It is a block diagram which shows another Example of the charge pump circuit mounted in the semiconductor integrated circuit device based on this invention. FIG. 16 is a circuit diagram showing an embodiment of the element pump circuit of FIG. 15. FIG. 16 is a circuit diagram illustrating an example of a drive circuit with precharge control DRVP in FIG. 15. FIG. 16 is a timing chart for explaining the operation of the charge pump circuit of FIG. 15. FIG. 16 is a timing chart for explaining the operation of the charge pump circuit of FIG. 15. It is a block diagram which shows one Example of the wireless IC tag to which this invention is applied. FIG. 21 is a circuit diagram showing an embodiment of the power supply rectifier circuit of FIG. 20. FIG. 21 is a block diagram showing an example of the EEPROM of FIG. 20. It is a block diagram which shows another Example of the charge pump circuit mounted in the semiconductor integrated circuit device based on this invention. 1 is a cross-sectional view of an element structure showing an embodiment of an EEPROM memory cell used in the present invention. FIG. 5 is a circuit diagram of a memory mat portion for explaining the operation of the EEPROM used in the present invention. FIG. 26 is a timing chart for explaining the read mode of FIG. 25. FIG. 26 is a timing chart for explaining an erase mode in FIG. 25. FIG. 26 is a timing chart for explaining the write mode of FIG. 25. FIG. 23 is a timing chart for explaining an example of the operation of the EEPROM of FIG. 22. It is a circuit diagram for demonstrating an example of the conventional charge pump circuit. FIG. 31 is a timing chart for explaining the operation of the charge pump circuit of FIG. 30.

Explanation of symbols

  RECT: Element pump circuit, LM-DRV: Drive circuit, BIAS: Bias circuit, GCNT: Gate control circuit, DRVP: Drive circuit with precharge control, CP1-CP4: Boost capacitor, D1-D14: Diode, LD: Load circuit G1, G2... Gate circuit, M1 to M22... MOS transistor, CG... Capacitance, C11 to C14.

Claims (11)

An input terminal through which the propagated energy is input in the form of an electrical signal;
A power supply circuit that generates a DC voltage from an electrical signal input from the input terminal;
A charge pump circuit that receives a DC voltage formed by the power supply circuit and forms an internal voltage different from the DC voltage;
An internal circuit that operates at the internal voltage,
The charge pump circuit is a semiconductor integrated circuit device characterized in that a current at startup is limited. In claim 1,
The semiconductor integrated circuit device, wherein the propagated energy is an electromagnetic wave including a signal component. In claim 2,
The charge pump circuit is
Including an oscillation circuit, a drive circuit, a plurality of element pump circuits and an output capacity that operate with the DC voltage,
The oscillation circuit forms an oscillation pulse,
The element pump circuit has a pump capacity and a switch element that performs switching corresponding to the signal level of the oscillation pulse corresponding to the pump capacity,
2. The semiconductor integrated circuit device according to claim 1, wherein the drive circuit limits a current for driving a pump capacity of the element pump circuit in response to the oscillation pulse. In claim 3,
A semiconductor integrated circuit device, wherein the drive circuit is provided corresponding to each of a plurality of element pump circuits. In claim 2,
The charge pump circuit is
Including an oscillation circuit, a drive circuit, a plurality of element pump circuits and an output capacity that operate with the DC voltage,
The oscillation circuit forms an oscillation pulse,
The element pump circuit has a pump capacity and a switch element that performs switching corresponding to the signal level of the oscillation pulse corresponding to the pump capacity,
The drive circuit drives the pump capacity of the element pump circuit in response to the oscillation pulse,
The element pump circuit is divided into a plurality of blocks corresponding to the pumping operation,
The semiconductor integrated circuit device according to claim 1, wherein the plurality of divided blocks operate with a time difference in order from the low voltage side at the time of startup. In claim 2,
The charge pump circuit is
Including an oscillation circuit, a drive circuit, a plurality of element pump circuits and an output capacity that operate with the DC voltage,
The oscillation circuit forms an oscillation pulse,
The element pump circuit has a pump capacity and a switch element that performs switching corresponding to the signal level of the oscillation pulse corresponding to the pump capacity,
The drive circuit drives the pump capacity of the element pump circuit in response to the oscillation pulse,
A semiconductor integrated circuit device, wherein a current at the time of startup is limited by controlling a frequency of the oscillation pulse. In claim 2,
The charge pump circuit is
Including an oscillation circuit, a drive circuit, a plurality of element pump circuits, a charge-up switch, and an output capacitor that operate with the DC voltage,
The oscillation circuit forms an oscillation pulse,
The element pump circuit includes a pump capacity and a switch element that performs switching in accordance with the signal level of the oscillation pulse corresponding to the pump capacity.
The charge-up switch is temporarily turned on at start-up to charge up the pump capacity of each element pump circuit.
The drive circuit generates an output signal necessary for the charge-up operation of the pump capacitor in accordance with the on-state of the charge-up switch at the start-up, and responds to the oscillation pulse after the pump capacitor is charged up. A semiconductor integrated circuit device for driving the pump capacity of the element pump circuit. In any of claims 5, 6 or 7,
2. The semiconductor integrated circuit device according to claim 1, wherein the drive circuit limits a current for driving a pump capacity of the element pump circuit in response to the oscillation pulse. In claim 3 or 8,
The drive circuit includes a CMOS circuit having a P-channel MOSFET and an N-channel MOSFET that receive a pulse signal, and a MOSFET that is connected in series to the P-channel MOSFET and the N-channel MOSFET to perform a current limiting operation. Semiconductor integrated circuit device. In any one of Claim 1 thru | or 9,
The semiconductor integrated circuit device is a device for transmitting and receiving data wirelessly. In claim 10,
The semiconductor integrated circuit device, wherein the internal circuit is a nonvolatile memory that can be electrically rewritten using the internal voltage.

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