JP2007027981A5 - - Google Patents
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- Publication number
- JP2007027981A5 JP2007027981A5 JP2005204641A JP2005204641A JP2007027981A5 JP 2007027981 A5 JP2007027981 A5 JP 2007027981A5 JP 2005204641 A JP2005204641 A JP 2005204641A JP 2005204641 A JP2005204641 A JP 2005204641A JP 2007027981 A5 JP2007027981 A5 JP 2007027981A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005204641A JP2007027981A (ja) | 2005-07-13 | 2005-07-13 | 発振装置およびその制御方法 |
US11/485,464 US7616066B2 (en) | 2005-07-13 | 2006-07-13 | Oscillation device and controlling method therefor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005204641A JP2007027981A (ja) | 2005-07-13 | 2005-07-13 | 発振装置およびその制御方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007027981A JP2007027981A (ja) | 2007-02-01 |
JP2007027981A5 true JP2007027981A5 (ja) | 2007-07-12 |
Family
ID=37661123
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005204641A Pending JP2007027981A (ja) | 2005-07-13 | 2005-07-13 | 発振装置およびその制御方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US7616066B2 (ja) |
JP (1) | JP2007027981A (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2195927B1 (en) * | 2007-08-23 | 2013-06-26 | Rambus Inc. | Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency |
KR100915817B1 (ko) * | 2007-10-09 | 2009-09-07 | 주식회사 하이닉스반도체 | Dll 회로 |
TWI390915B (zh) * | 2008-09-11 | 2013-03-21 | Realtek Semiconductor Corp | 具有適應性通道估測功能之接收系統及其適應性通道估測器 |
US8018289B1 (en) * | 2009-08-19 | 2011-09-13 | Integrated Device Technology, Inc. | Holdover circuit for phase-lock loop |
US8502522B2 (en) | 2010-04-28 | 2013-08-06 | Teradyne, Inc. | Multi-level triggering circuit |
US8542005B2 (en) | 2010-04-28 | 2013-09-24 | Teradyne, Inc. | Connecting digital storage oscilloscopes |
US8531176B2 (en) * | 2010-04-28 | 2013-09-10 | Teradyne, Inc. | Driving an electronic instrument |
US8248167B2 (en) * | 2010-06-28 | 2012-08-21 | Mstar Semiconductor, Inc. | VCO frequency temperature compensation system for PLLs |
KR20120079635A (ko) * | 2011-01-05 | 2012-07-13 | 삼성전자주식회사 | 호이스트 장치 및 그 제어 방법 |
JP5795347B2 (ja) | 2012-02-23 | 2015-10-14 | 旭化成エレクトロニクス株式会社 | デジタルpll回路及びクロック発生器 |
JP6133071B2 (ja) * | 2013-02-07 | 2017-05-24 | 古河電気工業株式会社 | 発振回路及びその制御方法 |
US9258001B1 (en) * | 2013-09-03 | 2016-02-09 | Cirrus Logic, Inc. | Dual-input oscillator for redundant phase-locked loop (PLL) operation |
JP6222356B2 (ja) * | 2014-11-07 | 2017-11-01 | 株式会社ソシオネクスト | 半導体集積回路及び処理回路 |
WO2024008299A1 (en) * | 2022-07-07 | 2024-01-11 | Telefonaktiebolaget Lm Ericsson (Publ) | Transmitter for operation with restricted power consumption |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5866427A (ja) | 1981-10-16 | 1983-04-20 | Toshiba Corp | 無線通信装置 |
JPS5866422A (ja) | 1981-10-16 | 1983-04-20 | Toshiba Corp | フエ−ズロツクル−プ回路 |
JPS58101526A (ja) | 1981-12-11 | 1983-06-16 | Nec Corp | Pll回路 |
CA1282464C (en) * | 1985-10-23 | 1991-04-02 | Masanori Ienaka | Phase-locked oscillator |
JPH0496515A (ja) | 1990-08-13 | 1992-03-27 | Fujitsu Ltd | 位相固定ループ回路及び半導体集積回路 |
JP2581398B2 (ja) | 1993-07-12 | 1997-02-12 | 日本電気株式会社 | Pll周波数シンセサイザ |
JP2953992B2 (ja) * | 1995-06-02 | 1999-09-27 | 埼玉日本電気株式会社 | Pll回路 |
US6771133B2 (en) * | 1997-10-21 | 2004-08-03 | Emhiser Research Limited | Phase-locked oscillator with improved digital integrator |
US6345079B1 (en) * | 1997-10-29 | 2002-02-05 | Victor Company Of Japan, Ltd. | Clock signal generation apparatus |
JPH11308104A (ja) | 1998-04-20 | 1999-11-05 | Mitsubishi Electric Corp | 周波数シンセサイザ |
US6731146B1 (en) * | 2000-05-09 | 2004-05-04 | Qualcomm Incorporated | Method and apparatus for reducing PLL lock time |
JP2003298415A (ja) | 2002-04-01 | 2003-10-17 | Matsushita Electric Ind Co Ltd | Pll回路およびpll制御方法 |
-
2005
- 2005-07-13 JP JP2005204641A patent/JP2007027981A/ja active Pending
-
2006
- 2006-07-13 US US11/485,464 patent/US7616066B2/en not_active Expired - Fee Related
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