JP2007019501A - 半導体素子のビットライン形成方法 - Google Patents
半導体素子のビットライン形成方法 Download PDFInfo
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- JP2007019501A JP2007019501A JP2006181009A JP2006181009A JP2007019501A JP 2007019501 A JP2007019501 A JP 2007019501A JP 2006181009 A JP2006181009 A JP 2006181009A JP 2006181009 A JP2006181009 A JP 2006181009A JP 2007019501 A JP2007019501 A JP 2007019501A
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- forming
- bit line
- insulating film
- interlayer insulating
- barrier metal
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 50
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000002184 metal Substances 0.000 claims abstract description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010936 titanium Substances 0.000 claims description 9
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】 所定の構造物が形成された半導体基板の上部に第1層間絶縁膜を形成した後、コンタクトホールを形成する段階と、前記コンタクトホールの内部に第1導電層を形成する段階と、前記第1導電層を所定の深さエッチングした後、バリアメタル層を形成して前記コンタクトホールを埋め込む段階と、全体構造上に第2層間絶縁膜を形成する段階と、前記バリアメタル層が露出されるように前記第2層間絶縁膜をエッチングした後、第2導電層を埋め込む段階とを含む、半導体素子のビットライン形成方法を提供する。
【選択図】 図2
Description
102…ゲートパターン
104…接合領域
106…第1層間絶縁膜
108…第1導電層
110…バリアメタル層
112…第2層間絶縁膜
114…感光膜
116…第2導電層
Claims (7)
- 所定の構造物が形成された半導体基板の上部に第1層間絶縁膜を形成した後、コンタクトホールを形成する段階と、
前記コンタクトホールの内部に第1導電層を形成する段階と、
前記第1導電層を所定の深さエッチングした後、バリアメタル層を形成して前記コンタクトホールを埋め込む段階と、
全体構造上に第2層間絶縁膜を形成する段階と、
前記バリアメタル層が露出されるように前記第2層間絶縁膜をエッチングした後、第2導電層を埋め込む段階とを含むことを特徴とする、半導体素子のビットライン形成方法。 - 前記第1導電層はポリシリコンで形成することを特徴とする、請求項1に記載の半導体素子のビットライン形成方法。
- 前記所定の深さは100Å〜5000Åであることを特徴とする、請求項1に記載の半導体素子のビットライン形成方法。
- 前記バリアメタル層はチタニウム(Ti)またはチタニウムナイトライド(TiN)で形成することを特徴とする、請求項1に記載の半導体素子のビットライン形成方法。
- 前記コンタクトホールを埋め込んだ後、化学的機械的研磨工程を行って平坦化する段階をさらに含むことを特徴とする、請求項1に記載の半導体素子のビットライン形成方法。
- 前記第2層間絶縁膜のエッチング幅を前記バリアメタル層の幅より所定の幅大きくしてミスアラインを防止することを特徴とする、請求項1に記載の半導体素子のビットライン形成方法。
- 前記第2導電層はタングステン(W)、アルミニウム(Al)および銅(Cu)のいずれか一つで形成することを特徴とする、請求項1に記載の半導体素子のビットライン形成方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050061373A KR100784074B1 (ko) | 2005-07-07 | 2005-07-07 | 반도체 소자의 비트 라인 형성 방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2007019501A true JP2007019501A (ja) | 2007-01-25 |
Family
ID=37609708
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006181009A Pending JP2007019501A (ja) | 2005-07-07 | 2006-06-30 | 半導体素子のビットライン形成方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20070010089A1 (ja) |
JP (1) | JP2007019501A (ja) |
KR (1) | KR100784074B1 (ja) |
CN (1) | CN100487886C (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106158794B (zh) * | 2015-04-07 | 2019-01-15 | 华邦电子股份有限公司 | 半导体装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10200075A (ja) * | 1996-11-14 | 1998-07-31 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2001250792A (ja) * | 2000-03-06 | 2001-09-14 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP2003007850A (ja) * | 2001-06-18 | 2003-01-10 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2006013431A (ja) * | 2004-06-25 | 2006-01-12 | Samsung Electronics Co Ltd | 半導体装置の配線構造体及びその形成方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
US6043529A (en) * | 1996-09-30 | 2000-03-28 | Siemens Aktiengesellschaft | Semiconductor configuration with a protected barrier for a stacked cell |
KR19990080654A (ko) * | 1998-04-20 | 1999-11-15 | 윤종용 | 오버랩을 확보할 수 있는 도전막 식각방법 |
US6284655B1 (en) * | 1998-09-03 | 2001-09-04 | Micron Technology, Inc. | Method for producing low carbon/oxygen conductive layers |
KR20000056158A (ko) * | 1999-02-13 | 2000-09-15 | 윤종용 | 반도체 메모리 장치 및 그 장치의 제조 방법 |
US6348709B1 (en) * | 1999-03-15 | 2002-02-19 | Micron Technology, Inc. | Electrical contact for high dielectric constant capacitors and method for fabricating the same |
KR100309799B1 (ko) * | 1999-11-15 | 2001-11-02 | 윤종용 | 반도체 소자의 제조방법 |
KR100346455B1 (ko) * | 1999-12-30 | 2002-07-27 | 주식회사 하이닉스반도체 | 반도체소자의 캐패시터 형성방법 |
JP4198906B2 (ja) * | 2001-11-15 | 2008-12-17 | 株式会社ルネサステクノロジ | 半導体装置および半導体装置の製造方法 |
US6518167B1 (en) * | 2002-04-16 | 2003-02-11 | Advanced Micro Devices, Inc. | Method of forming a metal or metal nitride interface layer between silicon nitride and copper |
US20040121583A1 (en) * | 2002-12-19 | 2004-06-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming capping barrier layer over copper feature |
CN1241250C (zh) * | 2002-12-27 | 2006-02-08 | 中芯国际集成电路制造(上海)有限公司 | 多孔电介质中镶嵌铜结构的制造方法 |
-
2005
- 2005-07-07 KR KR1020050061373A patent/KR100784074B1/ko not_active IP Right Cessation
-
2006
- 2006-06-30 JP JP2006181009A patent/JP2007019501A/ja active Pending
- 2006-07-05 US US11/482,134 patent/US20070010089A1/en not_active Abandoned
- 2006-07-07 CN CNB2006101285051A patent/CN100487886C/zh not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10200075A (ja) * | 1996-11-14 | 1998-07-31 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2001250792A (ja) * | 2000-03-06 | 2001-09-14 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP2003007850A (ja) * | 2001-06-18 | 2003-01-10 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2006013431A (ja) * | 2004-06-25 | 2006-01-12 | Samsung Electronics Co Ltd | 半導体装置の配線構造体及びその形成方法 |
Also Published As
Publication number | Publication date |
---|---|
CN100487886C (zh) | 2009-05-13 |
US20070010089A1 (en) | 2007-01-11 |
KR20070006231A (ko) | 2007-01-11 |
CN1897249A (zh) | 2007-01-17 |
KR100784074B1 (ko) | 2007-12-10 |
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