JP2007018689A - Page buffer and nonvolatile memory device including the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a page buffer and a nonvolatile memory device including the same. <P>SOLUTION: The nonvolatile memory device includes a memory cell array and the page buffer. The page buffer includes a sense node selectively connected to the bit line of the memory cell array, a first main latch selectively connected to the sense node, a main latch circuit including a second main latch, and a latch input node selectively connected to the first and second main latches. The page buffer circuit includes a cache latch circuit including first and second cache latch nodes, a switch circuit for selectively connecting the second cache latch node to the latch input node, and a shared sense circuit connected between the latch input node and a reference potential. In this case, the shared sense circuit selectively connects the latch input node to the reference potential in response to the voltage of the sense node and the voltage of the first cache latch node. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory device and a method for operating the nonvolatile memory device.

  Recently, there is an increasing demand for non-volatile memory devices that can be electrically programmed and erased. Such devices are at least partially characterized by the ability to store data even without a power source. So-called flash memories are particularly widely used in portable electronic devices such as digital cameras, mobile phones, PDAs, and laptop computers. A flash memory such as a NAND flash memory can store a large amount of data in a relatively small area.

  As a prior art, basic operating principles for flash memory cells and flash memory devices are introduced below. However, the following description is merely illustrative and is not to be understood as defining or limiting the scope of the invention.

  The operation principle of the flash memory cell will be described with reference to FIGS. 1A to 1C. FIG. 1A illustrates a flash memory cell transistor connected between a word line and a bit line. FIG. 1B shows a circuit symbol of the flash memory cell transistor, and FIG. 1C shows a threshold voltage characteristic of the flash memory cell transistor.

  1A to 1C, the flash memory cell transistor includes a source region 4 and a drain region 5 formed on the surface of the substrate 3. In this case, the substrate is P type, and the source and drain regions 4 and 5 are N + type. The gate structure is aligned on top of the channel region defined between the source and drain regions 4,5. The gate structure includes a floating gate 1 and a control gate 2. Although not shown, a tunneling insulating film is inserted between the floating gate 1 and the surface of the substrate P-sub. Further, another thin oxide film (control insulating material in the figure) is inserted between the floating gate 1 and the control gate 2. As shown in the drawing, the drain voltage Vd is supplied from the bit line BL, the control gate voltage Vcg is supplied from the word line WL, and the source voltage Vs is connected to a reference potential such as a ground voltage.

  The threshold voltage (or voltage) of the flash memory cell transistor determines the logic value. That is, in an embodiment of a single-level cell (SLC) transistor, when the flash memory cell transistor is in an initial state (so-called “erased” state), the threshold voltage Vth is as shown in FIG. 1C. Relatively low. In this state, the cell transistor has a logic value “1”, which corresponds to an ON state in a general transistor device. On the other hand, if the cell transistor is in the “program” state PGM, the threshold voltage Vth is relatively high. Such a high threshold voltage state has a logic value “0”, and corresponds to a general transistor OFF state.

  In order to change (program) the cell transistor from the initial state to the programmed state, a well-known FN (Fowler-nordheim) tunneling process is used. Briefly, a relatively large positive potential difference is generated between the control gate 2 and the substrate P-sub, and a force is applied to the excited electrons inside the channel located on the surface of the substrate so as to enter the floating gate 1. To be captured. These negatively charged electrons act as a barrier between the control gate 2 and the channel on the substrate, thus increasing the cell transistor threshold voltage as illustrated in FIG. 1C. In the cell transistor, when a large negative potential difference is formed between the control gate 2 and the substrate P-sub, FN tunneling occurs, and the trapped electrons pass through the thin oxide film between the floating gate 1 and the substrate. The electron barrier is removed, and the threshold voltage Vth decreases. Thus, the cell transistor can also be returned to its initial state.

  The multi-level cell MLC non-volatile memory is characterized in that each cell transistor is used to simultaneously store two or more bits of data. FIG. 2 is a diagram for explaining the operation of the 2-bit nonvolatile cell memory. The threshold voltage Vth of a large number of flash cell transistors generally exhibits a bell-shaped curve distribution. In the example illustrated in FIG. 2, the cell transistor may exhibit any one of four different threshold voltage distributions in the first to fourth states. A cell transistor having a threshold voltage showing one distribution among the four states is assigned to a corresponding 2-bit logic value. For example, the 2-bit logic values are “11”, “10”, “00”, “01” as shown in FIG. The specific bit assignments illustrated in FIG. 2 are commonly known as “gray coding”.

  As described above, a cell transistor is said to be “programmed” when the threshold voltage of the cell transistor increases to a higher threshold voltage in the normal on state (ie, erased state). In FIG. 2, the threshold voltage distribution ("11") located on the leftmost side of the chart is in the erased state. In the 2-bit program operation of the cell transistor, two successive program operations are performed. That is, the least significant bit LSB program mode and the most significant bit MSB program mode.

  Such LSB and MSB program modes will be described below with reference to FIGS. 3-5.

  First, when the cell transistor is initially in the erased state, the initial logic value is “11” (see FIG. 2). In this embodiment, if the least significant bit of the stored data is “0”, the program operation proceeds to increase the threshold voltage of the cell transistor from the first state to the second state (see FIG. 3). . On the other hand, if the least significant bit of the stored data is “1”, no programmed progress is made while in the LSB program mode. After the LSB program mode, the cell transistor is in the first state or the second state.

  Next, in the MSB program mode, the most significant bit of the stored data instructs the operation. FIG. 4 shows the case where Gray-coding is applied. Regardless of whether the cell transistor is in the first state or the second state, if the most significant bit of the stored data is “1”, the program operation is not performed in the MSB program mode. On the other hand, when the most significant bit of the stored data is “0”, the program operation is performed depending on whether the cell transistor is in the first state or the second state after the LSB program mode. This is indicated by the dotted line in FIG. If the most significant bit of stored data is “0” and the cell transistor is in the first state after the LSB program mode, the threshold voltage of the cell transistor is shifted from the first state to the fourth state. The program operation is executed. On the other hand, if the most significant bit of the stored data is “0” and the cell transistor exists in the second state after the LSB program mode, the threshold voltage of the cell transistor is shifted from the second state to the third state. Program operation is executed.

  FIG. 5 is similar to 4 except that binary coding is applied. In this case, the first to fourth threshold voltage states indicate the bit values “11”, “10”, “01”, and “00”. That is, no program operation is performed if the most significant bit of stored data is “1” regardless of whether the cell transistor is in the first state or the second state after the LSB program mode. On the other hand, if the most significant bit of the stored data is “0”, the program operation is performed depending on whether the cell transistor is in the first state or the second state after the LSB program mode. This is indicated by the dotted line in FIG. If the most significant bit of stored data is “0” and the cell transistor exists in the first state after the LSB program mode, a program for shifting the threshold voltage of the cell transistor from the first state to the third state The action is executed. On the other hand, if the most significant bit of the stored data is “0” and the cell transistor is in the second state after the LSB program mode, the threshold voltage of the cell transistor is shifted from the second state to the fourth state. A program for progressing.

  The read operation of the multi-bit non-volatile memory will be described with reference to FIGS. 6 and 7 below. In particular, FIG. 6 shows that the logic value of the least significant bit of data stored in the LSB read mode is determined. The LSB read mode includes a first LSB read operation and a second LSB read operation of the condition part. In the first LSB read operation, the first read voltage Vread is applied to the word line of the cell transistor. As a result, when the cell transistor is turned on, the cell transistor is in the first state “11”. If the cell transistor remains off, a second LSB read operation is performed in which the second read voltage Vread2 is applied to the word line of the cell transistor. Here, even in the second LSB read operation, if the cell transistor is in the OFF state, it is certain that the cell transistor exists in the fourth state (“01”). On the other hand, when the cell transistor is turned on by the second LSB read operation, the least significant bit of the stored data is “0”. However, the most significant bit of the stored data is not yet known.

  In the case of gray-coding, the most significant bit of stored data is known by a single read operation. This is illustrated in FIG. 7 showing a read operation in which a third read voltage Vread3 is applied to the word line of the cell transistor. If the cell transistor is turned on, the most significant bit of the stored data is “1”. If the cell transistor remains off, the most significant bit of the stored data is “0”.

  As can be seen from the above, multi-bit detection for multi-bit non-volatile memory is somewhat more complicated than for single-bit non-volatile memory. Much effort continues to develop and design circuits for programming and reading multiple bits into individual cell transistors.

  An object of the present invention is to provide a non-volatile memory device and a method for operating the non-volatile memory device by programming and reading multiple bits into individual cell transistors.

  According to the features of the present invention for achieving the above-described object, the nonvolatile memory device includes a memory cell array and a page buffer. The page buffer includes a sensing node selectively connected to a bit line of the memory cell array, a first main latch selectively connected to the sensing node, a main latch circuit including a second main latch, and the first buffer. And a latch input node selectively connected to the second main latch node. The page buffer circuit also includes a cache latch circuit including first and second cache latch nodes, a switch circuit that selectively connects the second cache latch node to the latch input node, the latch input node, and a reference potential. Including a shared sensing circuit coupled between the two. Here, the shared sensing circuit selectively connects the latch input node to the reference potential in response to the voltage of the sensing node and the voltage of the first cache latch node.

  According to another aspect of the present invention, the page buffer of the nonvolatile memory device includes a main latch circuit, a cache latch circuit, and a shared sensing circuit. The shared sensing circuit selectively couples the main latch circuit to the reference potential in response to the voltages of the sensing node and the cache latch circuit.

  According to another aspect of the present invention, a method of operating a non-volatile memory device is provided. The nonvolatile memory device includes a nonvolatile memory cell array and a page buffer, wherein the page buffer is (a) a sensing node selectively connected to a bit line of the memory cell array; and (b) selective to the sensing node. A main latch node and a second main latch node connected to each other; (c) a latch input node selectively connected to the first and second main latch nodes; and (d) a first and second cache latch node. A cache latch circuit including: (e) a switch circuit that selectively couples the second cache latch node to the latch input node; and (f) a shared sensing circuit coupled between the latch input circuit and a reference potential. Including. The operation method of the non-volatile memory device includes performing a multi-level cell MLC program operation including an LSB program process and a subsequent MSB program process. Here, the MSB programming process includes: (a) a switch circuit responding to an initial sensing control signal to selectively connect the second disclosed latch node to the latch input node; and (b) the shared sensing circuit detects the sensing. An initial read operation for selectively coupling the latch input node to the reference potential in response to a node voltage;

  According to another aspect of the present invention, a method of operating a non-volatile memory device includes using a shared sensing circuit that selectively couples a main latch circuit to a reference potential in response to a voltage of a sensing node and a cache latch circuit.

  As described above, according to the present invention, various functions can be executed using one page buffer structure.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention can be modified in various forms, and the scope of the present invention is not construed as being limited by the embodiments described in detail below. The embodiments of the present invention are exaggerated to more fully describe the present invention to those skilled in the art and have average knowledge, and elements denoted by the same reference numerals in the drawings represent the same elements. means.

  Referring to FIG. 8, the nonvolatile semiconductor memory device includes a memory cell array MCARR, page buffer blocks PBB <63: 0>, first and second global input lines GDI and nGDI, global output lines GDOUT, and y address signal lines Yp <7. : 0>, Yq <7: 0>, latch signal line LCH <7: 0>, and page buffer decoder DECB <63: 0>.

  The memory cell array MCARR includes memory cells in a matrix form, word lines WL, and bit lines BL. In this embodiment, the memory cell is a NAND flash memory cell transistor.

  The internal input lines IDI <63: 0> and nIDI <63: 0> and the internal output lines IDOUT <63: 0> are connected to the page buffer decoder DECB <63: 0> of dl and the corresponding page buffer block PBB <63. : 0>.

  During a predetermined operation period such as a read mode, a program mode, and an erase mode, the first global input line GDI and the second global input line nGDI transmit input and control data having opposite logic states. As will be described in detail later, each page buffer decoder DECB <63: 0> decodes data GDI and nGDI together with y address data Yp <7: 0> and Yq <7: 0> to generate an internal input line IDI < Data of 63: 0> and nIDI <63: 0> are output.

  Each of the page buffer decoders DECB <63: 0> provides data corresponding to the data of the internal output line IDOUT <63: 0> to the global output line GDOUT.

  FIG. 9 is a schematic block diagram of a circuit connected to a single bit line BL of the multi-bit nonvolatile memory device of FIG. FIG. 11 shows a memory cell array 100 (corresponding to the position of the memory cell array MCARR in FIG. 8) and a row decoder 600 (not shown in FIG. 8).

  The NAND flash memory has a feature that a string of flash memory cell transistors connected in series and a plurality of parallel strings form a memory block of the flash memory. Each string includes a plurality of flash memory cell transistors connected in series to a bit line BL of the memory block and a word line connected to a respective control gate of a row of cell transistors in the memory block. For example, a flash memory device includes 16 or 32 cell transistors in each string, and 4224 strings (B / L0... B / L4223) in each memory block.

  FIG. 9 shows a set of memory cell MC strings each storing or outputting data through even bit lines BLe or odd bit lines BLo. That is, according to an embodiment of the present invention, each bit line BL includes an even bit line BLe and an odd bit line BLo. The connection to such even or odd bit lines will be described in detail below.

  A string selection transistor having a control gate to which a string selection signal SSL and a ground selection signal GSL are input is connected to the last ends of both sides of each individual string. In general, the selection signals SSL and GSL are used for reading and programming operations of cell transistors. Further, a common source line CSL for setting the source line voltage of the cell transistor string of each memory block is located at the end of each of the individual strings. As illustrated, the word line signal WL <n: 1> and the selection signals SSL and GSL are supplied from a row decoder 600 that decodes the row address signal RADD.

  Referring to FIG. 10, there is a cell transistor threshold voltage distribution forming various states of a multi-bit nonvolatile memory according to an embodiment of the present invention. The voltage values illustrated in FIG. 10 are exemplary only.

  According to an embodiment of the present invention, the logic value stored in each cell transistor corresponds to at least one of the four threshold voltage distributions. That is, as illustrated in FIG. 10, one embodiment of the present invention is displayed 11, 10, 00 individually displayed based on four consecutive threshold voltage distributions (ie, four other data states). , 01 adopts a gray-coding method for 2-bit logic values.

  In this embodiment, the threshold voltage value is associated with each data state as in Table 1.

  Each data state is represented by a combination of a first data bit value and a second data bit value. The first data bit value is the least significant bit LSB data value, and the second data bit value is the most significant bit MSB data value. Such an expression appears to have been described in Table 2 below.

  As described in Table 2, the first and fourth data states have the same first bit data value (ie, “1”), and the second and third data states have the same first bit data value. (Ie, “0”). Also, the first and second data states have the same second bit data value (ie, “1”), and the third and fourth data states have the same second bit data value (ie, “0”). Have

  Referring to FIG. 10, the first, second and third read voltages VR1, VR2 and VR3 are applied to the word line WL to determine the data state of the cell transistor. That is, it determines which one of the 2-bit values is stored in the cell transistor. The read voltage is set in a section between threshold voltage distributions in the data state. In the embodiment of the present invention, the read voltages VR1, VR2, and VR3 are 0V, 1V, and 2V, respectively.

  For example, assume a read operation when the third read voltage VR3 is applied to the word line WL1 connected to the selected memory cell MCsel. In this case, if the selected memory cell MCsel is programmed with a data state of “11”, “10”, or “00”, the memory cell MCsel is turned on in response to the third read voltage VR3, and the corresponding bit The line BL is driven with the ground voltage VSS. Conversely, when programmed in the data state of the memory cell MCsel “01”, the memory cell MCsel maintains the turn-off state, and the corresponding bit line BL maintains the initial voltage state. As will be described in detail later, in the read operation mode for determining the data state stored in the selected memory cell MCsel, the read voltages VR1, VR2, and VR3 are selectively applied to the selected word line WL1.

  FIG. 10 shows the first, second and third verification read voltages VF1, VF2 and VF3. As described later, such a verification voltage is used in a verification read operation for confirming whether or not the first and second bit data values are correctly programmed in the selected memory cell MCsel. Each of the verification read voltages VF1, VF2, and VF3 is set to a value similar to the minimum threshold voltage value in the second to fourth threshold voltage distributions. The verification read voltages VF1, VF2, and VF3 are about 0.3V, 1.3V, and 2.3V, respectively.

  FIG. 11 is a block diagram illustrating a multi-bit nonvolatile memory device according to an embodiment of the present invention. The multi-bit non-volatile memory device can operate in a multi-level cell MLC mode and a single-level cell SLC mode, respectively.

  Referring to FIG. 11, reference numerals 100 and 600 denote a memory cell array and a row decoder, respectively, which are the same as those described with reference to FIG.

  FIG. 11 shows a bias and selection circuit 400, a main latch 200, a catch latch 300, a switch circuit SW500, a sensing unit 700, a precharge 800, an output driving unit 900, and a decoder 1000. The circuit configuration of each such component is shown in FIG.

  Referring to FIGS. 11 and 12, the bias and selection circuit 400 selects the even bit line BLe and the odd bit line BLo, and sets the even bit line BLe and the odd bit line BLo at appropriate voltages in the read, program, and erase operation modes. The role to set. As shown in FIG. 12, the bias and selection circuit 400 includes two transistors whose gates are respectively connected to an even shield control signal SHLDe_VDD and an odd shield control signal SHLDo_VDD having a high level. And selectively supplied to the odd bit lines BLo. Similarly, the ground voltage VSS is selectively supplied to the even and odd bit lines BLe and BLo including two transistors having gates respectively connected to the low level even shield control signal SHLDe_VDD and the odd shield control signal SHLDo_VDD. It also includes two transistors used to select the even and odd bit lines BLe and BLo. That is, the two transistors are connected to the even and odd bit lines BLe and BLo, respectively, and the gates thereof are connected to the even bit line selection signal BLSLTe and the odd bit line selection signal BLSLTo.

  FIG. 12 shows a transistor to which a sensing node blocking signal SOPLK is input. This transistor controls the connection between the bias and selection circuit 400 and the main bit line BLm.

  The control signals SHLDe_VDD, SHLDo_VDD, BLSLTe, BLSLTo, and SOPLK are high voltage gate signals higher than the power supply voltage VDD.

  A bit line that is not selected among the even bit line BLe and the odd bit line BLo serves as an interface shield line. However, the present invention is not limited to such an arrangement and can be applied to a single bit line (ie, not even and odd bit lines BLe, BLo) environment.

  11 and 12, NSEN indicates a sense node, which reflects the voltage level of the bit line BLm. As shown in FIG. 12, the sensing node NSEN is selectively coupled to the bit line BLm through a blocking transistor that operates in response to the bit line blocking signal BLSHF. The bit line blocking transistor is a low voltage NMOS transistor.

  The precharge unit 800 charges the sensing node NSEN with a predetermined precharge voltage. In this embodiment, the precharge voltage is the power supply voltage VDD. When the selected memory cell MCsel is “on-cell”, the voltage level of the sense node NSEN decreases to the ground voltage VSS. On the other hand, when the selected cell MCsel is “off cell”, the sensing node NSEN may or may not maintain the power supply voltage VDD by the main latch 200 and the cache latch 300 (to be described later).

  The precharge unit 800 includes a PMOS transistor having a source terminal connected to the power supply voltage VDD and a gate connected to the precharge signal LOAD.

  The output driver 900 is enabled in response to the output of the decoder 100. The internal output line IDOUT is driven with a predetermined output drive voltage by the main latch data stored in the main latch node NLATM. Internal output line IDOUT is electrically insulated from main latch node NLATM and internal data signals DI and nDI. Therefore, the main latch node NLATM is prevented from being driven by data loaded on the internal output line IDOUT unintentionally.

  The output driver 900 includes first and second output driving transistors 220 connected in series between the output driving voltage and the internal output line IDOUT. The gate of the first output driving transistor is connected to the main latch node NLATM, and the gate of the second output driving transistor is connected to the main cache driving signal DIO_M <7: 0>. In this case, the output drive voltage becomes the ground voltage VSS.

  When the main latch node NLATM is at logic “H”, the internal output line IDOUT is driven to the ground voltage VSS in response to the output of the decoder 1000 that transitions at logic “H”. On the other hand, when the main latch node NLATM is logic “L”, the first output driving transistor is turned off. In this case, the internal output line IDOUT maintains the high voltage state regardless of whether or not the output voltage level of the decoder 1000 changes to logic “H”. The high voltage state of the internal output line IDOUT is the power supply voltage VDD.

  The main latch unit 200 and the cache latch 300 include latch circuits such as first and second transmission transistors. The page buffer set and reset signals PBRST <0: 7> and PBSET <0: 7> are input to the gates of the 1 and third transmission transistors of the main latch unit 200, respectively. Internal data signals IDI and nIDI are input to the gates of the first and second transmission transistors of the cache latch 300, respectively. The main latch driving transistors are connected as shown in FIG. 12, and drive the main latch 200 in response to the main latch driving signals DIO_M <0: 7>. On the other hand, the catch latch driving transistor drives the cache latch 300 in response to the latch driving signal DIO_C <0: 7>. In general, the main latch driving signal DIO_M <0: 7> and the cache latch driving signal DIO_C <0: 7> are generated by decoding the y-address signal.

  The sensing unit 700 operates under the control of the latch signal LCH, the dump signal DUMP, the sensing node NSEN, and the cache latch 700. For example, the sensing unit 700 includes four transistors connected between the main latch 200 and a reference potential (ground voltage) as illustrated. As will be described later, this circuit functions as a common sense and dump unit for the page buffer.

  Switch unit 500 includes a transistor connected between main latch unit 200 and cache latch unit 300. This transistor operates in response to the sensing signal INIT_Sens <0: 7>.

  The decoder 1000 has two basic functions based on y-address signals Yp <7: 0> and Yq <0: 7>. First, the decoder 1000 controls transmission of output data corresponding to the data of the internal output line IDOUT to the external output data line DataLine. Such transmission control is performed by generating a gate voltage applied to the output driver 900 by the enable signal nWOREable and the y-address signals Yp <7: 0> and Yq <0: 7>. Second, the page buffer decoder 1000 decodes data corresponding to the input data DI and nDI into the first internal input data IDI and the second internal input data nIDI, respectively. Similarly, such decoding is performed by the address signals Yp <7: 0> and Yq <0: 7>. In the embodiment illustrated in FIG. 12, the decoder 1000 includes two NOR gates and two NAND gates coupled as illustrated in FIG. However, it is obvious that other logic component combinations are possible.

  A description of the operation of the multi-level non-volatile memory of FIGS. 11 and 12 follows.

  First, the LSB read operation in the MLC page buffer operation mode will be described with reference to the flowchart of FIG. 13, the circuit diagrams of FIGS. 14 to 18, and the timing diagram of FIG.

  The LSB read operation in the MLC page buffer operation mode is characterized by the first sensing operation of the read voltage VR1 of FIG. 10 and the second sensing operation of the read voltage VR3 of FIG. Each of FIGS. 14 to 18 includes a threshold voltage distribution graph. Here, “A” corresponds to the read voltage VR1, “B” corresponds to the read voltage VR2, and “C” corresponds to the read voltage VR3.

  Referring to FIGS. 13, 14, and 31, in step 1301, the (main) bit line BL is discharged and the page buffer is reset. In general, the page buffer reset signal PBRST and the main latch driving signal DIO_M are activated to reset the page buffer. Accordingly, the main latch node NLATM becomes high (HIGH).

  Next, in step 1302, the bit lines are configured as shown in FIG. Here, the control signal BLSHF is deactivated, and thus the main bit line is shielded (cut off) from the even bit line BLe.

  Next, in step 1304, as shown in FIG. 17, the sensing and latching operation is performed by the read voltage “A” (VR1 in FIG. 10). The control signal BLSHF, the page buffer set signal PBSET, and the latch signal LCH are activated. Therefore, depending on the state of the sensing node NLATM, the main latch 200 maintains a preset state or is logically flipped.

  Steps 1305, 1306, and 1307 are performed in the same manner as steps 1301, 1302, and 1303 described above. However, the second precharge stage 1305 does not include an operation of resetting the main latch. Further, the sensing and latching operation in step 1307 is performed with reference to the read voltage “C” (VR3 in FIG. 10). Step 1307 is the same as the reverse sensing operation of the read voltage “C” shown in FIG. Control signals BLSLTe, SOPLK, BLSHF, page buffer reset signal PBRST, and latch signal LCH are all activated. Accordingly, depending on the state of the sensing node NLATM, the main latch 200 maintains a preset state or is logically flipped.

  13 represents a recovery period that occurs after the second sensing operation of step 1308, and 1309 represents a data output step in which data appearing at the main latch node NLAT is output to the external data line DataLine.

  Hereinafter, the MSB read operation in the MLC page buffer operation mode will be described with reference to the flowchart of FIG. 19, the circuit diagram of FIG. 20, and the timing diagram of FIG.

  The MSB read operation in the MLC page buffer operation mode is characterized by the sensing operation at the read voltage VR2 of FIG.

  Referring to FIG. 19, the MSB read operation in the MLC page buffer operation mode includes a bit line discharge and page buffer reset stage 1901, a bit line precharge stage 1902, a bit line formation stage 1303, a sensing stage 1904, and a recovery stage 1905. And a data output stage 1906. Such a step is identical to the step of the same name described with reference to FIG. 13 except for the sensing step 1904 performed by the read voltage “B” (VR2). Since the matters illustrated in detail in FIG. 19 are redundant descriptions below, they are omitted here. The circuit diagram of FIG. 20 shows the sensing stage 1904. For convenience of reference, each of FIGS. 14 to 18 includes a threshold voltage distribution diagram. Here, “A” corresponds to the read voltage VR1, “B” corresponds to the read voltage VR2, and “C” corresponds to the read voltage VR3. Control signals BLSLTe, SOPLK, BLSHF, page buffer reset signal PBRST, and latch signal LCH are all activated. Accordingly, depending on the state of the sensing node NLATM, the main latch 200 maintains a preset state or is logically flipped.

  The program operation in the MLC pay buffer operation mode will be described below with reference to the flowcharts of FIGS. 21 and 22, the circuit diagrams of FIGS. 23 to 27, and the timing diagram of FIG.

  The nonvolatile memory cell is selectively programmed in at least one of the first, second, third and fourth threshold voltage states. The first, second, third, and fourth threshold voltage states have data values “11”, “10”, “00”, and “01”, respectively.

  The MLC program operation includes an LSB program and a subsequent MSB program operation. The LSB program operation is illustrated in the flowchart of FIG. 21, and the MSB program operation is illustrated in the flowchart of FIG. Comparing these flowcharts, the LSB and MSB program operations are identical except for the initial read stage 2211 and the dual read verify stages 2209a and 2209b of the MSB program operation.

  In particular, the LSB program operation includes a cache latch (step 2101), a data loading operation (step 2102), a main latch setting operation (step 2103), a data dump operation (step 2104), and a high voltage (HV) activation operation (step 2105). )including. The LSB program operation includes a bit line BL setup operation (step 2106), a program execution operation (step 2107), a recovery interval (step 2108), a read verification operation (step 2109), and a scan interval (step 2110).

  The MSB program operation will be described in detail with reference to the flowchart of FIG. 22, the timing diagram of FIG. 30, and the circuit diagrams of FIGS.

  In operation 2201, the cache latch 300 is set in response to the activation of the disclosed latch driving signal DIO_C and the data signal DI. This is illustrated in FIG. Next, in step 2202, data is loaded into the cache latch 300 as illustrated in FIG. Subsequently, referring to the timing of FIG. 3, the main latch is set in step 2103, and the data dump operation is executed in step 2104.

  Next, in step 2211, an initial read operation is performed, and the switch device 500 responds to the control signal INIT_Sens to connect the cache latch circuit 300 to the input node of the main latch circuit 200. Also, the latch control signal is turned on and the dump control signal is turned off. The initial read operation is illustrated in FIG.

  Referring to FIG. 30, after the initial read operation, a high voltage activation operation is performed in step 2105, the bit line BL is set up in step 2106, and the target memory cell is programmed in step 2107. The program is executed after a recovery period of 2108 steps.

  Next, in steps 2209a and 2209b, first and second read verification operations are performed. In this embodiment, the first read verification operation is a “00” verification operation in which the latch control signal LCH is turned off and the dump control signal DUMP is turned on. In addition, the switch unit 500 separates the cache latch circuit 300 from the input node of the main latch circuit 200. The second read verification is a “01” verification operation in which the latch control signal LCH is turned on and the dump control signal DUMP is turned off. The switch unit 500 separates the cache latch circuit 300 from the input node of the main latch circuit 200. The first and second read verify operations are illustrated in FIGS. 26 and 27, respectively.

  Step 2210 represents a scan period, and it is determined whether the target memory cell is properly programmed based on the results of the first and second read verification operations. If the target memory cell is not properly programmed, the program operation returns to the bit line set-up phase 2206 to proceed with a continuous process when it is verified that the target memory cell is properly programmed.

  Single-level cell (SLC) mode operation is described in detail below with reference to FIGS.

  FIG. 28 illustrates a read operation in the SLC operation mode. The read operation in the SLC mode is executed in the same manner as the MSB read operation in the MLC operation mode described above. Therefore, a detailed technique for the read operation in the SLC mode is omitted.

  FIG. 29 shows a program operation in the SLC operation mode. The SLC program operation is characterized in that the program data is preloaded in the cache latch circuit 300 (preloading). The load path is extended through the shared sensing circuit 700 and the main latch circuit 200 as shown in FIG. The operation of preloading the program data into the cache latch 300 increases the operation speed of the SLC program operation.

  Although the invention has been described through embodiments of the invention, it will be apparent to those skilled in the art that various modifications and variations can be made. Further, the present invention is not limited by the above-described embodiments, and the spirit and scope of the present invention are determined by the above claims.

It is the schematic which shows the threshold voltage characteristic of a non-volatile memory cell. It is the schematic which shows the threshold voltage characteristic of the circuit symbol of a non-volatile memory cell. It is the schematic which shows the threshold voltage characteristic of a non-volatile memory cell. 6 is a diagram illustrating a threshold voltage distribution state of a multi-bit nonvolatile memory cell. FIG. 6 is a threshold voltage distribution diagram for explaining a flowgram operation of a multi-bit nonvolatile memory cell. FIG. 6 is a threshold voltage distribution diagram for explaining a flowgram operation of a multi-bit nonvolatile memory cell. FIG. 6 is a threshold voltage distribution diagram for explaining a flowgram operation of a multi-bit nonvolatile memory cell. FIG. 6 is a threshold voltage distribution diagram for explaining a read operation of a multi-bit nonvolatile memory cell. FIG. 6 is a threshold voltage distribution diagram for explaining a read operation of a multi-bit nonvolatile memory cell. 1 is a schematic diagram illustrating a multi-bit nonvolatile memory device according to an embodiment of the present invention; FIG. FIG. 3 is a schematic diagram illustrating a row decoder and a memory array according to an embodiment of the present invention. 1 is a threshold voltage distribution diagram of a multi-bit nonvolatile memory device according to an embodiment of the present invention; FIG. 1 is a block diagram illustrating a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. FIG. 3 is a block diagram illustrating a page buffer and related circuits according to an exemplary embodiment of the present invention. 3 is a flowchart illustrating an LSB read operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an LSB read operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an LSB read operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an LSB read operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an LSB read operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an LSB read operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. 3 is a flowchart illustrating an MSB read operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating an MSB read operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. 3 is a flowchart illustrating an LSB program operation and an MSB program operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. 5 is a flowchart illustrating an LSB program operation and an MSB program operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a program operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a program operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a program operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a program operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a program operation in an MLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 5 is a circuit diagram illustrating a read operation in an SLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a circuit diagram illustrating a program operation in an SLC mode of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a timing diagram illustrating an operation of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a timing diagram illustrating an operation of a multi-bit nonvolatile memory device according to an embodiment of the present invention. FIG. 6 is a timing diagram illustrating an operation of a multi-bit nonvolatile memory device according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Memory cell array 200 Main latch 300 Catch latch 400 Bias and selection circuit 500 Switch circuit 600 Row decoder 700 Sensing part 800 Precharge 900 Output drive part 1000 Decoder

Claims (38)

In a nonvolatile memory device including a nonvolatile memory cell array and a page buffer, the page buffer includes:
A sensing node selectively connected to a bit line of the memory cell array;
A main latch circuit including a first main latch and a second main latch selectively connected to the sensing node;
A latch input node selectively coupled to the first and second main latch nodes;
A cache latch circuit including first and second cache latch nodes;
A switch circuit that selectively couples the second cache latch node to the latch input node;
A shared sensing circuit coupled between the latch input node and a reference potential, wherein the shared sensing circuit refers to the latch input node according to a voltage of the sense node and a voltage of the first cache latch node; A non-volatile memory device selectively coupled to a potential. The shared sensing circuit is
First and second transistors connected in parallel between the main latch input node and the intermediate node;
The nonvolatile memory device of claim 1, further comprising third and fourth transistors connected in parallel between the intermediate node and a reference potential.   The non-volatile memory device of claim 2, wherein a gate of the second transistor is connected to the first cache latch node, and a gate of the third transistor is connected to the sensing node.   The non-volatile memory device of claim 3, wherein a gate of the second transistor is connected to a latch control signal, and a gate of the fourth transistor is connected to a dump control signal. The memory device operates in a multi-level cell MLC mode including a least significant bit LSB programming process and a most significant bit MSB programming process;
The MSB program process includes an initial read operation;
The initial read operation includes: (a) the switch circuit responding to an initial sensing control signal to connect the second cache latch node to the latch input node; and (b) the first transistor responding to the latch control signal. 5. The non-volatile memory device according to claim 4, wherein the non-volatile memory device is turned on, and (c) the fourth transistor is turned off in response to the dump control signal. In the MLC mode, the nonvolatile memory cell is selectively programmed in at least one of first, second, third, and fourth threshold voltage states;
6. The non-volatile of claim 5, wherein the first, second, third, and fourth threshold voltage states define data values “11”, “10”, “00”, and “01”, respectively. Memory device.   The MSB programming process further includes an MSB program execution operation in which a memory cell is programmed and an MSB verification operation in which a threshold voltage of the programmed memory cell is verified after the initial read operation. The non-volatile memory device according to claim 6. The at least one MSB verification operation includes a “00” verification operation;
The “00” verification operation includes (a) the latch control signal and the dump control signal turning off the first and fourth transistors, and (b) the switch circuit connecting the second cache latch node and the latch input node. The nonvolatile memory device according to claim 7, wherein the nonvolatile memory device is cut off. The at least one MSB verification operation includes a “01” verification operation;
The “01” verification operation includes: (a) the latch control signal turns on the first transistor; (b) the dump control signal turns off the fourth transistor; and (c) the switch circuit causes the second cache to turn on. 9. The nonvolatile memory device according to claim 8, wherein the latch node and the latch input node are cut off.   The non-volatile memory device of claim 1, wherein the memory device operates in a single level cell SLC mode and a multi-level cell MLC mode.   The non-volatile memory device of claim 10, wherein the SLC mode includes an SLC program process in which program data is preloaded into the cache latch circuit.   The nonvolatile memory device of claim 11, wherein the MLC mode includes an MLC program operation including an LSB program process and an MSB program process following the LSB program process. The MSB program process includes an initial read operation;
In the initial read operation, the switch circuit responds to a control signal to connect the cache latch circuit to the main latch circuit, and the shared sensing circuit responds to the voltage of the sensing node to connect the main latch circuit to the reference potential. The nonvolatile memory device according to claim 12, wherein the nonvolatile memory device is selectively coupled to the non-volatile memory device.   The method of claim 13, wherein the MSB programming process further includes an MSB program execution operation for programming a memory cell and a verification operation for verifying the threshold voltage of the programmed memory cell after the initial read operation. The nonvolatile memory device described.   The nonvolatile memory device according to claim 1, wherein the nonvolatile memory cell array is a NAND type flash memory cell. A main latch circuit;
A cache latch circuit;
A page buffer of a non-volatile memory device, comprising: a sensing node and a shared sensing circuit that selectively couples the main latch circuit to a reference potential in response to a voltage of the cache latch circuit.   The page buffer of claim 16, wherein the memory device operates in all of a single level cell SLC mode and a multi-level cell MLC mode.   The page buffer of claim 17, wherein the SLC mode includes an SLC program process in which program data is preloaded into the cache latch circuit.   The page buffer of claim 17, wherein the MLC mode includes an MLC program operation including an LSB program process and a subsequent MSB program process. The MSB program process includes an initial read operation;
In the initial read operation, a switch circuit responds to a control signal to connect the cache latch circuit to the main latch circuit, and the shared sensing circuit responds to a voltage of the sensing node to bring the main latch circuit to the reference potential. The page buffer of the non-volatile memory device according to claim 19, wherein the page buffer is selectively connected.   The method of claim 20, wherein the MSB programming process further includes an MSB program operation in which a memory cell is programmed after the initial read operation and at least one MSB verification operation to verify the programmed memory cell. A page buffer of the nonvolatile memory device described. In the MLC mode, the nonvolatile memory cell is selectively programmed in at least one state among first, second, third, and fourth threshold voltage states;
The nonvolatile memory of claim 21, wherein the first, second, third, and fourth threshold voltage states define data values "11", "10", "00", and "01", respectively. Page buffer of a random memory device. The at least one MSB verification operation includes a “00” verification operation;
In the “00” verification operation, the switch circuit responds to a control signal to shut off the cache latch circuit and the main latch circuit, and the shared sensing circuit responds to voltages of the sensing node and the cache latch circuit. The page buffer of claim 22, wherein a main latch circuit is selectively coupled to the reference potential.   The page of the non-volatile memory device according to claim 23, wherein the at least one MSB verification operation includes a "01" verification operation in which the switch circuit shuts off the cache latch circuit and the main latch input circuit. buffer.   The page buffer of claim 16, wherein the nonvolatile memory device includes NAND type flash memory cells. A non-volatile memory cell array and a page buffer, the page buffer comprising: (a) a sense node selectively coupled to a bit line of the memory cell array; and (b) a main latch selectively coupled to the sense node. A node and a second main latch node; (c) a latch input node selectively coupled to the first and second main latch nodes; and (d) a cache latch circuit including first and second cache latch nodes; (E) a non-volatile memory device including: a switch circuit that selectively connects the second cache latch node to the latch input node; and (f) a shared sensing circuit that has a reference potential connected between the latch input circuit and a reference potential. In operation method,
Performing a multi-level cell MLC program operation including an LSB program process and a subsequent MSB program process,
The MSB programming process includes: (a) a switch circuit responding to an initial sensing control signal to selectively connect the second cache latch node to the latch input node; and (b) the shared sensing circuit detects a voltage of the sensing node. And an initial read operation of selectively coupling the latch input node to the reference potential.   The MSB program process further includes an MSB program execution process for programming a memory cell and an at least one MSB verification operation for verifying a threshold voltage of the programmed memory cell after the initial read operation. Item 27. A method of operating a nonvolatile memory device according to Item 26. The at least one MSB verification operation includes a “00” verification operation;
The “00” verification operation is performed by: (a) the switch circuit responding to the initial sensing control signal to shut off the second cache latch node and the latch input node; and (b) the shared sensing circuit is the sensing node. 28. The method of claim 27, wherein the latch input node is selectively coupled to the reference potential in response to a voltage of the first cache latch node.   29. The operation of the nonvolatile memory device according to claim 28, wherein the at least one MSB verification operation includes a "01" verification operation in which the switch circuit cuts off the second cache latch node and the latch input node. Method.   27. The method of claim 26, further comprising performing an SLC program operation and an SLC read operation.   32. The method of claim 30, wherein the SLC program operation includes a preload operation for programming data in the cache latch.   The method of claim 15, wherein the nonvolatile memory device is a NAND type flash memory cell.   A method of operating a non-volatile memory device comprising using a shared sensing circuit that selectively couples a main latch circuit to a reference potential in response to voltages of a sensing node and a cache latch circuit.   The method of claim 33, further comprising selectively operating the nonvolatile memory device in all of the single level cell SLC mode and the multi-level cell MLC mode. .   35. The method of claim 34, wherein the SLC mode includes an SLC program process of preloading program data into the cache latch circuit (preloading).   35. The method of claim 34, wherein the MLC mode includes an MLC program operation including at least an LSB program process and a subsequent MSB program process.   In the MSB program process, the switch circuit responds to the control signal to connect the cache latch circuit to the main latch circuit, and the shared sensing circuit responds to the voltage of the sensing node to select the main latch circuit as the reference potential. 37. The method of claim 36, further comprising an initial read operation that is connected to each other.   34. The method of claim 33, wherein the nonvolatile memory device is a NAND type flash memory cell.