JP2007005727A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP2007005727A JP2007005727A JP2005187137A JP2005187137A JP2007005727A JP 2007005727 A JP2007005727 A JP 2007005727A JP 2005187137 A JP2005187137 A JP 2005187137A JP 2005187137 A JP2005187137 A JP 2005187137A JP 2007005727 A JP2007005727 A JP 2007005727A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 34
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- 238000000034 method Methods 0.000 claims description 32
- 238000007789 sealing Methods 0.000 claims description 5
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- 238000010586 diagram Methods 0.000 description 2
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- 101150091203 Acot1 gene Proteins 0.000 description 1
- 102100025854 Acyl-coenzyme A thioesterase 1 Human genes 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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Abstract
【解決手段】 基板100の表面に複数の半導体素子102を配置するステップと、基板102の裏面側を下部金型130上に固定するステップと、各半導体素子102の少なくとも1部を覆うように各半導体素子のそれぞれに液状樹脂114をノズル112から供給するステップと、一面に複数のキャビティ144が形成された上部金型を下部金型に対して押圧し、所定の温度下において複数のキャビティ144により液状樹脂114をモールドするステップと、上部金型140のキャビティ144を基板から離脱し、基板上に一括して、かつ個別に複数のモールド樹脂を形成する。
【選択図】 図2
Description
さらに本発明の目的は、基板の一面に搭載された複数の半導体チップのモールド樹脂を小型化、薄型化することができる半導体装置の製造方法を提供する。
さらに本発明の目的は、モールド樹脂が形成された基板の一面上に他の表面実装型の半導体装置を積層することができる半導体装置およびその製造方法を提供することを目的とする。
102、210、304、306:半導体チップ
104、212:ボンディングワイヤ
110:供給部
112:ノズル
114:液状樹脂
130:下部金型
140:上部金型
142:リリースフィルム
144:キャビティ
146:押圧部材
150:吸気孔
152:脚部
160、184、206、410:モールド樹脂
170、186:チャンファー
180:エアポケット
182:ランド
188:突起
200:第1の半導体装置
202:多層配線基板
204:はんだボール
208:ダイアタッチ
300:第2の半導体装置
Claims (26)
- 基板上に搭載された半導体素子を樹脂封止する半導体装置の製造方法であって、
基板の第1の主面上に複数の半導体素子を配し、
基板の第1の主面と対向する第2の主面を支持部材上に固定し、
各半導体素子の少なくとも1部を覆うように、各半導体素子のそれぞれに液状樹脂を供給し、
一面に複数の凹部が形成された型形成部材を支持部材に対して押圧し、一定の温度下において各凹部により各半導体素子の液状樹脂をモールドし、
型形成部材の凹部を基板から離脱させる、
ステップを含む半導体装置の製造方法。 - 液状樹脂を供給するステップは、基板の第1の主面上において液状樹脂を供給するノズルを走査するステップを含む、請求項1に記載の製造方法。
- 液状樹脂を供給するステップは、型形成部材の凹部の体積に対し±3%の範囲の量を供給する、請求項1または2に記載の製造方法。
- 液状樹脂は、常温で液状であり、30ないし150パスカル秒[Pa・s]の粘度を有する、請求項1ないし3いずれか1つに記載の製造方法。
- 液状樹脂は、約150度でモールドされる、請求項1ないし4いずれか1つに記載の製造方法。
- 製造方法はさらに、型形成部材の複数の凹部に、可撓性のフィルムを密着させるステップを含む、請求項1に記載の製造方法。
- フィルムは、型形成部材に形成された吸気孔をから空気を吸気することで各凹部に吸着される、請求項6に記載の製造方法。
- フィルムの軟化温度は、液状樹脂をモールドするときの温度に近い、請求項6に記載の製造方法。
- フィルムは、複数の凹部に接する面に粗さ加工が施されている、請求項6ないし8いずれか1つに記載の製造方法。
- フィルムは、少なくとも50μmの厚さを有する、請求項6ないし9いずれか1つに記載の製造方法。
- フィルムは、熱可塑性フッ素樹脂(ETFE)である、請求項6ないし10いずれか1つに記載の製造方法。
- 製造方法はさらに、型形成部材の凹部により液状樹脂をモールドする前に、液状樹脂の雰囲気を真空に引くステップを有する、請求項1に記載の製造方法。
- 絶対真空度は、少なくとも5キロパスカル[kPa]である、請求項12に記載の製造方法。
- 型形成部材の複数の凹部は、それぞれ独立して弾性的に変位可能である、請求項1に記載の製造方法。
- 型形成部材の複数の凹部は、コーナーにチャンファーが形成されている、請求項1に記載の製造方法。
- コーナーのチャンファーに連通するエアポケットが形成されている、請求項15に記載の製造方法。
- 製造方法はさらに、モールドされた半導体素子の領域に応じて基板を切断するステップを含む、請求項1に記載の製造方法。
- 製造方法はさらに、基板の第2の主面に接続端子を取り付けるステップを含む、請求項1に記載の製造方法。
- 製造方法はさらに、基板の第1の主面上に他の半導体装置を積層するステップを含む、請求項1ないし18いずれか1つに記載の製造方法。
- 請求項1ないし18のいずれか1つに記載された製造方法によって製造されたモールド樹脂を含む基板と、モールド樹脂内に封止された半導体素子とを含む、半導体装置。
- 基板の第1の主面上には配線パターンが形成され、他の半導体装置の裏面に形成された複数の接続端子が前記配線パターンに電気的に接続される、請求項20に記載の半導体装置。
- 他の半導体装置の接続端子は、モールド樹脂の外周に配され、モールド樹脂は、当該基板と他の半導体装置との間に配されている、請求項21に記載の半導体装置。
- 基板は、第1の主面と第2の主面との間に少なくとも1つの配線層を含む、請求項20ないし22いずれか1つに記載の半導体装置。
- 他の半導体装置の接続端子の高さは、モールド樹脂の高さよりも大きい、請求項21ないし23いずれか1つに記載の半導体装置。
- 半導体素子の電極は、基板の第1の主面の配線パターンにボンディングワイヤにより接続されている、請求項21ないし24いずれか1つに記載の半導体装置。
- 半導体素子の電極は、基板の第1の主面の配線パターンにフェースダウン接続されている、請求項21ないし25いずれか1つに記載の半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
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JP2005187137A JP4001608B2 (ja) | 2005-06-27 | 2005-06-27 | 半導体装置および半導体装置の製造方法 |
US11/426,622 US7520052B2 (en) | 2005-06-27 | 2006-06-27 | Method of manufacturing a semiconductor device |
US12/400,474 US7971351B2 (en) | 2005-06-27 | 2009-03-09 | Method of manufacturing a semiconductor device |
US13/114,554 US8304883B2 (en) | 2005-06-27 | 2011-05-24 | Semiconductor device having multiple semiconductor elements |
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JP2005187137A JP4001608B2 (ja) | 2005-06-27 | 2005-06-27 | 半導体装置および半導体装置の製造方法 |
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JP2007189775A Division JP4823161B2 (ja) | 2007-07-20 | 2007-07-20 | 半導体装置 |
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JP4001608B2 JP4001608B2 (ja) | 2007-10-31 |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007266650A (ja) * | 2007-07-20 | 2007-10-11 | Texas Instr Japan Ltd | 半導体装置 |
JP2007335690A (ja) * | 2006-06-16 | 2007-12-27 | Towa Corp | 電子部品の樹脂封止成形方法 |
JP2009289984A (ja) * | 2008-05-29 | 2009-12-10 | Canon Inc | 半導体装置の製造方法及び半導体装置 |
US8710642B2 (en) | 2011-03-25 | 2014-04-29 | Fujitsu Semiconductor Limited | Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus |
WO2015055646A3 (de) * | 2013-10-15 | 2016-01-21 | Osram Opto Semiconductors Gmbh | Herstellung eines optoelektronischen bauelements |
KR102705167B1 (ko) * | 2021-08-30 | 2024-09-09 | 시바우라 메카트로닉스 가부시끼가이샤 | 보호막 형성 장치 |
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- 2005-06-27 JP JP2005187137A patent/JP4001608B2/ja not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007335690A (ja) * | 2006-06-16 | 2007-12-27 | Towa Corp | 電子部品の樹脂封止成形方法 |
JP2007266650A (ja) * | 2007-07-20 | 2007-10-11 | Texas Instr Japan Ltd | 半導体装置 |
JP2009289984A (ja) * | 2008-05-29 | 2009-12-10 | Canon Inc | 半導体装置の製造方法及び半導体装置 |
US8710642B2 (en) | 2011-03-25 | 2014-04-29 | Fujitsu Semiconductor Limited | Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus |
WO2015055646A3 (de) * | 2013-10-15 | 2016-01-21 | Osram Opto Semiconductors Gmbh | Herstellung eines optoelektronischen bauelements |
CN105612624A (zh) * | 2013-10-15 | 2016-05-25 | 奥斯兰姆奥普托半导体有限责任公司 | 光电组件的生产 |
KR102705167B1 (ko) * | 2021-08-30 | 2024-09-09 | 시바우라 메카트로닉스 가부시끼가이샤 | 보호막 형성 장치 |
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