JP2006323602A - Electronic equipment device and its processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the shortening of the life of a battery when a power source switch is kept on, and/or to facilitate proper countermeasures when a microcomputer or ASIC runs away. <P>SOLUTION: This electronic equipment device is provided with first and second processing means (102, 101) for executing processing and a signal line (112) for connecting the first and second processing means, wherein the first processing means detects the operating status of the second processing means through the signal line, and performs processing corresponding to the operating status. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic apparatus device and a processing method thereof.

  A mobile electronic device having a backup battery and operating with an AC adapter, a battery, or the like is described in Patent Document 1, for example. In such a device, for example, a case where two different ICs coexist as shown in FIG. 5 will be described as an example.

  Reference numeral 501 denotes an ASIC with a built-in CPU, which controls the entire apparatus. Reference numeral 502 denotes a microcomputer that performs control such as detection of a power switch indicated by reference numeral 505, output control of a DC power source indicated by reference numeral 504, and backup of various status flags to a built-in RAM. Reference numeral 504 denotes a so-called DC power source such as an AC adapter or a battery, and the supply of 3.3 V is started when the output enable signal of reference numeral 506 is enabled. The microcomputer denoted by reference numeral 502 operates using either the DC power source denoted by reference numeral 504 or the battery denoted by reference numeral 509 as the main power source. However, if both are included due to the voltage difference between the DC power supply voltage Vd (3.3V) and the battery voltage Ve (3.0V) 509, the DC power supply 504 has priority. In this configuration, the battery 509 is not consumed.

  That is, when the power switch 505 is pressed by the user, the microcomputer 502 detects this, and then enables the DC power supply 504 to start up the apparatus body. When 3.3V is supplied from the DC power source indicated by reference numeral 504, the ASIC indicated by reference numeral 501 starts its operation, and at the same time, the power source of the microcomputer 502 indicated by reference numeral 509 is switched from the battery indicated by reference numeral 509 to the DC power source indicated by reference numeral 504.

JP 2000-228829 A

However, when the configuration shown in FIG. 5 is adopted, there are two problems described below.
The first problem is that if the AC adapter outlet is not connected or the battery is out of power, and the power switch denoted by reference numeral 505 is released, the power consumed by the microcomputer denoted by reference numeral 502 (the power supply denoted by reference numeral 505). All of the power required to detect the switch and the power that continues to output the output enable signal indicated by reference numeral 506 are covered by the capacity of the battery indicated by reference numeral 509, leading to a reduction in the life of the battery indicated by reference numeral 509.

  The second problem is that when the microcomputer 502 or the ASIC 501 runs away for some reason, even if one of them can get to know it, one resets the other. Since there was no means to synchronize each other again, there was no method other than expecting the user to turn the power switch of reference numeral 505 back on (reactivation as a device) at this stage.

  An object of the present invention is to prevent the battery life from being shortened when the power switch is pressed and / or to perform appropriate processing when the microcomputer or the ASIC goes out of control.

  The electronic apparatus apparatus according to the present invention includes first and second processing means for performing processing, and a signal line connecting the first and second processing means. An operation state of the second processing means is detected via a signal line, and processing according to the operation state is performed.

  The processing method for an electronic device according to the present invention is a processing method for an electronic device having first and second processing means connected via a signal line, wherein the first processing means includes the signal line. And detecting a state of operation of the second processing means via the step, and performing processing according to the state of operation.

  Since the first processing means performs processing according to the operation state of the second processing means, it is possible to prevent the battery life from being shortened when the power switch is left depressed. In addition, when the first processing unit or the second processing unit runs away, an appropriate process can be performed.

Embodiments according to the present invention will be described.
FIG. 1 is an overall block diagram of an electronic device apparatus including IC monitoring means according to an embodiment of the present invention.
Reference numeral 101 denotes an ASIC with a built-in CPU, which controls the entire apparatus.

  Reference numeral 104 denotes a DC voltage generation unit. The terminal OUT1 from which the supply of Vd (3.3 V) 107 is started simply by inserting the outlet 103 and the output enable signal 106 is enabled. 108 has a terminal OUT2 for starting supply of 3.3V.

  Reference numeral 102 denotes a first IC that plays the most important role in the present embodiment. In this configuration, the detection of the power switch indicated by reference numeral 105, the output control of the DC voltage generator indicated by reference numeral 104, and the built-in RTC function It plays a role of various time management using the CPU, backup of various status flags to the built-in RAM, command communication with the reference numeral 101, and reading of the voltage level of the reference numeral 112.

  In addition, the IC denoted by reference numeral 102 operates using either the DC power source denoted by reference numeral 107 or the battery denoted by reference numeral 109 as the main power source when energized. However, if both are included due to the voltage difference between the DC power supply voltage Vd (3.3 V) denoted by reference numeral 107 and the battery voltage Ve (3.0 V) denoted by reference numeral 109, the DC power supply has priority (reference numeral 111 = Vd). At this time, the battery 109 is not consumed when the IC 102 is operated.

  More specifically, when the battery voltage of Ve is the main power source, the operation of the IC 102 is limited to the RTC function and backup of various state flags to the built-in RAM, and operates in a low power consumption sleep mode. . In addition, when the Vd DC power source is the main power source, the IC 102 is operated in the normal mode and performs all of the above roles. If the battery capacity 109 is exhausted and the DC power supply 107 is not turned on, the RTC function is stopped and the backup data disappears.

  As will be described here, the transition of the IC denoted by reference numeral 102 from the sleep mode to the normal mode is called a warm start. As a condition for the warm start, supply of Vd (3.3 V) of reference numeral 107 is started when the outlet of reference numeral 103 is inserted while the IC of reference numeral 102 is operating in the sleep mode. When ON is detected.

  In addition, from the state where there is no main power source of the IC of reference numeral 102, that is, the voltage of reference numeral 111 is 0V, either the DC power source of reference numeral 107 or the battery voltage of reference numeral 109 is supplied, and the IC of reference numeral 102 operates. Starting the process is called a cold start. There are two cold start conditions. The first is the moment when the supply of Vd (3.3 V) 107 is started when the voltage 111 is 0 V and the outlet 103 is inserted. And The second is the moment when the voltage is supplied to the reference numeral 111 when the voltage of the reference numeral 111 is 0V and the battery of the reference numeral 109 is replaced or newly installed.

Reference numeral 103 denotes an outlet of the DC voltage generation unit 104.
Reference numeral 105 denotes a power switch of the present apparatus, which is connected to the port P0 of the IC indicated by reference numeral 102 and detects the switch. Key-on wakeup is set for the port P0 of the IC 102. The key-on wakeup is a setting at the IC port denoted by reference numeral 102. When the switch is detected, the mode is shifted from the sleep mode to the normal mode.

Reference numeral 106 denotes an output enable signal given to the DC voltage generation unit 104.
Reference numeral 107 denotes Vd (3.3 V) output from the terminal OUT1 of the DC voltage generation unit 104, which is supplied to the IC 102 through the diode 113.

  Reference numeral 108 denotes a 3.3 V line output from the terminal OUT2 of the DC voltage generation unit 104, which supplies power to an IC (ASIC) 101.

  Reference numeral 109 denotes a backup coin battery, and a voltage is supplied to the IC indicated by reference numeral 102 via a diode indicated by reference numeral 110. The voltage of the coin battery is Ve = 3.0V.

  Reference numeral 112 denotes a signal line that plays an important role in the present embodiment. In this configuration, the signal line is output from the IC port denoted by reference numeral 101 and the voltage level is read at the port P1 of the IC denoted by reference numeral 102. As will be described in detail later, the signal line 112 is also a monitoring signal line used to monitor the operating state of the IC 101 according to the situation, and from the IC 101 to the IC 102. It is also a signal line used to give a reset command.

Reference numeral 111 denotes a power supply voltage of the IC indicated by reference numeral 102 and also a pull-up voltage of the power switch indicated by reference numeral 105.
Reference numeral 113 denotes a diode that is connected in series with Vd of reference numeral 107.

  In the configuration of this embodiment, it is necessary to select a low-leakage product (a diode having a very small leakage current in the reverse direction) as the diode denoted by reference numeral 113. The reason for this is that while the IC of the reference numeral 109 is operated with the coin battery voltage of the reference numeral 109 as the main power supply, a leakage current in the reverse direction occurs with respect to the diode of the reference numeral 113 due to the wraparound of Ve. This is because, depending on the diode to be used, a numerical value that cannot be ignored with respect to the battery life of 109. Since the smaller the leakage current, the less wasteful consumption is required. Therefore, it is necessary to select a low-leakage diode for the diode 113.

  Reference numeral 114 denotes a resistor that pulls down the signal line 112. It is desirable to add this because the voltage level of the reference numeral 112, which is the port output, is stabilized at a low level (hereinafter referred to as "L") when the voltage to the IC of the reference numeral 101 is 0V.

  Reference numeral 115 denotes a bidirectional signal line for communication between the IC of reference numeral 101 and the IC of reference numeral 102. The IC of reference numeral 101 periodically notifies the IC of reference numeral 102 of various status flags as commands. The IC denoted by reference numeral 102 has a built-in memory (storage means), and stores the received status flag in the built-in memory.

  This status flag is a specification that always keeps a history of one time in the built-in memory of the IC of reference numeral 102 and overwrites it every time it is received. In addition, the IC denoted by reference numeral 102 performs processing for notifying the state flag stored last time by a command each time the IC denoted by reference numeral 101 is activated.

  That is, even if some trouble occurs in the previous time and the voltage supply from the DC voltage generating unit 104 is cut off, the next time the IC 101 is started, You can know if it is finished.

  In the following description, a case where an electronic device apparatus including the IC monitoring unit of this embodiment is actually used will be described as an example.

(Case 1)
Case 1 will be described with reference to FIGS. 1 and 2.
In case 1, with the battery capacity of reference numeral 109 remaining, after turning on the outlet of reference numeral 103, the power switch of reference numeral 105 is turned on to supply power to the entire system of FIG. A procedure for determining whether the IC has been normally activated by the IC denoted by reference numeral 102 will be described as an example. In fact, most use states are likely to be included in this case.

  In the initial state in this case, since the battery capacity of reference numeral 109 remains, the IC of reference numeral 102 is operating in the sleep mode. As a step, the user is staying at step S209.

  In this state, when the outlet of the reference numeral 103 is turned on, Vd (3.3 V) of the reference numeral 107 is supplied. From the difference in voltage level between Ve (3.0 V) of the reference numeral 109 and Vd (3.3 V) of the reference numeral 107. , Vd of reference numeral 107 is supplied to the IC of reference numeral 102. For the IC denoted by reference numeral 102, the main power source is switched from Ve to Vd.

  Further, when the power switch denoted by reference numeral 105 is turned on from this state, the IC denoted by reference numeral 102 detects that the power switch denoted by reference numeral 105 is turned on at the port P0 (step S201). Return to mode, that is, warm start.

  The warm-started IC of reference numeral 102 enables the output enable signal of reference numeral 106 in step S202, and outputs 3.3V of reference numeral 108 from the terminal OUT2 of the DC voltage generation section of reference numeral 104. When 3.3V of reference numeral 108 is supplied to the IC of reference numeral 101, the IC of reference numeral 101 starts operation.

  As will be described here, the IC denoted by reference numeral 101 immediately after resetting, after completing various initial settings, outputs a high level (hereinafter referred to as “H”) signal from the port to which the signal line denoted by reference numeral 112 is connected. Assume that it has been programmed in advance to output. That is, when the IC denoted by reference numeral 101 starts operating normally, “H” is output from the signal line denoted by reference numeral 112.

  The signal line 112 is maintained at “L” since the pull-down resistor 114 is attached in the previous state (the state where no power is supplied to the IC 101), and the IC 101 operates. Starts, the signal line 112 changes from “L” to “H”.

  The IC denoted by reference numeral 102 samples the signal line denoted by reference numeral 112 at a cycle of 7.5 ms in step S203, and can monitor whether or not the IC denoted by reference numeral 101 has started up normally after power-on.

  When the IC indicated by reference numeral 102 confirms that the signal line indicated by reference numeral 112 has changed from “L” to “H” in step S204, the IC advances to step S205, and recognizes that the IC indicated by reference numeral 101 has started up normally.

  However, if it is not confirmed in step S204 that the signal line 112 has changed from “L” to “H”, the process proceeds to step S206, and the IC of reference numeral 102 performs steps S203 and S204 for one second. Is repeated until the signal line 112 changes to “H”. However, if the signal line 112 does not become “H” even after 1 second, the IC 102 has timed out and proceeds to step S207, and the IC 101 cannot be activated for some reason. Or it judges that it is a runaway state.

  In any state, since it is impossible to leave the state in which the IC 101 cannot be normally started, in step S208, the IC 102 is returned to the initial state as a device. After the output enable signal of reference numeral 106 is disabled and the output from the terminal OUT2 of the DC voltage generation section of reference numeral 104 is dropped, the process proceeds to step S209, and the IC of reference numeral 102 shifts to the sleep mode.

An exceptional case in case 1 will be described.
The exception case here is that the battery capacity of reference numeral 109 remains and the power switch of reference numeral 105 is turned on in spite of the state where the outlet of reference numeral 103 is not inserted, and the entire system of FIG. The case where it is going to start is demonstrated as an example. This is an unexpectedly many case when the device is not powered.

  Even in the initial state in this case, the battery capacity of 109 remains, so that the IC of 102 is operating in the sleep mode. As a step, the user is staying at step S209.

  Since the outlet indicated by reference numeral 103 is not inserted, Vd (3.3 V) indicated by reference numeral 107 is not supplied, and the main power source of the IC indicated by reference numeral 102 remains Ve.

  In this state, when the power switch denoted by reference numeral 105 is turned on, the IC denoted by reference numeral 102 detects that the power switch denoted by reference numeral 105 is turned on at the port P0 (step S201), and the IC denoted by reference numeral 102 is changed from the sleep mode to the normal mode. Return to, that is, warm start.

  The warm-started IC of reference numeral 102 enables the output enable signal of reference numeral 106 in step S202, but 3.3V of reference numeral 108 is not output from the terminal OUT2 of the DC voltage generation unit of reference numeral 104. Since no power is supplied to the IC denoted by reference numeral 101, the IC denoted by reference numeral 101 cannot of course start operation, and the signal line denoted by reference numeral 112 remains "L".

  Similarly, in step S203, the IC denoted by reference numeral 102 samples the signal line denoted by reference numeral 112 at a cycle of 7.5 ms. However, since the signal line denoted by reference numeral 112 remains at “L” in step S204, step S206 is performed. Proceed to

  In step S206, the IC of reference numeral 102 waits for the signal line of reference numeral 112 to change to “H” while repeating steps S203 and S204 for one second. Since the line does not become “H”, the process times out and proceeds to step S207.

  In step S207, in this example, the outlet is not connected, but there is no change in that the IC with the reference numeral 101 cannot be normally started, so the IC with the reference numeral 102 is determined to be in an illegal state.

  Since the outlet is not connected, no voltage is originally output from the terminal OUT2 of the DC voltage generation unit 104, but in order to return to the initial state as the apparatus, the process proceeds to step S208. Disable the output enable signal.

  In this case, since the IC indicated by the reference numeral 102 covers the series of processes up to now with the power of the coin battery indicated by the reference numeral 109, in step S209, the IC immediately shifts to the sleep mode that is the power saving mode.

(Case 2)
The case 2 will be described with reference to FIGS. 1 and 3.
In case 2, the apparatus of FIG. 1 is so-called that the outlet of the reference numeral 103 is suddenly pulled out or the power supply to the apparatus is cut off due to a battery exhaustion or power failure. A case where “illegal power off” is performed will be described as an example.

  The initial state in this case is a state in which Vd of reference numeral 107 and 3.3 V of reference numeral 108 are being supplied from the terminals OUT1 and OUT2 of the DC voltage generation section of reference numeral 104, respectively. Both are operating in the normal mode.

  Further, the IC denoted by reference numeral 101 regularly notifies the IC denoted by reference numeral 102 as various commands using the communication line denoted by reference numeral 115, and the IC denoted by reference numeral 102 stores the received state flag in a built-in memory. Suppose you are saving to.

  Further, the IC of reference numeral 102 operating in the normal mode always samples the signal line of reference numeral 112 in a cycle of 7.5 ms in step S301 and stays in the loop of step S301 and step S302. The IC denoted by reference numeral 102 recognizes that the IC denoted by reference numeral 101 is operating normally while the signal line denoted by reference numeral 112 is “H”.

  In this state, if the outlet 103 is pulled out or if the battery runs out or a power failure occurs without being pulled out, the supply of Vd (3.3 V) 107 and 3.3 V 108 is cut off.

  By disconnecting Vd of reference numeral 107, Ve of reference numeral 109 is supplied to the IC of reference numeral 102 from the difference in voltage level between Ve (3.0V) of reference numeral 109 and Vd (0V) of reference numeral 107. become. That is, for the IC denoted by reference numeral 102, the main power supply is switched from Vd to Ve. In this case, as far as the IC of reference numeral 102 is concerned, only the main power source is switched, and there is no particular problem in operation.

  However, for the IC denoted by reference numeral 101, the operation stops at the moment when the supply of 3.3V denoted by reference numeral 108 is cut off. The voltage level of the signal line 112, which is the port output of the IC 101 whose operation is stopped, is inherently indefinite, but in this configuration, the pull-down resistor 114 is attached, so that “L” is determined. To do.

  That is, the IC of reference numeral 102 staying in the loop of step S301 and step S302 confirms that the voltage level of the signal line of reference numeral 112 has changed from “H” to “L” in the determination of step S302. The process proceeds to step S303.

  In step S303, first, the value of the sampling number counter (i) is initialized, and the process proceeds to step S304.

  In step S304, the IC denoted by reference numeral 102 samples the signal line denoted by reference numeral 112 again at a cycle of 7.5 ms. The reason is to avoid an erroneous determination such that the signal line 112 is instantaneously changed to “L” due to the influence of noise or the like, and happens to pass the determination in step S302.

  In the next determination in step S305, the IC of reference numeral 102 proceeds to step S306 if the determination of “L” has not changed, and returns to step S301 if the determination of “H”.

  In step S306, the IC denoted by reference numeral 102 measures the time during which the signal line denoted by reference numeral 112 holds “L”.

  This time, it is set that “illegal power-off” is confirmed when “L” is continuously detected in 16 times or more sampling (approximately 120 ms in terms of time) at a period of 7.5 ms.

  The IC denoted by reference numeral 102 proceeds from step S306 to step S307 while the number of times of sampling is 15 or less, increments the number counter i (plus one time) in step S307, returns to step S304, and steps S304 to S307. Repeat the loop.

  When the number of sampling times reaches 16, the IC of reference numeral 102 proceeds to step S308, determines that “illegal power off”, and in step S309, the fact that the illegal power off has occurred is stored as backup data in the built-in memory. save. The backup data is notified from the IC 102 to the IC 101 using the communication line 115 when the apparatus is turned on next time.

  Then, the IC denoted by reference numeral 102 disables the output enable signal denoted by reference numeral 106 in step S310, and then proceeds to step S311. The IC denoted by reference numeral 102 shifts to the sleep mode.

(Case 3)
Case 3 will be described with reference to FIGS. 1 and 4.
Case 3 will be described by taking as an example a case where the IC of reference numeral 101 uses the signal line of reference numeral 112 to reset the IC of reference numeral 102 during the normal operation of the apparatus of FIG.

  The initial state in this case is a state in which Vd of reference numeral 107 and 3.3 V of reference numeral 108 are being supplied from the terminals OUT1 and OUT2 of the DC voltage generation section of reference numeral 104, respectively. Both are operating in the normal mode. Further, the IC of reference numeral 102 operating in the normal mode always samples the signal line of reference numeral 112 in a cycle of 7.5 ms in step S401 and stays in the loop of step S401 and step S402.

  In this state, the IC denoted by reference numeral 101 outputs “L” to the signal line denoted by reference numeral 112 in order to reset the IC denoted by reference numeral 102. However, since the signal line 112 is also used as a monitoring signal for knowing the operating state of the IC 101 as described in the case 2, the time during which “L” is held (pulse width) is used here. Is defined as 15 ms to 112.5 ms, and when the signal line 112 is “L” with a pulse width that satisfies this condition, the IC 102 is determined to be a reset command from the IC 101. . The reset command is a pulse signal having a predetermined pulse width.

  As in Case 2, the voltage level of the signal line 112 changed from “H” to “L” in the discrimination of Step S402 in the IC of the code 102 staying in the loop of Step S401 and Step S402. And proceed to step S403. The IC denoted by reference numeral 102 initializes the value of the sampling number counter i in step S403, and then proceeds to step S404. Even in step S404, the IC of reference numeral 102 again samples the signal line of reference numeral 112 at a cycle of 7.5 ms in order to avoid erroneous determination that the signal line of reference numeral 112 has changed to “L” due to noise or the like. . In the next determination in step S405, the IC of reference numeral 102 proceeds to step S406 if the determination of “L” is not changed, and proceeds to step S412 if the determination is “H”.

  In step S406, the time during which the signal line 112 is held at “L” is measured.

  In this case, when “L” is detected in the range of 2 to 15 times in a cycle of 7.5 ms, the reset command is set to be confirmed. In terms of time, the pulse width corresponds to 15 ms to 112.5 ms.

  The IC denoted by reference numeral 102 increments the number counter i in step S407 (plus one time), and then repeats the loop of steps S404 to S407. If the signal line 112 returns to “H” in step S405, the process proceeds to step S412 to determine whether the value of the sampling number counter i is in the range of 2 to 15 times. If the IC of the code 102 satisfies the condition, it is interpreted as a reset command in step S413, and self-reset is performed in step S414.

  The self-reset here means a software reset, and an IC denoted by reference numeral 102 indicates that the program is started from an address (address) where the program started immediately after the reset is stored.

  As described above, it is possible to determine whether the reset command from the IC of the reference numeral 101 or the operation state of the IC of the reference numeral 101 is indicated by the time difference when the signal line of the reference numeral 112 becomes “L”.

  In step S406, the IC denoted by reference numeral 102 performs the processing of steps S408 to S411 when the number of sampling times becomes 16. Steps S408 to S411 are the same processing as steps S308 to S311 of FIG.

  As described above, according to the present embodiment, the battery 109 is mainly used for backup purposes, and the first IC (first processing means) 102 that operates using the battery 109 as a power source is provided. It has a DC power source 104 such as an AC adapter or a battery that is a main power source for the entire apparatus, and has a second IC (second processing means) 101 that operates using the DC power source 104 as a power source. The first IC 102 has a signal line 112 for connecting different ICs, and the first IC 102 has means for constantly monitoring the signal line 112. By monitoring the signal line 112, the operation state of the second IC 101 can be determined. Recognizing means and processing means for performing processing according to the recognized operating state.

  A mobile system having a first IC 102 that can operate constantly even when the power supply 104 is not turned on in the apparatus, and a second IC 101 that uses a DC power supply 104 supplied from the apparatus power supply as a main power supply. In the electronic apparatus, the first IC 102 monitors the signal line 112 connecting the two different ICs, thereby confirming that the second IC 101 has started up normally. Also, it is confirmed that the second IC 101 is operating normally. Further, the first IC 102 can receive a reset command from the second IC 101.

  By performing the IC monitoring, it is possible to determine whether or not the apparatus main body has started normally after turning on the power switch 105, and it is possible to take measures when the apparatus does not start normally.

  In addition, it is possible to monitor that the main unit is operating normally, and even if it encounters a so-called unauthorized power off such as sudden battery exhaustion, power outage, or pulling out of the outlet, processing according to the situation can be performed. It has become possible.

  Furthermore, there is an effect of reducing the number of signal lines by using the monitoring signal also as a reset signal line from the main body.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is a whole block diagram of the electronic device apparatus containing the IC monitoring means by embodiment of this invention. It is a flowchart which detects whether IC of the code | symbol 101 started in the IC of the code | symbol 102. FIG. 10 is a flowchart for detecting that the output from the DC voltage generation unit indicated by reference numeral 104 is suddenly turned off in the IC indicated by reference numeral 102. 10 is a flowchart for determining a reset command from the IC of reference numeral 101 in the IC of reference numeral 102; It is a whole block diagram of the conventional electronic device apparatus.

Explanation of symbols

101 Second IC
102 First IC
103 Outlet 104 DC voltage generator with output enable function 105 Power switch 106 Output enable signal 109 Backup coin battery 110 Diode 111 Power line 112 Signal line 113 Diode 114 Resistor 115 Communication line

Claims (10)

First and second processing means for performing processing;
A signal line connecting the first and second processing means,
The electronic device apparatus, wherein the first processing unit detects an operation state of the second processing unit via the signal line, and performs processing according to the operation state. The signal line is connected to a port output of the second processing means;
The second processing means outputs a predetermined voltage level from the port according to an operating state,
2. The first processing means detects an operation state of the second processing means by detecting a voltage level of the signal line, and performs processing according to the operation state. The electronic device apparatus as described. A first power source connected to the first processing means;
A second power supply for supplying power to the second processing means in response to an instruction from the first processing means,
The second processing means outputs a first level to the signal line when power is supplied from the second power source,
The first processing means recognizes that the second processing means has started normally when the signal line is at the first level within a predetermined period from a power supply instruction to the second processing means. The electronic device apparatus according to claim 1 or 2, wherein   The first processing means shifts to a power saving mode when the signal line does not become the first level within a predetermined period from a power supply instruction to the second processing means. 3. The electronic device device according to 3. The second processing means holds the signal line at the first level during operation,
5. The method according to claim 1, wherein the first processing unit recognizes that the second processing unit is operating normally while the signal line is at the first level. The electronic device apparatus of Claim 1.   6. The electronic device apparatus according to claim 5, wherein the first processing unit shifts to a power saving mode when the signal line changes from the first level to the second level.   The first processing means has storage means, and stores backup data in the storage means when the signal line changes from the first level to the second level. 5. The electronic device apparatus according to 5 or 6. The second processing means can output a reset signal to the signal line,
8. The electron according to claim 1, wherein the first processing unit applies a self-reset when a reset signal is input from the second processing unit via the signal line. 9. Equipment device.   9. The electronic device apparatus according to claim 8, wherein the reset signal is a pulse signal having a predetermined pulse width. A processing method for an electronic device having first and second processing means connected via a signal line,
The processing method of an electronic device apparatus, comprising: a step in which the first processing unit detects an operation state of the second processing unit via the signal line and performs a process according to the operation state. .

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